CN115863439A - LDMOS device and manufacturing method thereof - Google Patents
LDMOS device and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to an LDMOS device and a manufacturing method thereof. The LDMOS device comprises a substrate, a gate oxide layer, a polysilicon gate and a field plate structure. The substrate is provided with a source region, a drain region, a channel region and a drift region. The gate oxide layer is disposed on the substrate. The polysilicon gate is disposed on the gate oxide layer. The field plate structure is arranged on the gate oxide layer. The field plate structure comprises a field plate dielectric layer, a polycrystalline silicon layer and a first crystallization layer which are sequentially stacked, wherein the field plate dielectric layer is positioned between the gate oxide layer and the polycrystalline silicon layer, and the first crystallization layer is made of cobalt silicon compound. The LDMOS device forms a polycrystalline silicon layer and a first crystallization layer as an upper polar plate to form a field plate capacitor, so that a drift region is depleted, and lower Rsp and Qgd can be obtained. The field plate structure can adopt a columnar contact hole, the process difficulty of contact hole photoetching and etching can be greatly reduced, and the transverse size of the field plate structure can be larger, so that the capacitance of the field plate can be increased.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to an LDMOS device and a manufacturing method thereof.
Background
DMOS (double diffused metal oxide semiconductor field effect transistor) devices are core devices in BCD circuits, and in order to better integrate with IC mature processes, LDMOS (lateral double diffused metal oxide semiconductor field effect transistor) devices are generally used. Currently, LDMOS devices with various structures are continuously developed to achieve the purposes of improving their performance, reducing cost, increasing density, and the like.
DMOS (double diffused metal oxide semiconductor field effect transistor) devices are core devices in BCD circuits, and in order to better integrate with IC mature processes, LDMOS (lateral double diffused metal oxide semiconductor field effect transistor) devices are generally used. Currently, LDMOS devices with various structures are continuously developed to achieve the purposes of improving performance, reducing cost, increasing density, and the like.
The field plate structure is located at the core of the LDMOS device. In order to meet the requirement of voltage resistance, a thermally grown oxide layer is generally used as a field plate in the conventional LDMOS device, specifically, a region of the thermally grown oxide layer is defined first, and then thermal growth is performed. Benefits of this approach include: 1. the quality of the thermal oxidation layer is good, and the reliability is guaranteed; 2. the bird's beak can grow naturally, and the transition is gentle at the boundary of the field plate, so that the electric field intensity of the area can be smoothly distributed.
However, the thermally grown oxide layer consumes silicon surface, making the field plate not "planar" below, which results in a device with a large specific on-resistance Rsp and a large gate-to-drain charge Qgd.
Another recent field plate structure, which is mainly used in low voltage applications, is a contact hole field plate (CFP), which uses a large plate-shaped contact hole as the upper plate of the field plate capacitor, as shown in fig. 1. However, the structure needs a strip plate-shaped contact hole, and a column-shaped contact hole and the strip plate-shaped contact hole need to be simultaneously manufactured during device manufacturing, so that the process difficulty is high, and also because of the strip plate-shaped contact hole, the field plate area cannot be very large, so that the field plate capacitor cannot be large, and the application of the device under a high-voltage condition is limited.
Disclosure of Invention
Therefore, it is necessary to provide an LDMOS device and a method for manufacturing the same to reduce the specific on-resistance Rsp and the gate-drain charge Qgd of the device, and to reduce the process difficulty of device production.
One of the purposes of the present invention is to provide an LDMOS device, the scheme is as follows:
an LDMOS device comprising:
the transistor comprises a substrate, a first transistor and a second transistor, wherein the substrate is provided with a source region, a drain region, a channel region and a drift region, the channel region surrounds the source region, and the drift region surrounds the drain region;
the gate oxide layer is arranged on the substrate;
the polycrystalline silicon gate is arranged on the gate oxide layer and is positioned between the source region and the drain region; and
the field plate structure is arranged on the gate oxide layer and corresponds to the drain region, the field plate structure comprises a field plate dielectric layer, a polycrystalline silicon layer and a first crystallization layer which are sequentially stacked, the field plate dielectric layer is positioned between the gate oxide layer and the polycrystalline silicon layer, and the first crystallization layer is made of cobalt silicon compounds.
In one embodiment, the resistance of the first crystallization layer is 5 ohm/Sqr to 8 ohm/Sqr.
In one embodiment, the thickness of the field plate dielectric layer is 600A-1500A.
In one embodiment, the polysilicon layer has a thickness of 300A-1000A.
In one embodiment, the first crystalline layer has a thickness of 200A-400A.
In one embodiment, the field plate dielectric layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer which are arranged in a stacked mode.
In one embodiment, the LDMOS device further includes:
and the interlayer dielectric layer covers the gate oxide layer, the polysilicon gate and the field plate structure.
In one embodiment, the LDMOS device further includes:
and the field plate contact hole is a columnar structure which extends from one end of the interlayer dielectric layer, which is far away from the substrate, to the first crystallization layer.
In one embodiment, the LDMOS device further includes:
the metal layer is arranged on one side, far away from the substrate, of the interlayer dielectric layer and is connected with the field plate contact hole.
One of the purposes of the present invention is to provide a method for manufacturing an LDMOS device, the scheme is as follows:
a manufacturing method of an LDMOS device comprises the following steps:
providing a substrate, wherein the substrate is provided with a source region, a drain region, a channel region and a drift region, the channel region surrounds the source region, and the drift region surrounds the drain region;
manufacturing a gate oxide layer on the substrate;
manufacturing a polysilicon gate on the gate oxide layer, wherein the polysilicon gate is positioned between the source region and the drain region;
and manufacturing a field plate structure, wherein the manufacturing of the field plate dielectric layer on the gate oxide layer, the manufacturing of a polycrystalline silicon layer on the field plate dielectric layer and the manufacturing of a first crystallization layer on the polycrystalline silicon layer are carried out, the first crystallization layer is made of a cobalt silicon compound, and the field plate structure corresponds to the drain region in position.
In one embodiment, the field plate dielectric layer is fabricated by a chemical vapor deposition process.
In one embodiment, the polysilicon layer is fabricated by a furnace process.
Compared with the traditional scheme, the LDMOS device and the manufacturing method thereof have the following beneficial effects:
the LDMOS device and the manufacturing method thereof form a polycrystalline silicon layer and a first crystallization layer as an upper polar plate, the first crystallization layer adopts a low-resistance material cobalt silicon compound to form a field plate capacitor, so that a drift region is depleted, and because the capacitance values of parasitic G (gate) and D (drain) are lower, a lower specific on-resistance Rsp and a lower gate-drain charge Qgd can be obtained. Compared with a large plate-shaped contact hole field plate, the field plate structure of the LDMOS device can adopt a columnar contact hole, the process difficulty of contact hole photoetching and etching can be greatly reduced, in addition, the transverse size of the field plate structure can be larger, so that the capacitance of the field plate can be increased, the possibility of further increasing the transverse size of the field plate is increased, and the source-drain breakdown voltage BV of the LDMOS device can be further improved.
Drawings
Fig. 1 is a schematic structural diagram of a conventional LDMOS device;
FIG. 2 is a schematic structural diagram of an LDMOS device according to an embodiment of the present invention;
FIG. 3 is a layout of the LDMOS device shown in FIG. 1;
fig. 4 is a layout of the LDMOS device shown in fig. 2.
Description of reference numerals:
100. an LDMOS device; 110. a substrate; 111. a source region; 112. a drain region; 113. a channel region; 114. a drift region; 120. a gate oxide layer; 130. a polysilicon gate; 140. a field plate structure; 141. a field plate dielectric layer; 142. a polysilicon layer; 143. a first crystallization layer; 151. a field plate contact hole; 152. a source contact hole; 153. a drain contact hole; 154. a gate contact hole; 160. a metal layer; 170. a second crystalline layer; 180. a third crystallization layer; 190. and a fourth crystallization layer.
Detailed Description
In order that the invention may be more fully understood, reference will now be made to the following description. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a single embodiment.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Referring to fig. 2, an LDMOS device 100 according to an embodiment of the invention includes a substrate 110, a gate oxide 120, a polysilicon gate 130, and a field plate structure 140.
The substrate 110 has a source region 111, a drain region 112, a channel region 113, and a drift region 114. The channel region 113 surrounds the source region 111 and the drift region 114 surrounds the drain region 112. The gate oxide layer 120 is disposed on the substrate 110. A polysilicon gate 130 is disposed on the gate oxide layer 120 and between the source region 111 and the drain region 112. The field plate structure 140 is disposed on the gate oxide layer 120 and corresponds in position to the drain region 112.
Specifically, the field plate structure 140 includes a field plate dielectric layer 141, a polysilicon layer 142, and a first crystallized layer 143, which are sequentially stacked, the field plate dielectric layer 141 is located between the gate oxide layer 120 and the polysilicon layer 142, and the first crystallized layer 143 is made of cobalt silicon compound (CoSi) x ）。
The LDMOS device 100 forms the polysilicon layer 142 and the first crystallization layer 143 as the top plate, the first crystallization layer 143 uses a low-resistance material cobalt silicide to form a field plate capacitor, so that the drift region 114 is depleted, and because the capacitance values of the parasitic G (gate) and D (drain) are low, a low specific on-resistance Rsp and a low gate-drain charge Qgd can be obtained. Compared with a large plate-shaped contact hole field plate, the field plate structure 140 of the LDMOS device 100 can adopt a columnar contact hole, the process difficulty of contact hole photoetching and etching can be greatly reduced, in addition, the transverse size of the field plate structure 140 can be larger, so that the capacitance of the field plate can be increased, the possibility of further increasing the transverse size of the field plate is increased, and the source-drain breakdown voltage BV of the LDMOS device 100 can be further improved.
In one example, the resistance of the first crystallized layer 143 is 5 ohm/Sqr 8 ohm/Sqr, such as 5 ohm/Sqr, 5.5 ohm/Sqr, 6 ohm/Sqr, 6.5 ohm/Sqr, 7 ohm/Sqr, 7.5 ohm/Sqr, etc.
In one example, the field plate dielectric layer 141 includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer in a stacked arrangement.
In one example, the field plate dielectric layer 141 is fabricated by a chemical vapor deposition process.
Compared with the conventional thermal oxide layer field plate, the field plate dielectric layer 141 in the LDMOS device 100 of the above example is manufactured by a physical vapor deposition process or a chemical vapor deposition process, so that the consumption of the surface of the substrate 110 is avoided, the "planarization" of the field plate is realized, and the specific on-resistance Rsp of the device can be reduced. In addition, three thermal-grown furnace tube processes with long time for two layers of pad oxide layers and pad silicon nitride layers are reduced, and time cost and machine cost can be reduced.
In one example, the thickness of the field plate dielectric layer 141 is 600A-1500A, specifically 600A, 700A, 800A, 900A, 1000A, 1200A, 1400A, etc.
In one example, the thickness of the polysilicon layer 142 is 300A-1000A, specifically 300A, 400A, 500A, 600A, 700A, 800A, 900A, etc.
In one of these examples, the first crystallized layer 143 has a thickness of 200A-400A, such as 200A, 250A, 300A, 350A, 400A, and the like.
In one example, the LDMOS device 100 further includes an interlayer dielectric layer (not shown). The interlayer dielectric layer covers the gate oxide layer 120, the polysilicon gate 130, and the field plate structure 140.
In one example, the thickness of the interlayer dielectric layer is 3000A-8000A, specifically 3000A, 5000A, 6000A, 7000A, 8000A, etc.
Further, the LDMOS device 100 further includes a field plate contact hole 151, and the field plate contact hole 151 penetrates through the interlayer dielectric layer to the first crystallization layer 143. The LDMOS device 100 further includes a metal layer 160, and the metal layer 160 is disposed on a side of the interlayer dielectric layer away from the substrate 110 and connected to the field plate contact hole 151.
The field plate contact hole 151 is plural in number. The field plate contact hole 151 is a columnar structure extending from one end of the interlayer dielectric layer away from the substrate 110 to the first crystallization layer 143. The field plate contact hole 151 may have a polygonal, circular, or the like cross-section, for example. In a specific example, the field plate contact hole 151 has a square cross section.
Compared with the mode of forming a large plate-shaped contact hole on the contact hole field plate, the thin strip-shaped contact hole can reduce the difficulty of the manufacturing process.
It is understood that the LDMOS device 100 further includes a source contact hole 152, a drain contact hole 153, and a gate contact hole 154 formed in the interlayer dielectric layer.
In one example, the LDMOS device 100 further includes a second layer of crystallization 170. The second patterning layer 170 is disposed between the interlayer dielectric layer and the source region 111 of the substrate 110. Further, the source contact hole 152 extends from an end of the interlayer dielectric layer away from the substrate 110 to the second crystallization layer 170.
In one example, the thickness of the second crystalline layer 170 is 1500A-3000A, specifically 1500A, 1800A, 2000A, 2300A, 2600A, 2900A, 3000A, and the like.
In one example, the LDMOS device 100 further comprises a third crystallization layer 180. A third crystallization layer 180 is disposed between the interlayer dielectric layer and the drain region 112 of the substrate 110. Further, the drain contact hole 153 extends from an end of the interlayer dielectric layer away from the substrate 110 to the third crystallization layer 180.
In one example, the LDMOS device 100 further comprises a fourth crystallization layer 190. A fourth crystallization layer 190 is disposed between the interlayer dielectric layer and the gate polysilicon 130. Further, the gate contact hole 154 extends from an end of the interlayer dielectric layer away from the substrate 110 to the fourth crystallization layer 190.
The first, second, third and fourth crystallization layers 143, 170, 180, 190 may be formed in the same process, and may be made of cobalt silicide (CoSix).
Further, the present invention also provides a method for manufacturing the LDMOS device 100 of any of the above examples, including the following steps:
step S1, a substrate 110 is provided, and the substrate 110 has a source region 111, a drain region 112, a channel region 113, and a drift region 114. The channel region 113 surrounds the source region 111 and the drift region 114 surrounds the drain region 112.
Step S2, a gate oxide layer 120 is fabricated on the substrate 110.
Step S3, a polysilicon gate 130 is fabricated on the gate oxide layer 120, and the polysilicon gate 130 is located between the source region 111 and the drain region 112.
Step S4, fabricating a field plate structure 140, including fabricating a field plate dielectric layer 141 on the gate oxide layer 120, fabricating a polysilicon layer 142 on the field plate dielectric layer 141, and fabricating a first crystallization layer 143 on the polysilicon layer 142, where the field plate structure 140 corresponds to the drain region 112.
The method for manufacturing the LDMOS device 100 forms the polysilicon layer 142 and the first crystallized layer 143 as the upper plate, the first crystallized layer 143 uses a low-resistance material cobalt silicide to form a field plate capacitor, so that the drift region 114 is depleted, and a lower on-resistance Rsp and a gate-drain charge Qgd can be obtained. Compared with a large plate-shaped contact hole field plate, the field plate structure 140 of the LDMOS device 100 can adopt a columnar contact hole, the process difficulty of contact hole photoetching and etching can be greatly reduced, in addition, the transverse size of the field plate structure 140 can be larger, so that the capacitance of the field plate can be increased, the possibility of further increasing the transverse size of the field plate is increased, and the source-drain breakdown voltage BV of the LDMOS device 100 can be further improved.
In one example, in step S4, the field plate dielectric layer 141 is fabricated by a physical vapor deposition process or a chemical vapor deposition process.
Compared with the conventional thermal oxide layer field plate, the field plate dielectric layer 141 in the LDMOS device 100 of the above example is manufactured by a physical vapor deposition process or a chemical vapor deposition process, so that the consumption of the surface of the substrate 110 is avoided, the "planarization" of the field plate is realized, and the specific on-resistance Rsp of the device can be reduced. In addition, three thermal-grown furnace tube processes with long time for two layers of pad oxide layers and pad silicon nitride layers are reduced, and time cost and machine cost can be reduced.
In one example, in step S4, the field plate dielectric layer 141 and the polysilicon layer 142 are deposited over the entire surface. Further, before the first crystallized layer 143 is formed, the field plate dielectric layer 141 and the polysilicon layer 142 in the remaining region are removed by photolithography and etching processes, and only the field plate dielectric layer 141 and the polysilicon layer 142 corresponding to the drain region 112 are remained.
In one example, the Critical Dimension (CD) of the photolithography process is 0.15 μm to 1.2 μm, and a positive photoresist of KrF (light source 248 nm) type is used. The thickness of the photoresist is 5000-20000A.
In one example, the etching process includes dry etching and wet etching.
The polysilicon layer 142 in the rest area is removed by dry etching, and the polysilicon layer remains in the field plate dielectric layer 141 below the polysilicon layer 142 after etching, for example, the residual thickness of the field plate dielectric layer 141 is 50A-200A.
And removing the residual field plate dielectric layer 141 in the rest area by wet etching, wherein the loss of the polysilicon below the field plate dielectric layer 141 is below 20A.
Fig. 3 shows a reticle layout 20 for an LDMOS device employing a contact hole field plate. Where region 21 corresponds to the region of the source contact hole, region 22 corresponds to the region of the drain contact hole, region 23 corresponds to the region of the polysilicon gate, region 24 corresponds to the region of the gate contact hole, region 25 corresponds to the region of the contact field plate, region 26 corresponds to the region of the crystalline layer on the source, and region 27 corresponds to the region of the crystalline layer on the drain.
Fig. 4 shows a reticle layout 30 of an LDMOS device according to an embodiment of the invention. Region 31 corresponds to the region of the source contact hole, region 32 corresponds to the region of the drain contact hole, region 33 corresponds to the region of the polysilicon gate, region 34 corresponds to the region of the gate contact hole, region 35 corresponds to the region of the field plate structure, region 36 corresponds to the region of the field plate contact hole, region 37 corresponds to the region of the second layer of transistors, and region 38 corresponds to the region of the third layer of transistors.
Compared with the photomask layout 20 of the traditional device, the photomask layout 30 of the LDMOS device is generalBy adding a light shield corresponding to the field plate structure region, the pattern of the field plate contact hole can be changed from a long strip shape to a square hole shape, and the whole layout only has the contact hole with the square hole shape, so that the process difficulty of contact hole photoetching and etching can be greatly reduced. Meanwhile, the transverse dimension O of the field plate structure is convenient to be adjusted 2 Is made larger so as to increase the capacitance of the field plate and further increase the lateral dimension O of the field plate 2 The source-drain breakdown voltage BV of such an LDMOS device may be further increased.
The LDMOS device and the method for manufacturing the LDMOS device of the present invention are further described with an embodiment.
The LDMOS device of a specific embodiment comprises a substrate, a gate oxide layer, a polysilicon gate, a field plate structure, an interlayer dielectric layer, a contact hole and a metal layer.
The substrate is provided with a source region, a drain region, a channel region and a drift region. The channel region surrounds the source region and the drift region surrounds the drain region. The gate oxide layer is disposed on the substrate. The polysilicon gate is arranged on the gate oxide layer and is positioned between the source region and the drain region. And side walls are respectively arranged on two sides of the polysilicon gate.
The field plate structure is arranged on the gate oxide layer and corresponds to the drain region. The field plate structure comprises a field plate dielectric layer, a polycrystalline silicon layer and a first crystallization layer which are sequentially stacked, wherein the field plate dielectric layer is positioned between the gate oxide layer and the polycrystalline silicon layer.
The interlayer dielectric layer covers the gate oxide layer, the polysilicon gate and the field plate structure. And a second crystallization layer is arranged between the interlayer dielectric layer and the source region of the substrate. And a third crystallization layer is arranged between the interlayer dielectric layer and the drain region of the substrate. And a fourth crystallization layer is arranged between the interlayer dielectric layer and the polysilicon gate.
The contact holes comprise a field plate contact hole, a source electrode contact hole, a drain electrode contact hole and a grid electrode contact hole. The field plate contact hole is a columnar structure which extends from one end, far away from the substrate, of the interlayer dielectric layer to the first crystallization layer. The source contact hole extends from one end of the interlayer dielectric layer far away from the substrate to the second crystal layer. The drain contact hole extends from one end of the interlayer dielectric layer far away from the substrate to the third crystallization layer. The grid contact hole extends from one end of the interlayer dielectric layer far away from the substrate to the fourth crystallization layer.
The metal layer is arranged on one side of the interlayer dielectric layer far away from the substrate and is connected with the field plate contact hole, the source electrode contact hole, the drain electrode contact hole and the grid electrode contact hole.
The manufacturing method of the LDMOS device comprises the following steps:
step 1, providing a silicon substrate, and performing ion implantation on the silicon substrate to form a source region, a drain region, a channel region and a drift region, wherein the channel region surrounds the source region, and the drift region surrounds the drain region, so as to obtain a substrate.
And 2, manufacturing a gate oxide layer on the substrate.
And 3, manufacturing a polysilicon gate on the gate oxide layer, wherein the polysilicon gate is positioned between the source region and the drain region, and manufacturing side walls on two sides of the polysilicon gate.
And 4, sequentially depositing silicon oxide, silicon nitride and silicon oxide on the gate oxide layer to form a dielectric material layer.
And 5, depositing polycrystalline silicon on the dielectric material layer to form a polycrystalline silicon material layer.
And 6, forming a photoresist layer on the region of the polycrystalline silicon material layer corresponding to the drain region by adopting a photoetching process through operations of gluing, exposing, developing and the like. The Critical Dimension (CD) of the photoetching process is 0.15-1.2 mu m. The light resistance layer is KrF (light source 248 nm) positive light resistance with a thickness of 10000A.
And 7, removing the dielectric material layer and the polycrystalline silicon material layer in the rest area by adopting an etching process, and only keeping the dielectric material layer and the polycrystalline silicon material layer corresponding to the drain area. Specifically, the polysilicon layer in the remaining region is removed by dry etching using halogen and CF 4 The gas acts as the main etch gas, and the etch depth is controlled by obtaining the EPD signal. And staying in the silicon oxide material layer after etching, wherein the residual thickness is 50-200A. And further performing wet etching by using HF (hydrogen fluoride), and removing the residual dielectric material layer in the rest area, wherein the loss of the polycrystalline silicon below the dielectric material layer is below 20A. Thus, a field plate dielectric layer and a polysilicon layer corresponding to the drain region are formed.
And 8, depositing a cobalt silicon compound on the polycrystalline silicon layer to form a crystallization layer.
And 9, manufacturing an interlayer dielectric layer, wherein the interlayer dielectric layer covers the gate oxide layer, the polysilicon gate and the field plate structure.
And step 10, manufacturing a field plate contact hole, a source electrode contact hole, a drain electrode contact hole and a grid electrode contact hole.
And 11, manufacturing a metal layer on one side of the interlayer dielectric layer, which is far away from the substrate, and connecting the metal layer with the field plate contact hole, the source electrode contact hole, the drain electrode contact hole and the grid electrode contact hole.
Compared with the conventional thermal oxide field plate device, the LDMOS device of the above embodiment has the following advantages:
(1) The layout area is reduced, and for example, the layout area can be reduced by 5-20% by taking a 0.18 mu m technical node as an example.
(2) The consumption of the substrate surface is avoided, the planarization of the field plate is realized, and the specific on-resistance Rsp of the device can be reduced. Taking a 0.18 μm technology node as an example, rsp can be reduced by 10% -35% (specifically related to field plate length and channel length) due to the reduction of current path.
(3) The process difficulty and the production cost are reduced. Three thermal growth furnace tube processes (a pad oxide layer and a pad silicon nitride layer) with longer time are reduced, and the time cost and the machine cost can be reduced.
(4) The performance of the device is improved: qgd is reduced, increasing the speed of the device.
Compared with the device of the contact hole field plate, the LDMOS device of the embodiment has the following advantages:
(1) And the difficulty of the contact hole manufacturing process is reduced.
(2) The possibility of making the field plate area large is increased, so that the possibility of using the LDMOS device under high voltage can be improved.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An LDMOS device, comprising:
the transistor comprises a substrate, a source region, a drain region, a channel region and a drift region, wherein the channel region surrounds the source region, and the drift region surrounds the drain region;
the gate oxide layer is arranged on the substrate;
the polysilicon gate is arranged on the gate oxide layer and is positioned between the source region and the drain region; and
the field plate structure is arranged on the gate oxide layer and corresponds to the drain region, the field plate structure comprises a field plate dielectric layer, a polycrystalline silicon layer and a first crystallization layer which are sequentially stacked, the field plate dielectric layer is positioned between the gate oxide layer and the polycrystalline silicon layer, and the first crystallization layer is made of cobalt silicon compounds.
2. The LDMOS device of claim 1, wherein the first crystallized layer has a resistance of 5-8 ohm/Sqr.
3. The LDMOS device of claim 1, wherein the first crystalline layer has a thickness of 200A-400A.
4. The LDMOS device of claim 1, wherein the field plate dielectric layer has a thickness of 600A-1500A.
5. The LDMOS device of claim 1, wherein the polysilicon layer has a thickness of 300A-1000A.
6. The LDMOS device of claim 1, wherein the field plate dielectric layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer which are arranged in a stack.
7. The LDMOS device of any one of claims 1-6, further comprising:
and the interlayer dielectric layer covers the gate oxide layer, the polysilicon gate and the field plate structure.
8. The LDMOS device of claim 7, further comprising:
and the field plate contact hole is a columnar structure which extends from one end of the interlayer dielectric layer, which is far away from the substrate, to the first crystallization layer.
9. The LDMOS device of claim 8, further comprising:
the metal layer is arranged on one side, far away from the substrate, of the interlayer dielectric layer and is connected with the field plate contact hole.
10. A manufacturing method of an LDMOS device is characterized by comprising the following steps:
providing a substrate, wherein the substrate is provided with a source region, a drain region, a channel region and a drift region, the channel region surrounds the source region, and the drift region surrounds the drain region;
manufacturing a gate oxide layer on the substrate;
manufacturing a polysilicon gate on the gate oxide layer, wherein the polysilicon gate is positioned between the source region and the drain region;
and manufacturing a field plate structure, wherein the manufacturing of the field plate dielectric layer on the gate oxide layer, the manufacturing of a polycrystalline silicon layer on the field plate dielectric layer and the manufacturing of a first crystallization layer on the polycrystalline silicon layer are carried out, the first crystallization layer is made of a cobalt silicon compound, and the field plate structure corresponds to the drain region in position.
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