TW502333B - Method for fabricating semiconductor devices - Google Patents
Method for fabricating semiconductor devices Download PDFInfo
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- TW502333B TW502333B TW090113973A TW90113973A TW502333B TW 502333 B TW502333 B TW 502333B TW 090113973 A TW090113973 A TW 090113973A TW 90113973 A TW90113973 A TW 90113973A TW 502333 B TW502333 B TW 502333B
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- Prior art keywords
- seed layer
- base member
- plating
- film
- plating seed
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 70
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000007747 plating Methods 0.000 claims abstract description 68
- 238000005498 polishing Methods 0.000 claims abstract description 60
- 239000012530 fluid Substances 0.000 claims abstract description 48
- 239000010408 film Substances 0.000 claims description 85
- 238000009713 electroplating Methods 0.000 claims description 35
- 238000004519 manufacturing process Methods 0.000 claims description 27
- 238000007789 sealing Methods 0.000 claims description 22
- 230000004888 barrier function Effects 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 16
- 239000013078 crystal Substances 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 6
- 230000002079 cooperative effect Effects 0.000 claims 3
- 238000003825 pressing Methods 0.000 claims 2
- 235000012054 meals Nutrition 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 238000007517 polishing process Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 69
- 239000002585 base Substances 0.000 description 41
- 239000000463 material Substances 0.000 description 33
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 16
- 229910052802 copper Inorganic materials 0.000 description 16
- 239000010949 copper Substances 0.000 description 16
- 239000000243 solution Substances 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 7
- 229910000831 Steel Inorganic materials 0.000 description 6
- 230000000717 retained effect Effects 0.000 description 6
- 239000010959 steel Substances 0.000 description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- -1 tungsten nitride Chemical class 0.000 description 4
- 238000005868 electrolysis reaction Methods 0.000 description 3
- 239000003480 eluent Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- NLXLAEXVIDQMFP-UHFFFAOYSA-N Ammonia chloride Chemical compound [NH4+].[Cl-] NLXLAEXVIDQMFP-UHFFFAOYSA-N 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000005484 gravity Effects 0.000 description 2
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 2
- 150000003839 salts Chemical class 0.000 description 2
- PAWQVTBBRAZDMG-UHFFFAOYSA-N 2-(3-bromo-2-fluorophenyl)acetic acid Chemical compound OC(=O)CC1=CC=CC(Br)=C1F PAWQVTBBRAZDMG-UHFFFAOYSA-N 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 235000010627 Phaseolus vulgaris Nutrition 0.000 description 1
- 244000046052 Phaseolus vulgaris Species 0.000 description 1
- 241001674048 Phthiraptera Species 0.000 description 1
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 1
- YZCKVEUIGOORGS-NJFSPNSNSA-N Tritium Chemical compound [3H] YZCKVEUIGOORGS-NJFSPNSNSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 235000019270 ammonium chloride Nutrition 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000008280 blood Substances 0.000 description 1
- 210000004369 blood Anatomy 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 125000001309 chloro group Chemical class Cl* 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- OMBRFUXPXNIUCZ-UHFFFAOYSA-N dioxidonitrogen(1+) Chemical compound O=[N+]=O OMBRFUXPXNIUCZ-UHFFFAOYSA-N 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- IDBFBDSKYCUNPW-UHFFFAOYSA-N lithium nitride Chemical compound [Li]N([Li])[Li] IDBFBDSKYCUNPW-UHFFFAOYSA-N 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052700 potassium Inorganic materials 0.000 description 1
- 239000011591 potassium Substances 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 229910052722 tritium Inorganic materials 0.000 description 1
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 1
- 238000009941 weaving Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
Description
五、發明說明（1 發明背景 1 ·發明領域 2明有關-種製造半導體裝置之方法，尤其有關—種 k半導體裝置之方法，其中藉雙重全屬 層線路結構。 ㈣成多 2 ’相關技藝描述 鋁合金廣泛地被使用爲LSIS切路㈣。“，在近來 LSIs縮小尺寸及其操作加速之下，該種鋁合八 =確保：充分之性質(高可信度及低電阻係數)。解：此種V. Description of the Invention (1 Background of the Invention 1) Field of Invention 2 relates to a method for manufacturing a semiconductor device, and more particularly to a method for a k semiconductor device, in which a dual full-layer circuit structure is borrowed. ㈣ 成 多 2 'Related technical description Aluminum alloys are widely used as LLSI cutouts. "Under the recent downsizing of LSIs and the acceleration of their operation, this type of aluminum alloy = ensures: sufficient properties (high reliability and low resistivity). Solutions: This kind
Si 在於電遷移阻力較綠合金線路優越且電 阻係數較低之銅線路，已被導用於部分半導體裝 +該鋼佈線程序中，認爲溝槽式佈線較爲"^爲鋼通 常較不易猎乾式姓刻加工。在溝槽式佈線時，於 氧切所製之絕緣薄膜中形成預定槽溝二由— 填佈線材料，之糊如化學機械峰川=== 除該佈線材料的多餘部分，以於該溝槽内形成線路。， 於溝槽式佈線方法—進行研究者—中充、 係包括電解電鍍方法、化學 Η 7 ””的万法 、織逆流…方法:積万法(以下簡稱爲⑽) A u 4、.且口万法、咼壓逆流方法、 法。其中，.最近製造半道俨劈W &1 及”，'电电鍍万 速率、薄膜开m 針對於薄膜形成 成成本、所得金屬薄膜之純度及黏著性“ 行無電電鍍方法。 f H而進 以下描述使用血雷當祐士 於該溝槽及連接孔中的;·;^’。將作爲佈線材料之鋼充填 502333 A7Si is a copper circuit with better electromigration resistance than green alloy circuits and lower resistivity. It has been used in some semiconductor equipment + this steel wiring procedure, and it is considered that trench wiring is more difficult. Hunting dry type engraving processing. In the trench wiring, a predetermined trench is formed in the insulating film made by oxygen cutting. The filling material is filled with a wiring material, such as a chemical mechanical peak. === Except for the excess portion of the wiring material, the trench Form a line inside. For the trench wiring method—researcher—Zhongchong, including electrolytic plating method, chemical method 7 ”” method, weaving counter current… method: product method (hereinafter referred to as ⑽) A u 4, and Mouth method, pressure countercurrent method, method. Among them, recently, half-way manufacturing W & 1 and "," Electro-plating speed, film opening m "aim at the film formation cost, the purity and adhesion of the resulting metal film" Electroless plating method. f H 进 进 The following description uses the blood thunder as a protector in the groove and the connecting hole; ·; ^ '. Fill steel as wiring material 502333 A7
於位在基件上的中間層絕緣薄膜中形成溝槽。於該中間 層絕緣薄膜上及於該溝槽之内表面上，藉濺鍍形成一障壁 層，一般包括30毫微米厚的氮化鋰（TaN)薄膜。障壁層係= 以防止銅擴散至由二氧切薄膜製得之中間層絕料膜中 其八，一般包括1 50耄微米厚之銅薄膜的電鍍種晶層係藉 濺鍍而形成於該電鍍種晶層上。該電鍍種晶層係作爲經： 連續電解電鍍幫助銅層生長的種晶層。 二 其次，於Μ電鍍種晶層表面上，藉電鍍生長鋼薄膜，以 无填該溝槽，以覆蓋該中間層絕緣薄膜，同時夹置以該产 壁層。 μ早 裝 訂A trench is formed in the interlayer insulating film on the base member. A barrier layer is formed on the interlayer insulating film and on the inner surface of the trench by sputtering, and generally includes a 30 nm thick lithium nitride (TaN) film. Barrier layer system = In order to prevent copper from diffusing into the interlayer insulation film made of dioxy-cut film, the plating seed layer, which generally includes a copper film of 150 耄 micron thickness, is formed on the plating by sputtering Seed layer. The plating seed layer serves as a seed layer through which continuous electrolytic plating helps the copper layer to grow. Secondly, on the surface of the M plating seed layer, a steel film is grown by electroplating to fill the trench without covering the interlayer insulating film, while sandwiching the wall-forming layer. μ early binding
線 該銅膜位於中間層絕緣薄膜上的多餘部分被移除，以形 成線路。雖然該移除通常係採用CMP，但可另外採用_種 其中精電鍍形成之銅薄膜藉電解拋光進行回蝕的方法。該 電解拋光意指一種拋光方法，其巾金屬表面係於特定溶液 中於陽極側面上溶解，以得到光滑且具光澤之表面。傳統 採用電解拋光，主要用以去除鋁或不銹鋼之粗糙物及 提高表面光澤度，且用以預處理銅或銅合金的電鍍。 當該電解拋光方法使用於晶圓程.序中時，需使^極⑴與 預先形成於晶圓101上的電鍍種晶層1〇3接觸，同時夾置 障壁層102，如圖3A所示。某些情況下，亦需使用密封元. 件（例如〇形環）密封該晶圓101的外緣部分，以避免2接觸 之電極11 1與電解拋光流體1 2 1之間接觸。 然而，此種.情況使得在電解拋光完成之後，電鍍種晶層 1〇3殘留於未與該電解拋光流體（未示）接觸之部分^The excess portion of the copper film on the interlayer insulating film is removed to form a line. Although the removal is usually performed by CMP, a method in which a copper film formed by fine plating is etched back by electrolytic polishing may be additionally used. The electrolytic polishing means a polishing method in which the metal surface of the towel is dissolved in a specific solution on the side of the anode to obtain a smooth and shiny surface. Traditionally, electrolytic polishing is used to remove the roughness of aluminum or stainless steel and improve the surface gloss. It is also used to pretreat the electroplating of copper or copper alloys. When the electrolytic polishing method is used in a wafer process, the electrode layer needs to be brought into contact with the plating seed layer 10 formed on the wafer 101 in advance, and the barrier layer 102 is sandwiched, as shown in FIG. 3A . In some cases, it is also necessary to use a sealing element (such as an O-ring) to seal the outer edge portion of the wafer 101 to avoid contact between the 2 contacting electrode 11 1 and the electrolytic polishing fluid 1 2 1. However, in this case, after the electrolytic polishing is completed, the electroplating seed layer 103 remains in a portion that is not in contact with the electrolytic polishing fluid (not shown) ^
502333 A7 B7 五、發明説明（ 被電極1 π所遮蓋或位於晶圓101之外緣部分上者，如圖3B 所示。此種殘留之電鍍種晶層103係該晶圓1〇1之外緣部分 上產生高値高度差的主因。 於後續程序步驟中形成絕緣薄膜104因爲殘留之種晶層 103的圖型邊緣而於該絕緣薄膜104之表面上形成高値階梯 部分S，如圖3C所示。此種情況需要另一個使該缒緣薄膜 10 4之表面平坦化的程序步.驟。移除該階梯度部分s的失敗 係後續形成於其上層之線路剝離的主因。 發明概述 如前文所述，晶圓範疇中殘留之金屬佈線材料導致各式 各樣之缺點，諸如線路間之短路及階梯部分覆蓋性變差。 因此’本發明之目的係提出一種用以解決前述問題的半 導體裝置製造方法。 本發明之一具體實例的第一種製造半導體裝置的方法係 包括以下步壤：於基件（例如晶圓）上形成一電鍍種晶層； 藉私鍍方法於该電鍍種晶層上，除該基件之外緣部分以外 的區域中’形成一電鍍薄膜；使用電解拋光方法拋光該電 鍵薄膜’同時拋光該電鍍種晶層；及選擇性地移除殘留於 該基件之外緣部分上的電鍍種晶層。 琢第一種製造半導體裝置之方法具有選擇性地移除殘留 方；#基件之外緣邵分上的電鍍種晶層之步驟，故該電鍍種 曰曰層絕對不會電解拋光之後殘留於該基件表面上與使用於 $電解抛光之電極接觸的部分中，而符合期望地縮小該基 件（平面内高度差。此種在電解拋光之後縮小平面内高度 :297公釐） 502333 A7 B7 五、發明説明（4 ) 差的方式及此種移除構成該佈線材料薄膜之電鍍薄膜及電 鍵種晶層之非必要部分的方式可成功的提高半導體裝置之 良率比例，·可免除在長晶之後藉CMP將絕緣薄膜平面化的 必要性，而降低製造成本。 本發明另一具體實例的第二種製造半導體裝置的方法係 包括以下步驟：於該基件上形成一電鍍種晶層；藉電鍍方 法’於該電鍍種晶層上，在除該基件外緣部分以外的區域 中，形成電鍍之薄膜；藉蝕刻移除位於該基件外緣部分上 的電鍍種晶層；及使用電解拋光方法拋光該電鍍之薄膜， 同時拋光該電鍍種晶層。 該第二種製造半導體裝置的方法具有藉蝕刻移除位於該 基件之外緣部分上的電鍍種晶層的步驟，使得該電鍍種晶 層始終不會在電解拋光之後殘留於該基件的表面上，符合 期望地縮小該基件之平面内高度差。此種在電解拋光之後 、，宿小平面内问度差的方式及此種移除構成該佈線材料薄膜 之電鍍薄膜及電鍍種晶層之非必要部分的方式可成功的提 高半導體裝置之良率比例，可免除在長晶之後藉CMp將絕 緣薄膜平面化的必要性，因而降低製造成本。 圖式簡單說明 參照附圖.，由以下本發明較佳例示具體實例的插述可進 -步明瞭本發明之前述及其他目的、特色及優點，其中： 圖1A至1F係爲部分剖面圖，出示本發明第一種製造半導 月豆I置之方法的具體實例中之程序步驟； 圖2 A 土 2F係#分剖面圖，出示本發明第二種製造半導體502333 A7 B7 V. Description of the invention (The one covered by the electrode 1 π or located on the outer edge of the wafer 101, as shown in Figure 3B. This residual plating seed layer 103 is outside the wafer 101 The main cause of the difference in height between the edge and the edge is the formation of a high-profile step S on the surface of the insulating film 104 due to the pattern edge of the seed layer 103 remaining on the insulating film 104 in the subsequent program steps, as shown in FIG. 3C. In this case, another process step is required to flatten the surface of the edge film 104. The failure to remove the stepped portion s is the main cause of the subsequent stripping of the upper layer of the circuit. Summary of the Invention It is stated that the remaining metal wiring materials in the wafer category cause various disadvantages, such as short circuits between lines and poor coverage of the stepped portion. Therefore, the object of the present invention is to propose a semiconductor device manufacturing to solve the aforementioned problems. Method The first method for manufacturing a semiconductor device according to a specific embodiment of the present invention includes the following steps: forming a plating seed layer on a substrate (such as a wafer); On the electroplated seed layer, an electroplated film is formed in a region other than the outer edge portion of the base member; the electro-chemical polishing method is used to polish the key film while polishing the electroplated seed layer; and selectively remove the remaining The plating seed layer on the outer edge portion of the base member. The first method of manufacturing a semiconductor device has a selective removal of the remaining squares; the step of plating the seed layer on the outer edge of the base member, so The electroplating seed layer will never remain in the part on the surface of the base member in contact with the electrode used for electrolytic polishing after electrolytic polishing, and it is expected to reduce the base member (the height difference in the plane. This kind of electrolysis Reduce the in-plane height after polishing: 297 mm) 502333 A7 B7 V. Description of the invention (4) The poor method and the way to remove the unnecessary parts of the plating film and the key seed layer that constitute the wiring material film can be successful To improve the yield ratio of the semiconductor device, the need to planarize the insulating film by CMP after growing the crystal can be eliminated, and the manufacturing cost can be reduced. The second manufacturing method of another specific example of the present invention The method of the conductor device includes the following steps: forming a plating seed layer on the substrate; and forming a plated film on the plating seed layer by the plating method in an area other than the outer edge portion of the substrate ; Removing the plating seed layer on the outer edge portion of the base member by etching; and polishing the plated film using an electrolytic polishing method while polishing the plating seed layer. The second method of manufacturing a semiconductor device includes etching by etching The step of removing the plating seed layer on the outer edge portion of the base member, so that the plating seed layer will never remain on the surface of the base member after electrolytic polishing, and the plane of the base member is desirably reduced. Internal height difference. After electrolytic polishing, this method of poor interfacial surface and this method of removing unnecessary parts of the plating film and plating seed layer that constitute the wiring material film can successfully improve the semiconductor. The yield ratio of the device can eliminate the necessity of planarizing the insulating film by CMP after growing the crystal, thereby reducing the manufacturing cost. The drawings are briefly explained with reference to the drawings. The foregoing and other objects, features, and advantages of the present invention can be further clarified by the following examples of specific examples of the present invention, of which: FIGS. 1A to 1F are partial cross-sectional views, Show the procedure steps in the concrete example of the first method for manufacturing semiconducting moon beans of the present invention; FIG. 2 A Soil 2F series # sectional view showing the second manufacturing semiconductor of the present invention
502333 五 、發明說明（5 A7 B7 裝置之方法的具體實例中之程序步驟：且 圖从至3C係爲出π相關技藝中之問題的部分剖面圖。 較佳具體實例描述 以下參照圖1Α至1F說明本發明第一種製造半導髀牡詈 之方法的具體實例’該圖係爲出示其程序步驟：：：： 面圖。 雖未出示，但將預定裝置製造於一基材（例如半道邮基 内’之後於其上層形成中間層絕緣薄膜。於其上 ·=如形成在預定位置上具有開口的光阻圖型，而該中間層 絕緣薄膜隨後使用該光阻圖型作爲蝕刻罩幕而進行蚀刻， 以形成佈線溝槽。隨之移除該光阻圖型。 其次，如圖1Α所示，一般包括氮化鎢薄膜之障壁層以係 藉例如CVD方法形成於該經處理基件丨丨上。該氮化鎢薄膜 之形成一般可使用7Τ氟化鎢（WF6)、氮（ν2)及氫（η2)之混合 氣體作爲來源氣體，該來源氣體之流速條件係爲〇 25毫升/ 分鐘，而薄膜生成溫度係300至40CTC。 其次’用以於電鍍中幫助長晶之電鍍種晶層22係使用藉 物理氣相沉積（PVD)方法諸如濺鍍生成之銅薄膜形成。該銅 薄膜之生長一般可採用氬（Ar)作爲程序氣體，其條件係爲濺 鍍裝置之DC能量係爲12仟瓦，程序氣體流速係爲50厘米3/ 分鐘，薄膜生長氛圍之壓力係爲0.2帕司卡，而薄膜生長溫 度係爲100°C。 其次，如圖1B所示，藉電鍍於該電鍍種晶層22上沉積 厚度一般爲1 · 0微米之銅薄膜，以形成完全充填前述佈線 本紙張尺度適用中國國家標準(CNS) A4规格(210X297公釐) 502333 A7 ____B7 五、發明説明（6 ) 溝才曰（未示）之電鍍層23。該電鍍種晶層22及電鍍之薄膜23 現在一起構成一佈線材料薄膜24。該電鍍係於在基件丨丨側 面上具有凹陷之帽罩41與該基件1丨之間保持電鍍流體5丨的 情況下進行。於此種結構之下，密封元件（例如〇形環）42係 提供於該基件Π之外緣部分與該帽罩41之外緣之間，以避 免該電鍍流體5 1向著該基件Π之後表面洩漏，並保持陰極 3 1遠離該電鍍流體5 1。該陰極3 1係與該電鍍種晶層22接觸 。因爲該基件11與進料電鍍流體5 1之間隔係使用帽罩4丨及 密封元件42密封，故保留於該基件11與該帽罩41之間的電 鍍泥體5 1不會向外洩漏。因此，所電鏡之薄膜23僅生長於 位於該密封元件42内側之區域中。 該電鍍一般可採用硫酸銅-鹼電鍍流體作爲電鍍流體，其 條件係爲電鍍電流2.83埃，長晶速率係爲4·5分鐘每1微米薄 膜生長，及18°C之流體溫度。 其次，如圖1C所示，佈線材料薄轉24(參照圖1B)係進行 電解拋光，同時提供電解拋光流體61於介於該基件丨丨與該 中目罩43間之間隔内’以僅於該佈線溝槽（未示）中留下該佈線 材料薄膜24，因而完成該溝槽佈線（未示）。該電解拋光係在 使電解拋光流體6 1保持介於在基件丨丨之側面上具有凹陷之 帽罩43與該基件11之間的條件下進行。於該結構下，密封 元件（例如Ο形環）44提供於該基件11之外緣部分與該帽罩43 足外緣之間，以避免該電解拋光流體6丨向著該基件丨丨之後 表面戍漏，並保持陰極32遠離該電解拋光流體61。該陰極 3 2係轉黾鍵種晶層2 2接觸。因爲位於該基件11上進料該電 -9 - 本紙張尺度適财@ @家標準(CNS) A4規格(21GX 297公董） —-- 502333 A7 _ __B7__ 五、發明説明（7 ) 解拋光流體6 1之間隔係使用帽罩43及密封元件44密封，故 保留於該基件1 1與該帽罩43之間的電解拋光流體6 1不會向 外洩漏。因·此，僅拋光位於該密封元件44内側之區域中的 佈線材料薄膜24(參照圖1B)。該電鍍種晶層22位於該密封 元件44外側之部分（參照圖1C)於該基件丨丨上保持未拋光， 如圖1D所示。現在已知該帽罩43及該密封元件44可爲供電 鍍使用者。 該電解拋光一般可採用磷酸（比重=1.6)溶液作爲拋光流體 ’其條件係電流密度5至20A/dm2，且拋光溫度係1 5至25°C。 該種電解拋光中，當位於該範疇中之佈線材料薄膜24被耗 盡時，電流開始流經電導係數低於銅薄膜之障壁層2 1，故 該佈線材料薄膜24可保持其電導係數高於邊緣部分，使得 該佈線材料薄膜24可輕易地被蚀刻。因此，可幾乎完全且 均勻地移除位於該範疇中的佈線材料薄膜24。 其次’殘留於該基件11之外緣部分上的電鍍種晶層22係 藉著選擇性地提供銅所使用之蚀刻流體而移除。 氯化鐵蚀刻溶液一般可作爲供銅使用之蝕刻流體，其含 有340至380克/升之氣化鐵（此情況下例如“ο克/升）及5至6〇 毫升鹽fe (此情 >兄下例如3 0毫升）。該钱刻流體之溫度可爲$ 〇 至70°C。此實施例中，採用50°c之溫度。 亦可使用氯化鋼溶液，其可含有50至200克/升之氣化鋼（此 情況下爲例如100克/升），2至50毫升之鹽酸（此情況下例如 10毫升），及5至70克/升之氣化鉀(此情況下例如扣克/升）。 該触刻流體之溫度可爲20至70X：。此實施例中，採用5(rc502333 V. Description of the invention (5 A7 B7 device method in the specific example of the program steps: and the figure from 3C is a partial cross-sectional view of the problems related to π. The preferred specific example is described below with reference to FIGS. 1A to 1F Describe a specific example of the first method for manufacturing a semiconducting clam according to the present invention. 'This drawing is to show its procedure steps: ::: top view. Although it is not shown, a predetermined device is manufactured on a substrate (for example, halfway). In the post, an intermediate layer insulating film is formed on the upper layer. On top of it, a photoresist pattern having an opening at a predetermined position is formed, and the intermediate layer insulating film subsequently uses the photoresist pattern as an etching mask. Etching is performed to form wiring trenches. The photoresist pattern is subsequently removed. Next, as shown in FIG. 1A, a barrier layer generally including a tungsten nitride film is formed on the processed substrate by, for example, a CVD method.丨 丨. The formation of the tungsten nitride film can generally use a mixed gas of 7T tungsten fluoride (WF6), nitrogen (ν2) and hydrogen (η2) as the source gas, and the flow rate condition of the source gas is 0.25 ml / Minutes while The film formation temperature is 300 to 40 CTC. Secondly, the electroplated seed layer 22 used to help grow the crystals in the electroplating is formed using a copper thin film formed by a physical vapor deposition (PVD) method such as sputtering. The growth of the copper thin film is generally Argon (Ar) can be used as the program gas, the conditions are that the DC energy of the sputtering device is 12 watts, the flow rate of the program gas is 50 cm3 / min, and the pressure of the film growth atmosphere is 0.2 Pascal, and The film growth temperature is 100 ° C. Second, as shown in FIG. 1B, a copper film with a thickness of generally 1.0 micron is deposited on the plating seed layer 22 by electroplating to form a complete filling of the aforementioned wiring. This paper is suitable for China National Standard (CNS) A4 specification (210X297 mm) 502333 A7 ____B7 V. Description of the invention (6) Gou Cai said (not shown) plating layer 23. The plating seed layer 22 and the plating film 23 now form a wiring together Material film 24. The electroplating is performed while a plating fluid 5 is maintained between a cap 41 having a recess on the side surface of the base member and the base member 1 丨. Under this structure, a sealing element (such as 〇-ring) 42 series Provided between the outer edge portion of the base member Π and the outer edge of the cap 41 to prevent the plating fluid 51 from leaking toward the rear surface of the base member Π, and to keep the cathode 31 away from the plating fluid 51. The The cathode 3 1 is in contact with the plating seed layer 22. Since the distance between the base member 11 and the feed plating fluid 51 is sealed by a cap 4 and a sealing member 42, it is retained in the base member 11 and the cap The electroplating mud 51 between 41 will not leak to the outside. Therefore, the film 23 of the electron microscope only grows in the area located inside the sealing element 42. Generally, copper sulfate-alkaline electroplating fluid can be used as the electroplating fluid. The conditions are a plating current of 2.83 angstroms, the growth rate of the crystals is 4 · 5 minutes per 1 micron film growth, and a fluid temperature of 18 ° C. Secondly, as shown in FIG. 1C, the thin wiring material 24 (refer to FIG. 1B) is subjected to electrolytic polishing, and an electrolytic polishing fluid 61 is provided at an interval between the base member 丨 丨 and the middle mask 43 to The wiring material film 24 is left in the wiring trench (not shown), thereby completing the trench wiring (not shown). The electrolytic polishing is performed under the condition that the electrolytic polishing fluid 61 is held between the cap 43 having a recess on the side surface of the base member 丨 and the base member 11. Under this structure, a sealing element (such as an O-ring) 44 is provided between the outer edge portion of the base member 11 and the outer edge of the cap 43 to prevent the electrolytic polishing fluid 6 from moving toward the base member. The surface leaks and keeps the cathode 32 away from the electrolytic polishing fluid 61. The cathode 3 2 system is in contact with the transition bond seed layer 22. Because it is located on the base 11 and feeds the electricity-9-This paper is suitable for size @ @ 家 标准 (CNS) A4 size (21GX 297 public director) --- 502333 A7 _ __B7__ V. Description of the invention (7) Solution polishing The interval of the fluid 61 is sealed with a cap 43 and a sealing element 44. Therefore, the electrolytic polishing fluid 61 retained between the base member 11 and the cap 43 does not leak outward. Therefore, only the wiring material film 24 in the area inside the sealing element 44 is polished (see Fig. 1B). The portion of the electroplated seed layer 22 (refer to FIG. 1C) located outside the sealing element 44 is left unpolished on the substrate, as shown in FIG. 1D. It is now known that the cap 43 and the sealing element 44 can be used for power plating users. The electrolytic polishing can generally use a phosphoric acid (specific gravity = 1.6) solution as a polishing fluid. The conditions are a current density of 5 to 20 A / dm2, and a polishing temperature of 15 to 25 ° C. In this kind of electrolytic polishing, when the wiring material film 24 located in this category is depleted, current starts to flow through the barrier layer 21 having a conductivity lower than that of the copper film, so the wiring material film 24 can maintain its conductivity higher than The edge portion allows the wiring material film 24 to be easily etched. Therefore, the wiring material film 24 located in this category can be removed almost completely and uniformly. Secondly, the plating seed layer 22 remaining on the outer edge portion of the base member 11 is removed by selectively supplying an etching fluid used for copper. The iron chloride etching solution can generally be used as an etching fluid for copper, which contains 340 to 380 g / l of gasified iron (for example, "ο g / l) and 5 to 60 ml of salt fe (in this case & gt (E.g., 30 ml). The temperature of the fluid can be $ 0 to 70 ° C. In this embodiment, a temperature of 50 ° c is used. A chlorinated steel solution can also be used, which can contain 50 to 200 G / l of gasified steel (in this case 100 g / l), 2 to 50 ml of hydrochloric acid (in this case 10 ml), and 5 to 70 g / l of potassium gaseous (in this case for example Buckle / liter). The temperature of the engraving fluid can be 20 to 70X :. In this embodiment, 5 (rc
A7A7
之溫度。 不可使用鹼虱蝕刻溶液作爲蝕刻溶液，其可含有川至2⑽ 升之氫氧化銨（此情況下例如⑽克/升），5q至Μ。克/升之 =化銨(此情況下例如80克/升)’ 5。至2〇。克/升之氯化銨(此 3況下例如12G克/升），5()至_克/升之錢氫铵（此情況下 例如120克/升）’及50至200克/升之硝酸銨（此情況下例如 120克/升）。㈣流體之溫度可爲2Q至赃。此實施例中， 採用50°c之溫度。 ' 亦可使用過氧化氫與氫氟酸之混合溶液。此實施例採用i 至3分鐘之蝕刻時間。 此種万法所得之結果，障壁層21係保留於基材"之範田壽 中，如圖1Ε所示。 其次，藉例如旋轉清潔使用㈣化氯水溶液移除在移除 佈線材料薄膜24之㈣曝露之障壁層21。使得該基件ih〇 圖IF所示般地曝露，得到溝槽式料，其中佈線溝槽充填 佈線材料薄膜24，唯未出示。 、由氮化鐫所製得之障壁層21的移除可採用過氧化氮水溶 液作爲淋洗流體，其條件設定於淋洗時間⑴分鐘，而淋 洗流體溫度爲1 5至4 0 °C。 第-種製造半導體裝置之方法具有選擇性地移除殘留於 該基件11之外緣部分上的佈線材料薄膜24之步驟，使得在 電解拋光之後，電鍍種晶層22始終不殘留於該基件u之表 面上，與使用於該電解拋光中之電極接觸的部分中，符合 期望地縮小該基件11的平面内高度差。此種在電解抛光之 -11 - G張尺度適财國目家標準(CNg) A4規格(21G x 297公董5——-- 後縮小平面内高度差的方 2 4之非c/ i、 種移除該佈線材料薄膜 取非必要邵分的方式可成 $ 存挺 比例。 、乂同半導體裝置之良率 其次，以下參照圖2A至的兑 奘冒> 士、+· α 以乃罘一種製造半導體 私置 < 万法的具體實例， 亨 面圖。 ϋ係馬出不程序步驟之部分剖 興第 美姑種方法的具體實例相同;也，雖未出示，但可於- 基材中氣造預定之裝置， 、 而&其上層形成中間層絕緣薄膜 奴^孩中間層絕緣薄膜中形成佈線溝槽。 其’入’如圖2 Α所示，血來昭岡〗Λ、 昨 、 ” > 知圖1Α所述之方法相同地，該 罘種Ρ早壁層21 —般包括—氮化㈣膜，藉如cvd方法形 成於該經處理基件11上。用以電鍍”助長得之電鍵種晶 層22係使用藉由物理氣相沉積（pVD)方法諸如錢生長之鋼 薄膜形成。 其次，如圖2B所示，與參照圖1B所述之方法相同地， 一般具有1.0微米厚度的銅薄膜藉電鍍沉積於該電鍍種晶 層22上，以形成完全充填前述佈線溝槽（未示）的電鍍層^ 。琢電鍍種晶層22及所電鍍之薄膜23現在一起構成該佈 線材料薄膜2 4。在該電鍍泥體5 1保持於在該基件1 1之側 面上具有凹陷之帽罩4 1與該基件1 1之間的情況下進行電 鍍。於此種結構下，密封元件（例如〇形環）4 2提供於該基 件1 1之外緣部分與該帽罩4 1之外緣之間，以避免該電鍍 >瓦體5 1向著該基件1 1之後表面戌漏，並保持陰極3 1遠離 該電鍍流體5 1。因爲位於該基件1 1上進料該電鍍流體5 i -12- 本紙張尺度適用中國國家標準(CNS) A4规格(210X 297公釐) A7 B7 五、發明説明（10 ) 〈間隔係由帽罩41及密封元件42所密封，故保留於該基 件1 1與咸巾目罩41之間的電鍍流體5 1不會向外洩漏。因此 ，所電鍍之薄膜23僅於位㈣密封元件42内側 生長。 其次，如圖2C所示，該電鍍種晶層22曝露於位在該基件 上之外緣部分中的部分（參照圖2B)係藉著選擇性地施加 ^法蝕刻該障壁層21的蝕刻流體而移除。市售蝕刻流體之Of temperature. An alkaline lice etching solution cannot be used as an etching solution, and it may contain 1 to 2 liters of ammonium hydroxide (in this case, for example, ⑽g / liter), 5q to M. G / L = ammonium (in this case 80 g / L, for example) '5. To 20%. G / L of ammonium chloride (in this case, 12G g / L), 5 () to _g / L of ammonium dihydrogen (in this case, 120 g / L) 'and 50 to 200 g / L Ammonium nitrate (for example 120 g / L in this case). The temperature of the tritium fluid can be from 2Q to arrogant. In this embodiment, a temperature of 50 ° C is used. 'You can also use a mixed solution of hydrogen peroxide and hydrofluoric acid. This embodiment uses an etching time of i to 3 minutes. As a result of this method, the barrier layer 21 is retained in Fan Tianshou of the base material, as shown in FIG. 1E. Next, the barrier layer 21 exposed in the removed wiring material film 24 is removed by, for example, spin cleaning using a halogenated chlorine aqueous solution. The base member ih0 was exposed as shown in FIG. IF to obtain a trench material, in which the wiring trench is filled with the wiring material film 24, but it is not shown. For the removal of the barrier layer 21 made of hafnium nitride, an aqueous solution of nitrogen peroxide can be used as the eluent fluid, and the conditions are set at a rinse time of ⑴ minutes, and the temperature of the eluent fluid is 15 to 40 ° C. The first method of manufacturing a semiconductor device has a step of selectively removing the wiring material film 24 remaining on the outer edge portion of the base member 11 so that after electrolytic polishing, the plating seed layer 22 does not remain on the base On the surface of the member u, in the portion in contact with the electrode used in the electrolytic polishing, the in-plane height difference of the base member 11 is desirably reduced. This type of electro-polishing -11-G scale is suitable for national standards (CNg) A4 specifications (21G x 297 public directors 5 --- after reducing the square height difference in the square 2 4 non-c / i, This method of removing the wiring material film and taking unnecessary points can be a ratio of $. It is the same as the yield of the semiconductor device. Second, refer to FIG. 2A to the following. A specific example of manufacturing semiconductor private < Wanfa, Hengmian diagram. The specific example of the method of the Dimeigu method is part of the program steps; also, although not shown, it can be used on-substrate China Gas made the intended device, and its upper layer forms an interlayer insulating film, and a wiring groove is formed in the interlayer insulating film. Its 'in' is shown in Figure 2 Α. ≫ Knowing that the method described in FIG. 1A is the same, the P early wall layer 21 generally includes a nitride film, which is formed on the treated substrate 11 by the cvd method. It is promoted by electroplating " The bond seed layer 22 is formed using a thin steel film grown by a physical vapor deposition (pVD) method such as money. Secondly, as shown in FIG. 2B, similar to the method described with reference to FIG. 1B, a copper thin film generally having a thickness of 1.0 micron is deposited on the plating seed layer 22 by electroplating to form a complete filling of the aforementioned wiring trenches (not shown) The electroplated layer ^. The electroplated seed layer 22 and the plated film 23 now together constitute the wiring material film 24. The electroplating mud 51 is held on the side of the base member 1 with a recessed cap Electroplating is performed between the cover 41 and the base member 11. In this structure, a sealing member (such as an O-ring) 4 2 is provided on the outer edge portion of the base member 1 1 and the cap 41. Between the outer edges to avoid the plating > tile body 51 from leaking towards the surface of the base member 1 1 and to keep the cathode 3 1 away from the plating fluid 51. Because it is located on the base member 1 1 the Electroplating fluid 5 i -12- This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297 mm) A7 B7 V. Description of the invention (10) <The space is sealed by the cap 41 and the sealing element 42, so it is retained The plating fluid 51 between the base member 11 and the salt towel mask 41 does not leak outward. Therefore, all The plated film 23 grows only inside the sealing element 42. Next, as shown in FIG. 2C, the portion of the plating seed layer 22 exposed on the outer edge portion of the substrate (see FIG. 2B) is borrowed. An etching fluid for selectively etching the barrier layer 21 is selectively applied and removed.
實例係包括氯化鐵蝕刻流體、氯化銅蝕刻流體、及鹼氨蝕 刻流體。 :'入，如圖2D所示，與圖1C所述之方法相同地，該佈線 材料薄膜24係進行電解拋光，以僅於佈線溝槽（未示）中保留 泫佈、’泉材料薄膜24，因而完成溝槽佈線（未示）。該電解拋光 係於該電解拋光流體6 1保留於在基件1 1之側面上具有凹陷 (巾目罩43與該基件丨丨之間的情況下進行。於此結構下，該 密封元件（例如〇形環）44係提供於該基件丨丨之外側邊緣部分 與帽罩43之外緣之間，以避免電解拋光流體61向著該基件 1 1之後表面洩漏，且保持陰極3 2遠離該電解拋光流體6 1。 々陰極3 2係接觸於該障壁層2 1。因爲位於該基件1 1上進料 該電解抛光流體6丨之間隔係由帽罩43及密封元件44所密封 ’故保留於該基件丨丨與該帽罩43之間的電解拋光流體61不 會向外洩漏。因此，拋光位於該密封元件44内側之佈線材 料薄膜24。 該電解拋光一般可採用磷酸（比重=丨·6)溶液作爲拋光 流體，其條件係電流密度5至20A/dm2，拋光溫度15至25 -13 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 502333 A7Examples include iron chloride etching fluid, copper chloride etching fluid, and alkali ammonia etching fluid. : 'In, as shown in FIG. 2D, the wiring material film 24 is electrolytically polished in the same manner as described in FIG. 1C, so that only the cloth and the spring material film 24 are retained in the wiring grooves (not shown). Thus, the trench wiring (not shown) is completed. The electrolytic polishing is performed when the electrolytic polishing fluid 61 is left with a depression (between the mask 43 and the base member 丨) on the side of the base member 1 1. Under this structure, the sealing element ( For example, O-ring) 44 is provided between the outer edge of the base member and the outer edge of the cap 43 to prevent the electrolytic polishing fluid 61 from leaking toward the surface of the base member 1 1 and to keep the cathode 3 2 away from The electrolytic polishing fluid 6 1. The cathode 3 2 is in contact with the barrier layer 21. The interval between feeding the electrolytic polishing fluid 6 on the base member 1 1 is sealed by the cap 43 and the sealing element 44 ′ Therefore, the electrolytic polishing fluid 61 retained between the base member 丨 and the cap 43 will not leak to the outside. Therefore, the wiring material film 24 located inside the sealing member 44 is polished. The electrolytic polishing can generally use phosphoric acid (specific gravity = 丨 · 6) The solution is used as a polishing fluid. The conditions are a current density of 5 to 20 A / dm2, and a polishing temperature of 15 to 25 -13.-This paper size applies to China National Standard (CNS) A4 (210X 297 mm) 502333 A7
、中，當位於該範疇中之佈線材料薄膜24 7 -時’電流開始流經電導係數低於銅薄膜之障壁層 故該佈線材料薄膜24可保持其電導係數高於邊二: 分，使得該佈線材料薄膜24可輕易地被蝕刻。因此，可 幾乎元全且均勻地移除位於該範疇中的佈線材料薄膜Μ 。現在應已發現該帽罩43及密封元件44可爲電鍍所使用 者0 歷經該程序之結果，障壁層21保留於該基件丨丨上的範疇 中，如圖2Ε所示。 其次，在移除該佈線材料薄膜24之後所曝露之障壁層η 係藉由例如旋轉清潔法使用過氧化氫水溶液移除。使得該 基件11如同圖2F所示般地曝露，並得到充填該佈線材料薄 膜的溝槽佈線。 由氮化鎢所製得之障壁層2 1之移除可採用過氧化氫水溶 液作馬淋洗流體，其條件係爲淋洗吟間丨至3分鐘，而淋洗 流體之溫度係爲1 5至40°C。 第二種製造半導體裝置之方法具有選擇性地蝕刻去除 該電鍍種晶層22曝露於基件丨丨之外緣部分中的部分之步 驟，故该電鍍種晶層2 2在電解拋光之後，始終不會殘留 於基件1 1之表面上，符合期望地縮小該基件丨丨之平面内 高度差。此種在電解拋光之後縮小平面内高度差的方式 及此種移除構成該佈線材料薄膜24之電鍍薄膜23及電鍍 種晶層22之非必要部分的方式可成功的提高半導體裝置 之良率比例。 -14 - 本紙張尺度適用中國國家標準(CNS) A4规格(210 X 297公|) 裝 訂When the wiring material film 24 7 in this category is located, the current starts to flow through the barrier layer with a conductivity lower than that of the copper film. Therefore, the wiring material film 24 can maintain its conductivity higher than that of the edge 2: points, making the The wiring material film 24 can be easily etched. Therefore, the wiring material film M located in this category can be removed almost completely and uniformly. It should now be found that the cap 43 and the sealing element 44 can be used by electroplating users. As a result of this procedure, the barrier layer 21 remains in the category on the base member, as shown in Fig. 2E. Next, the barrier layer η exposed after the wiring material film 24 is removed is removed by using a hydrogen peroxide solution, for example, by a spin cleaning method. The base member 11 is exposed as shown in Fig. 2F, and a trench wiring filled with the thin film of the wiring material is obtained. The removal of the barrier layer 21 made of tungsten nitride can use an aqueous hydrogen peroxide solution as the horse eluent fluid, the conditions of which are from the shower room to 3 minutes, and the temperature of the shower fluid is 1 5 To 40 ° C. The second method for manufacturing a semiconductor device has a step of selectively etching and removing a portion of the plating seed layer 22 exposed on the outer edge portion of the base member. Therefore, the electroplating seed layer 22 is always polished after electrolytic polishing. It will not remain on the surface of the base member 1 1, and it is desirable to reduce the height difference in the plane of the base member 丨 丨. This method of reducing the in-plane height difference after electrolytic polishing and this method of removing unnecessary portions of the plating film 23 and the plating seed layer 22 constituting the wiring material film 24 can successfully improve the yield ratio of the semiconductor device. . -14-This paper size applies to China National Standard (CNS) A4 (210 X 297 male |) Binding
線 502333 第090113973號專利申請案 中文說明書修正頁（91年6月） 五、發明説明（12 ) 雖已針對較佳型式於特定特異程度下描述本發明，但 其可顯然可有許多變化及改變。因此， 已知除所詳細描 述者之外，本發明可在不偏離其範圍及精神的情況下進 行。 圖式元件符號說明 11基件 51電鍍流體 21障壁層 61電解撾光流體 22電鍍種晶層 101晶圓 23電鍍層 102障壁層 24佈線材料薄膜 103電鍍種晶層 31陰極 104絕緣薄膜 32陰極 111電極 41帽罩 121電解据光流體 42密封元件 131帽罩 43帽罩 S 階梯度部分 44密封元件 -15- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)Line 502333 No. 090113973 Patent Application Chinese Specification Revised Page (June 91) V. Description of the Invention (12) Although the present invention has been described with a specific specific level for a better type, it can obviously have many changes and modifications. . Therefore, it is known that the present invention can be carried out without departing from its scope and spirit, except as described in detail. Symbol descriptions of figure elements 11 base 51 electroplating fluid 21 barrier layer 61 electrolysis fluid 22 electroplating seed layer 101 wafer 23 electroplating layer 102 barrier layer 24 wiring material film 103 electroplating seed layer 31 cathode 104 insulating film 32 cathode 111 Electrode 41 cap 121 electrolysis light fluid 42 sealing element 131 cap 43 cap S step portion 44 sealing element -15- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm)
Claims (1)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000176216A JP4055334B2 (en) | 2000-06-13 | 2000-06-13 | Manufacturing method of semiconductor device |
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| TW502333B true TW502333B (en) | 2002-09-11 |
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| TW090113973A TW502333B (en) | 2000-06-13 | 2001-06-08 | Method for fabricating semiconductor devices |
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| US (1) | US6602787B2 (en) |
| JP (1) | JP4055334B2 (en) |
| KR (1) | KR100815829B1 (en) |
| TW (1) | TW502333B (en) |
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| JP4644926B2 (en) * | 2000-10-13 | 2011-03-09 | ソニー株式会社 | Semiconductor manufacturing apparatus and semiconductor device manufacturing method |
| JP2003179242A (en) * | 2001-12-12 | 2003-06-27 | National Institute Of Advanced Industrial & Technology | Metal oxide semiconductor thin film and its manufacturing method |
| JP2003326419A (en) * | 2002-05-09 | 2003-11-18 | Sony Corp | Plating method, plating device, and polishing method, polishing device, and method for manufacturing semiconductor device |
| JP4086567B2 (en) * | 2002-07-10 | 2008-05-14 | Ｎｅｃエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| US7192886B2 (en) * | 2002-10-25 | 2007-03-20 | Intersurface Dynamics, Inc. | Method for using additives in the caustic etching of silicon for obtaining improved surface characteristics |
| US7735451B2 (en) * | 2002-11-15 | 2010-06-15 | Ebara Corporation | Substrate processing method and apparatus |
| US7528065B2 (en) * | 2006-01-17 | 2009-05-05 | International Business Machines Corporation | Structure and method for MOSFET gate electrode landing pad |
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| US6268289B1 (en) * | 1998-05-18 | 2001-07-31 | Motorola Inc. | Method for protecting the edge exclusion of a semiconductor wafer from copper plating through use of an edge exclusion masking layer |
| KR19990086371A (en) * | 1998-05-27 | 1999-12-15 | 윤종용 | Polishing process for manufacturing semiconductor device |
| JP2000064083A (en) * | 1998-08-24 | 2000-02-29 | Sony Corp | Electrolysis, electrolyte and production of semiconductor device |
| US6056864A (en) * | 1998-10-13 | 2000-05-02 | Advanced Micro Devices, Inc. | Electropolishing copper film to enhance CMP throughput |
| US6423636B1 (en) * | 1999-11-19 | 2002-07-23 | Applied Materials, Inc. | Process sequence for improved seed layer productivity and achieving 3mm edge exclusion for a copper metalization process on semiconductor wafer |
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| JP4055334B2 (en) | 2008-03-05 |
| JP2001358092A (en) | 2001-12-26 |
| US20020068438A1 (en) | 2002-06-06 |
| KR20010112653A (en) | 2001-12-20 |
| US6602787B2 (en) | 2003-08-05 |
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