KR20010004718A - Method of forming a metal wiring in a semiconductor device - Google Patents

Method of forming a metal wiring in a semiconductor device Download PDF

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Publication number
KR20010004718A
KR20010004718A KR1019990025432A KR19990025432A KR20010004718A KR 20010004718 A KR20010004718 A KR 20010004718A KR 1019990025432 A KR1019990025432 A KR 1019990025432A KR 19990025432 A KR19990025432 A KR 19990025432A KR 20010004718 A KR20010004718 A KR 20010004718A
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layer
copper
forming
trench
contact hole
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KR1019990025432A
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Korean (ko)
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KR100323875B1 (en
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이병주
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A metal line formation method in semiconductor devices is provided to be capable of obtaining a copper filling layer having a good filling characteristic and the surface planarizing and also reducing internal defects such as voids and key holes. CONSTITUTION: An interlayer insulating film(12) is first formed on a bottom layer(11). A portion of the interlayer insulating film is then etched to form a via contact hole(13) and a trench(14). After performing a cleaning process, a diffusion barrier layer(15) and a copper seed layer(16) are formed on the surface of the interlayer insulating film including the via contact hole and the trench. Next, a mask layer(100) to open the via contact hole and the trench is formed. A copper filling layer(17) is selectively formed in the via contact hole and the trench by copper electroplating process. After removing the mask layer, a polishing process is performed to form a copper metal line(167). Then, a capping layer(18) is deposited on the entire surface of the wafer.

Description

반도체 소자의 금속 배선 형성 방법 {Method of forming a metal wiring in a semiconductor device}Method of forming a metal wiring in a semiconductor device

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 구리 전해 도금법을 이용한 구리(Cu) 증착법으로 구리 금속 배선을 형성함에 있어, 비아 콘택홀 및 트렌치에만 구리를 선택적으로 매립하면서 구리 매립층의 평탄화를 증대시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices. In particular, in forming copper metal wirings by a copper (Cu) deposition method using copper electroplating, the copper buried layer is planarized while selectively filling copper only in via contact holes and trenches. It relates to a metal wiring forming method of a semiconductor device capable of increasing the.

반도체 산업이 초대규모 집적 회로(Ultra Large Scale Integration; ULSI)로 옮겨 가면서 소자의 지오메트리(geometry)가 서브-하프-마이크로(sub-half-micron) 영역으로 계속 줄어드는 반면, 성능 향상 및 신뢰도 측면에서 회로 밀도(circuit density)는 증가하고 있다. 이러한 요구에 부응하여, 반도체 소자의 금속 배선을 형성함에 있어서 구리 박막은 알루미늄에 비해 녹는점이 높아 전기이동도(electro-migration; EM)에 대한 저항이 커서 반도체 소자의 신뢰성을 향상시킬 수 있고, 비저항이 낮아 신호전달 속도를 증가시킬 수 있어, 집적 회로(integration circuit)에 유용한 상호연결 재료(interconnection material)로 사용되고 있다.As the semiconductor industry moves to Ultra Large Scale Integration (ULSI), the geometry of the device continues to shrink to the sub-half-micron region, while improving circuitry in terms of performance and reliability. Circuit density is increasing. In response to these demands, the copper thin film has a higher melting point than aluminum in forming metal wirings of the semiconductor device, and thus has high resistance to electro-migration (EM), thereby improving reliability of the semiconductor device and providing a specific resistance. This low rate can increase the signal transfer rate, making it a useful interconnect material for integration circuits.

현재, 사용이 가능한 구리 매립 방법으로는 물리기상증착(PVD)법/리플로우 (reflow), 화학기상증착법(CVD), 전해 도금(Electroplating)법, 무전해 도금(Electroless-plating)법 등이 있으며, 이 중에서 선호되는 방법은 구리 매립 특성이 비교적 양호한 전해 도금법과 화학기상증착법이다. 그러나, 반도체 소자의 고집적화에 따라 비아 콘택홀의 크기가 감소하고, 어스펙트 비가 증가하게 되었고, 이로 인해 점점 열악해지는 구리 매립 특성을 향상시키고자하는 방안이 연구 개발 중이다.Currently available copper embedding methods include physical vapor deposition (PVD) / reflow, chemical vapor deposition (CVD), electroplating, and electroless-plating. Among these, preferred methods are electroplating and chemical vapor deposition which have relatively good copper embedding properties. However, due to the high integration of semiconductor devices, the size of the via contact hole is reduced and the aspect ratio is increased. Accordingly, a method for improving copper embedding characteristics, which is worsened, is being researched and developed.

구리 매립 특성이 불량할 경우에는 비아 콘택홀의 저항이 높거나 구리 플러그가 단락(fail)되는 문제가 발생한다. 또한 반도체 소자의 속도가 느려지며(RC time delay 증가), 신뢰성이 열악해지고, 수율이 감소하는 문제점이 발생한다.If the copper buried property is poor, a high resistance of the via contact hole or a shortage of the copper plug may occur. In addition, there is a problem that the speed of the semiconductor device becomes slow (increased RC time delay), the reliability becomes poor, and the yield decreases.

따라서, 본 발명은 매립 특성이 양호한 구리 전해 도금법을 이용한 구리(Cu) 증착법으로 비아 콘택홀 및 트렌치에만 구리를 선택적으로 매립하면서 구리 매립층의 평탄화를 증대시켜, 금속 배선에 대한 신뢰성, 안정성, 성능 및 생산성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention provides a copper (Cu) deposition method using a copper electroplating method with good buried characteristics to increase the planarization of the copper buried layer while selectively filling copper only in via contact holes and trenches, thereby improving reliability, stability, performance and It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device capable of improving productivity.

이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 금속 배선 형성 방법은 하지층상에 층간 절연막을 형성한 후, 상기 층간 절연막의 일부분을 식각하여 비아 콘택홀 및 트렌치를 형성하는 단계; 클리닝 공정을 실시한 후, 상기 비아 콘택홀 및 트렌치를 포함한 상기 층간 절연막 표면에 확산 장벽층 및 구리 시드층을 형성하는 단계; 상기 비아 콘택홀 및 트렌치가 개방되는 마스크층을 형성하는 단계; 구리 전해 도금 공정으로 상기 비아 콘택홀 및 트렌치에만 구리 매립층(17)을 선택적으로 형성하는 단계; 및 상기 마스크층을 제거한 후, 연마 공정을 실시하여 구리 금속 배선을 형성하고, 웨이퍼의 표면에 캡핑층을 전면 증착하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, a method of forming a metal wiring of a semiconductor device according to an embodiment of the present invention may include forming a via contact hole and a trench by forming an interlayer insulating film on an underlayer and then etching a portion of the interlayer insulating film; After the cleaning process, forming a diffusion barrier layer and a copper seed layer on a surface of the interlayer insulating layer including the via contact hole and the trench; Forming a mask layer in which the via contact hole and the trench are opened; Selectively forming a copper buried layer (17) only in the via contact hole and the trench by a copper electroplating process; And removing the mask layer, performing a polishing process to form a copper metal wiring, and depositing a capping layer on the entire surface of the wafer.

도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

11: 하지층 12: 층간 절연막11: base layer 12: interlayer insulating film

13: 비아 콘택홀 14: 트렌치13: via contact hole 14: trench

15: 확산 장벽층 16: 구리 시드층15: diffusion barrier layer 16: copper seed layer

17: 구리 매립층 167: 구리 금속 배선17: copper buried layer 167: copper metal wiring

18: 캡핑층 100: 마스크층18: capping layer 100: mask layer

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for describing a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.

도 1a를 참조하면, 하지층(11)상에 층간 절연막(12)을 형성한 후, 층간 절연막(12)의 일부분을 식각하여 비아 콘택홀(13) 및 트렌치(14)를 형성한다. 클리닝(cleaning) 공정을 실시한 후, 비아 콘택홀(13) 및 트렌치(14)를 포함한 층간 절연막(12) 표면에 확산 장벽층(15)을 형성한다. 전해 도금 공정을 진행하기 위해 촉매 역할을 하는 구리 시드층(16)을 확산 장벽층(15) 상에 형성한다.Referring to FIG. 1A, after forming the interlayer insulating layer 12 on the base layer 11, a portion of the interlayer insulating layer 12 is etched to form the via contact hole 13 and the trench 14. After the cleaning process, the diffusion barrier layer 15 is formed on the surface of the interlayer insulating layer 12 including the via contact hole 13 and the trench 14. A copper seed layer 16 serving as a catalyst is formed on the diffusion barrier layer 15 to proceed the electroplating process.

상기에서, 하지층(11)은 반도체 기판, 폴리실리콘(poly-Si), 텅스텐(W), 알루미늄(Al), 구리(Cu) 등과 같은 전도성 물질로 형성된 층이거나, 절연 물질로 형성된 층이다. 층간 절연막(12)은 낮은 유전 상수(low k)를 갖는 절연 물질로 형성한다. 비아 콘택홀(13) 및 트렌치(14)는 듀얼 다마신(dual damascene) 방식으로 형성한다.In the above, the base layer 11 is a layer formed of a conductive material such as a semiconductor substrate, polysilicon (poly-Si), tungsten (W), aluminum (Al), copper (Cu), or the like, or a layer formed of an insulating material. The interlayer insulating film 12 is formed of an insulating material having a low dielectric constant (low k). The via contact hole 13 and the trench 14 are formed in a dual damascene method.

클리닝 공정은 하지층(11)이 텅스텐(W)이나 알루미늄(Al)과 같은 금속일 경우 고주파 플라즈마(RP plasma)를 이용하고, 하지층(11)이 구리(Cu)일 경우 리액티브 클리닝(reactive cleaning) 방식을 적용하며, 하지층(11)이 절연 물질일 경우 스퍼터링(sputtering) 방식을 적용하고, 이외에도 NF3클리닝, 습식(wet) 클리닝이 있다. 확산 장벽층(15)은 ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, CVD WN 중 적어도 어느 하나로 형성하며, 100 내지 700Å 두께의 접착층과 100 내지 1000Å 두께의 베리어 메탈층이 적층되어 있다.The cleaning process uses high frequency plasma (RP plasma) when the base layer 11 is a metal such as tungsten (W) or aluminum (Al), and reactive cleaning when the base layer 11 is copper (Cu). The cleaning method is applied, and if the base layer 11 is an insulating material, a sputtering method is applied. In addition, there are NF 3 cleaning and wet cleaning. The diffusion barrier layer 15 is formed of at least one of ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, and CVD WN, and has an adhesive layer having a thickness of 100 to 700 GPa and a thickness of 100 to 1000 GPa. The barrier metal layer of thickness is laminated | stacked.

구리 시드층(16)은 스퍼터링법, 화학기상증착법, 메탈 이온 플라즈마(Ionic Metal Plasma; IMP)-물리기상증착법 등으로 100 내지 1000Å의 두께로 증착한다. 구리 시드층(16)은 스텝 커버리지가 우수하여야 한다.The copper seed layer 16 is deposited to a thickness of 100 to 1000 mW by sputtering, chemical vapor deposition, Ionic Metal Plasma (IMP) -physical vapor deposition, or the like. The copper seed layer 16 should have good step coverage.

도 1b를 참조하면, 선택적 구리 증착을 위해 비아 콘택홀(13) 및 트렌치(14)가 개방되는 마스크층(100)을 형성한다. 구리 전해 도금법을 이용한 구리 증착법으로 비아 콘택홀(13) 및 트렌치(14)에만 구리 매립층(17)을 선택적으로 형성한다.Referring to FIG. 1B, a mask layer 100 is formed in which the via contact hole 13 and the trench 14 are opened for selective copper deposition. The copper buried layer 17 is selectively formed only in the via contact hole 13 and the trench 14 by a copper deposition method using a copper electroplating method.

상기에서, 마스크층(100)은 구리 전해 도금 공정시 구리가 도금되지 않도록 구리 도금 방지 역할을 하며, 포토레지스트(photoresist)와 같은 물질로 형성 가능하다. 구리 전해 도금법은 전해액 내에서 웨이퍼의 표면에 음극의 전해 포텐셜을 인가하면 전해액 내의 구리 이온이 환원되어 웨이퍼의 구리 시드층(16)에 도금되어 구리 매립층(17)이 형성된다. 이때, 양극으로는 구리 금속을 사용하며, 양극에서는 구리의 산화 반응이 일어난다. 구리 매립층(17)의 매립 특성 및 표면 평탄화를 증대시키기 위하여, 구리 전해 도금 공정시 웨이퍼의 전해 포텐셜을 음극-양극-음극 순으로 변화시키면서 전해 도금-전해 폴리싱-전해 도금 순으로 공정이 진행되도록 한다. 즉, 웨이퍼의 표면에 양극의 전해 포텐셜을 인가하면 표면으로부터 가장 높은 구리 도금층 부위가 먼저 전해 폴리싱되어 구리 매립층(17)의 표면 평탄화 효과가 증대되고, 웨이퍼의 표면에 음극의 전해 포텐셜을 인가하면 구리가 전해 도금된다.In the above, the mask layer 100 serves to prevent copper plating so that copper is not plated during the copper electrolytic plating process, and may be formed of a material such as a photoresist. In the copper electroplating method, when the cathode potential is applied to the surface of the wafer in the electrolyte solution, copper ions in the electrolyte are reduced to plate the copper seed layer 16 of the wafer to form a copper buried layer 17. At this time, a copper metal is used as an anode, and an oxidation reaction of copper occurs at the anode. In order to increase the embedding characteristics and the surface planarization of the copper buried layer 17, the process is performed in the order of electrolytic plating-electrolytic polishing-electrolytic plating while changing the electrolytic potential of the wafer in the order of cathode-anode-cathode in the copper electrolytic plating process. . In other words, when the electrolytic potential of the anode is applied to the surface of the wafer, the highest copper plating layer portion is first electropolished from the surface to increase the surface planarization effect of the copper buried layer 17, and when the electrolytic potential of the cathode is applied to the surface of the wafer, copper Is electroplated.

도 1c를 참조하면, 마스크층(100)을 제거한 후, 화학적 기계적 연마(CMP) 공정 및 포스트-클리닝(post-cleaning) 공정을 실시하여 비아 콘택홀(13) 및 트렌치(14) 내에 구리 금속 배선(167)을 형성한다. 이후, 웨이퍼의 표면에 캡핑층(18)을 전면 증착한다.Referring to FIG. 1C, after removing the mask layer 100, a chemical mechanical polishing (CMP) process and a post-cleaning process are performed to form copper metal wirings in the via contact holes 13 and the trenches 14. 167 is formed. Thereafter, the capping layer 18 is entirely deposited on the surface of the wafer.

상기에서, 캡핑층(18)은 구리 금속 배선(167)으로부터 구리 원자가 이후에 구리 금속 배선(167) 상부쪽에 형성될 층간 절연막으로 확산하는 것을 막는 역할을 하며, 주로 실리콘 나이트라이드(SiN)로 형성한다. 이로써, 듀얼 다마신 공정에 의한 최종적인 구리 금속 배선이 완성된다.In the above, the capping layer 18 serves to prevent diffusion of copper atoms from the copper metal wiring 167 to the interlayer insulating film to be formed later on the copper metal wiring 167, and is mainly formed of silicon nitride (SiN). do. This completes the final copper metal wiring by the dual damascene process.

상술한 바와 같이, 본 발명은 구리의 전해 도금법을 적용하면서 비아 콘택홀 및 트렌치 내에만 선택적으로 구리를 매립하되, 구리 전해 도금 공정시 웨이퍼의 전해 포텐셜을 음극-양극-음극 순으로 변화시키면서 전해 도금-전해 폴리싱-전해 도금 순으로 공정이 진행되도록 하여 구리 매립층의 매립 특성 및 표면 평탄화를 향상시키므로써, 구리 매립층의 보이드(void) 및 키홀(keyhole)과 같은 내부 결함을 줄일 수 있어 금속 배선에 대한 신뢰성, 안정성 및 성능을 향상시킬 수 있을 뿐만 아니라, 연마 공정의 진행시간과 슬러리(slurry) 등의 소모품의 사용량을 줄일 수 있어 원가 절감 및 생산성을 향상시킬 수 있다.As described above, in the present invention, copper is selectively embedded in the via contact hole and the trench while applying the electrolytic plating method of copper, while the electrolytic plating of the wafer is changed in the order of cathode-anode-cathode during the copper electroplating process. Electrolytic Polishing-Electrolytic plating allows the process to proceed to improve the embedding properties and surface planarity of the copper buried layer, thereby reducing internal defects such as voids and keyholes in the copper buried layer, thus reducing In addition to improving reliability, stability, and performance, it is possible to reduce the running time of the polishing process and the use of consumables such as slurry, thereby reducing costs and improving productivity.

Claims (9)

하지층상에 층간 절연막을 형성한 후, 상기 층간 절연막의 일부분을 식각하여 비아 콘택홀 및 트렌치를 형성하는 단계;Forming an interlayer insulating layer on the underlayer, and etching a portion of the interlayer insulating layer to form via contact holes and trenches; 클리닝 공정을 실시한 후, 상기 비아 콘택홀 및 트렌치를 포함한 상기 층간 절연막 표면에 확산 장벽층 및 구리 시드층을 형성하는 단계;After the cleaning process, forming a diffusion barrier layer and a copper seed layer on a surface of the interlayer insulating layer including the via contact hole and the trench; 상기 비아 콘택홀 및 트렌치가 개방되는 마스크층을 형성하는 단계;Forming a mask layer in which the via contact hole and the trench are opened; 구리 전해 도금 공정으로 상기 비아 콘택홀 및 트렌치에만 구리 매립층을 선택적으로 형성하는 단계; 및Selectively forming a copper buried layer only in the via contact hole and the trench by a copper electroplating process; And 상기 마스크층을 제거한 후, 연마 공정을 실시하여 구리 금속 배선을 형성하고, 웨이퍼의 표면에 캡핑층을 전면 증착하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.Removing the mask layer, performing a polishing process to form a copper metal wiring, and depositing a capping layer on the surface of the wafer. 제 1 항에 있어서,The method of claim 1, 상기 하지층은 반도체 기판이거나, 폴리실리콘(poly-Si), 텅스텐(W), 알루미늄(Al), 구리(Cu)와 같은 전도성 물질로 형성된 층이거나, 절연 물질로 형성된 층인 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The base layer may be a semiconductor substrate, a layer formed of a conductive material such as polysilicon (poly-Si), tungsten (W), aluminum (Al), copper (Cu), or a layer formed of an insulating material. Method of forming metal wiring. 제 1 항에 있어서,The method of claim 1, 상기 층간 절연막은 낮은 유전 상수를 갖는 절연 물질로 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법The interlayer insulating film is formed of an insulating material having a low dielectric constant, wherein the metal wiring forming method of a semiconductor device 제 1 항에 있어서,The method of claim 1, 상기 콘택홀 및 트렌치는 듀얼 다마신 방식으로 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And forming the contact hole and the trench in a dual damascene method. 제 1 항에 있어서,The method of claim 1, 상기 클리닝 공정은 상기 하지층이 텅스텐(W)이나 알루미늄(Al)과 같은 금속일 경우 고주파 플라즈마를 이용하고, 상기 하지층이 구리(Cu)일 경우 리액티브 클리닝 방식을 적용하며, 상기 하지층이 절연 물질일 경우 스퍼터링 방식을 적용하고, NF3클리닝 방식이나 습식(wet) 클리닝 방식을 적용하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The cleaning process uses a high frequency plasma when the base layer is a metal such as tungsten (W) or aluminum (Al), and applies a reactive cleaning method when the base layer is copper (Cu). In the case of an insulating material, a sputtering method is applied, and an NF 3 cleaning method or a wet cleaning method is applied. 제 1 항에 있어서,The method of claim 1, 상기 확산 장벽층은 ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, CVD WN 중 어느 적어도 어느 하나로 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The diffusion barrier layer is formed of at least any one of ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, CVD WN. 제 1 항에 있어서,The method of claim 1, 상기 구리 시드층은 스퍼터링법, 화학기상증착법, 메탈 이온 플라즈마-물리기상증착법중 어느 하나를 적용하여 100 내지 1000Å의 두께로 증착하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The copper seed layer is formed by depositing any one of the sputtering method, chemical vapor deposition method, metal ion plasma-physical vapor deposition method to a thickness of 100 ~ 1000Å, the metal wiring formation method of a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 마스크층은 포토레지스트로 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the mask layer is formed of a photoresist. 제 1 항에 있어서,The method of claim 1, 상기 구리 전해 도금 공정은 웨이퍼의 전해 포텐셜을 음극-양극-음극 순으로 변화시키면서 전해 도금-전해 폴리싱-전해 도금 순으로 공정이 진행되도록 하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The copper electroplating process is a metal wiring forming method of a semiconductor device, characterized in that the electroplating-electrolytic polishing-electrolytic plating in order to proceed the process while changing the electrolytic potential of the wafer in the order of cathode-anode-cathode.
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US9129897B2 (en) 2008-12-19 2015-09-08 Asm International N.V. Metal silicide, metal germanide, methods for making the same
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