JP3329696B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for embedding a plating metal into a recess provided on a semiconductor substrate.

[0002]

2. Description of the Related Art In a power semiconductor device, it is necessary to increase the cross-sectional area of a wiring so as to withstand use at a large current. Chemical Vapor
If an attempt is made to use the deposition method, the wiring material is expensive and the deposition takes a long time, which is problematic. In a device that usually requires heat resistance, it is desirable to use a wiring material having excellent heat resistance, for example, a combination of Cu, which is a high melting point material, and a barrier metal. Tosureba embedding further it takes a long time, a method of forming the wirings and the like due to a large plating deposition rate excellent because inclusive of embedding order to avoid these problems have been noted.

On the other hand, with the miniaturization of semiconductor devices, a plating metal embedded wiring in which a plating metal is buried in a wiring groove and the surface thereof is polished and flattened has been proposed as a method of forming fine wiring suitable for high density. . These plated metal embedded wirings have a wiring structure that is extremely useful as the wiring of the power semiconductor device.

The problem with embedding a metal material using the plating method is that under the condition that the fluidity of the plating solution is hindered inside deep grooves or holes and the diffusion of ions is performed only unevenly. It is difficult to grow a dense and high-purity metal material having excellent electric conductivity with high reproducibility.

With reference to FIG. 8, the problem of the conventional method of forming a buried plated metal wiring will be described more specifically. For example, after a first insulating layer 2 is formed as a base insulating film on a semiconductor substrate 1 made of silicon, and a thick second insulating layer 3 for forming a buried wiring is formed,
Using a resist pattern (not shown) and ordinary RIE (Reactive Ion Etching) method,
The wiring groove 5 is formed at a predetermined position as shown in FIG.

After removing the resist pattern (not shown) using a normal O ₂ plasma ashing method,
The inside of the wiring groove 5 and the upper surface of the second insulating film are covered with a metal electrode film 6a using a sputtering method or the like, and then a metal such as Cu is formed on the metal electrode film 6a by an electroplating method. The film 7 is formed as a wiring material. However, when the metal film 7 is formed inside the wiring groove 5 in this manner, anions, chelates and the like are taken into the metal film 7 as impurities.

FIG. 8A shows a situation in which an anion 9 in a plating solution is incorporated as an impurity in a plating layer made of Cu atoms 7a. In general, if an impurity such as an anion terminates the adsorption site on the surface regardless of the size, and if the epitaxial growth of Cu or the like is hindered, a lattice defect occurs in the metal wiring material and the crystal becomes smaller. Further, impurities and the like are easily accumulated at the grain boundaries, and as a result, the quality of the film is deteriorated and the wiring resistance is increased.

[0008] The growth rate of the wiring material in the plating solution largely depends on the ion concentration in the solution. In a fine hole or groove, the supply of ions from the plating solution due to flow or diffusion becomes insufficient, and a local change occurs in the ion concentration of the plating solution. When the metal film 7 having a defect inside the wiring groove 5 is grown from the plating solution having the non-uniform ion concentration, the inner surface thereof becomes the second insulating layer 3 as shown in FIG. Is a growth surface with more irregularities than the surface deposited on the upper surface.

In such a situation, if the thickness of the plating metal film 7 is increased and the wiring groove 5 is buried as shown in FIG. 8B, especially at the center of the wiring groove 5 where the uneven surface meets, A number of cavities 14 are created.

In the conventional buried wiring using plated metal, the metal film 7 is buried in the wiring groove in such an imperfect state, and thereafter, as shown by the broken line and the arrow in FIG.
CMP (Chemical Mechanical Polishing)
Using a method h), the metal film 7 formed outside the wiring groove 5 and the metal electrode film 6a deposited on the upper surface of the second insulating film 3 are removed to form a plated metal embedded wiring. I was

As described above, the metal film 7 including a large number of cavities 14 at the center of the wiring groove increases the wiring resistance and takes in a plating solution or the like into the cavities 14 to cause a corrosion reaction to cause disconnection failure. Was causing it.

In order to improve the unevenness of the metal film grown by the plating method, a method of adding a special agent called a brightener to a plating solution has been known. This method is considered to use the action of adsorbing the brightener to the apex of the metal crystal growing in the direction perpendicular to the plating surface to suppress the growth and promote the growth of the metal film in the in-plane direction. ing. However, according to this method, the brightener or a decomposition product thereof is taken into the metal film as an impurity, and the resistance of the metal wiring is greatly increased.

As described above, the conventional plated metal buried wiring has attracted attention as a wiring process which has a high deposition rate and can be applied to fine wiring, and has low wiring reliability and a low resistance value as designed. There was no problem.

[0014]

As described above, the method of embedding a metal film in a recess formed on a semiconductor substrate by a plating method, including the conventional plating metal-embedded wiring, includes a high-purity and cavity. There is a problem that a metal material having excellent electrical conductivity cannot be buried in the recess with high yield and reproducibility.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a metal wiring having a large cross-sectional area capable of withstanding a large current and a metal wiring having excellent heat resistance as compared with the related art can be formed on a semiconductor substrate in a short time. To provide a high-yield and high-reliability plating method capable of forming fine wirings, fine electrodes of active elements, plugs for burying contact holes for interconnecting them, and the like by using these techniques. With the goal.

[0016]

[0017]

[0018]

In the pretreatment for coating with iodine, the surface oxide generated on the surface of the conductive material by opening to the atmosphere is immersed and removed in an etching solution, and then the surface oxide is removed. The etching liquid is replaced with a chemical containing iodine without exposing the surface of the conductive material to the atmosphere again. It chemical preferably containing the iodine is either molarity of KI solution and HI solution of 1μM to 1M, the plating solution used in the electroplating are either CuSO ₄ solution and AgClO ₄ solution It is characterized by.

By performing a pretreatment of coating the surface of the conductive material with iodine in advance, the growth surface of the metal film to be grown thereon is flattened, and the high-purity recesses formed in the semiconductor substrate are formed on the semiconductor substrate. In addition, a dense metal film can be embedded.

According to the method of manufacturing a semiconductor device of the present invention, an insulating film is formed on a semiconductor substrate, and a groove is formed in the insulating film.
After covering the inner surface of the groove and the upper surface of the insulating film with a barrier metal, further covering the surface of the barrier metal with a seed metal, and coating the surface of the seed metal with iodine, the seed metal is used as a cathode. A metal film is formed by laminating the seed metal on the seed metal to fill the groove by electroplating, and the barrier metal, the seed metal, and the metal film deposited outside the groove are removed.

In this manner, a metal wiring embedded in an insulating film formed on a semiconductor substrate can be formed. Here, the seed metal is a growth nucleus for the growth of the metal film during electroplating, and the seed metal of the same material as the metal film is thinly deposited on the barrier metal in advance, so that the plating of the metal film can be performed well. It can be carried out. The barrier metal prevents interdiffusion of the metal film and improves heat resistance.

According to the method of manufacturing a semiconductor device of the present invention, a barrier metal is formed on a semiconductor substrate via an insulating film, the surface of the barrier metal is further covered with a seed metal, and a resist film is formed on the surface of the seed metal. Then, a groove-shaped opening reaching the seed metal is formed in the resist film, and the surface of the seed metal is exposed at the bottom of the opening. After pretreatment of covering at least the surface of the seed metal with iodine, the seed metal is electroplated as a cathode to form a metal film that is stacked on the seed metal exposed on the bottom surface of the opening to fill the opening. The method is characterized in that the seed metal and the metal film deposited outside the opening are removed, and the resist film and the barrier metal remaining under the resist film are further removed. At this time, the iodine coating does not particularly affect the surface of the resist film or the side surface of the opening.

In this manner, a metal wiring or a low-resistance gate electrode of, for example, a MOS transistor can be formed on the insulating film formed on the semiconductor substrate. Further, the barrier metal may be formed directly on the semiconductor substrate. In this manner, the first-layer fine wiring and the like directly formed on the gate electrode of the MESFET, the emitter and the base electrode of the bipolar transistor, and the semi-insulating compound semiconductor substrate can be formed.

According to the method of manufacturing a semiconductor device of the present invention, a first metal film is patterned on a semiconductor substrate via a first insulating film, and the first metal film is patterned on the semiconductor substrate on which the first metal film is patterned. Forming a second insulating film, forming a contact hole penetrating through the second insulating film and reaching the first metal film, and covering the inside of the contact hole and an upper surface of the second insulating film with a barrier metal. Then, the surface of the barrier metal is further coated with a seed metal, and after the pretreatment of coating the surface of the seed metal with iodine, the seed metal is electroplated as a cathode, thereby laminating the seed metal to form a contact hole. Forming a second metal film to be buried, removing the barrier metal, the seed metal, and the second metal film deposited outside the groove, and exposing the second metal film on the contact hole; The third metal film, characterized in that the pattern formed.

In this manner, the metal plug can be embedded in the contact hole connecting between the multilayer wirings formed on the semiconductor substrate via the insulating film. At this time, if the first metal film is directly patterned on the semiconductor substrate, it is possible to form a metal plug of a contact hole connecting between the electrode of the element formed on the semiconductor substrate and the multilayer wiring.

Preferably, the seed metal and the metal film are
Any of Cu, Ag, Pd, and Al, and the barrier metal is W, WSiN, WN, TiN, TiW, Z
r, ZrN, Ta, or TaN.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings. With reference to FIG. 1, a method for forming a buried plated metal wiring according to the first embodiment of the present invention will be described.

For example, on a semiconductor substrate 1 made of silicon, a SiO
₂ film 2 is formed, and a 1 μm thick plasma SiO ₂ film 3 to be used for the buried wiring is formed by the plasma CVD method. A resist film 4 is formed on the plasma SiO ₂ film 3, and a predetermined pattern is opened in a region where a buried wiring is to be formed by using ordinary photolithography. Subsequently, using the wiring pattern formed on the resist film 4 as a mask, as shown in FIG. 1A, a wiring groove 5 having a depth of 0.8 μm which determines the shape of the buried wiring by a normal RIE method.
Was formed.

RIE is performed by O ₂ plasma ashing.
After removing the resist film 4 used as a mask of
A barrier metal 6 made of a W film having a thickness of 0.1 μm was formed on the entire surface of the plasma SiO ₂ film including the inside of the wiring groove 5 by using a sputtering method. Further, before performing Cu plating, a thin film of Cu having a thickness of about several tens nm is formed as a seed metal (not shown) serving as a nucleus of plating growth by using a vapor deposition method, a sputtering method, or a CVD method. Deposited on top.

Further, as a pre-treatment for Cu plating, an iodine deposition layer was formed on the seed metal by using the following first and second methods. The first method is that, after depositing a thin film of Cu serving as the seed metal, the deposition, sputtering, or CVD chamber used for the deposition is continuously evacuated to a thickness of several atomic layers on the seed metal. This is to deposit iodine.

The second method is to use C as the seed metal.
After depositing a thin film of u, the semiconductor substrate 1 is opened to the atmosphere, and the surface oxide layer of the seed metal generated by the reaction with the atmosphere is immersed in an etching solution containing 1% HF solution or dilute sulfuric acid for about 30 seconds. Remove. Subsequently, the etching solution is replaced with a KI solution or a HI solution having a molar concentration of 1 mM so that the surface of the seed metal from which the surface oxide layer has been removed by the etching does not come into contact with the air, and the thickness of the seed metal is reduced to a surface. A few atomic layers of an iodine deposition layer are formed. Here, the range of the molar concentration that can be pretreated with the KI solution and the HI solution is 1 μM to 1M.

After the seed metal is coated with the iodine deposition using the above first and second methods, the iodine deposition layer forms a hydrophobic field and acts as a passivation film.
Even if the semiconductor substrate that has undergone the above steps is opened to the atmosphere, there is no adverse effect on the subsequent plating step.

Next, using a plating solution containing, for example, 5 mM CuSO ₄ and containing no iodine and ordinary plating conditions, as shown in FIG. The film 7 was formed as a wiring material.

Next, as shown in FIG. 1C, the metal film 7 made of Cu other than the wiring groove 5 was removed by a CMP method to form a metal buried wiring having a predetermined pattern. In the first embodiment, the plasma Si O ₂ film, sputtered W as a wiring metal material as the base insulating film
A Cu film formed by a plating method on a barrier metal made of a film was used, and a vapor deposition method or a method of dipping in a chemical solution containing iodine was used to form an iodine-applied layer.

Here, in the structure shown in the first embodiment, the barrier metal made of the sputtering W is plasma Si.
It plays a role in enhancing the adhesion to the O ₂ film 3. It is not impossible to perform Cu plating directly using this as an electrode. However, as described above, furthermore, as a nucleus of plating growth, C having excellent adhesion by sputtering or the like is used in advance.
If a seed metal made of u is formed, the quality of the metal film 7 grown by plating can be improved, and the adhesion between the plasma SiO ₂ film 3 and the metal film 7 can be further increased.

Also, a CuSO ₄ solution was used as a Cu plating solution, and a CMP method was used as a method of removing unnecessary wiring material. For example, instead of the CuSO ₄ solution, 5 mM Ag was used.
Other materials and methods can be used for the insulating film, the wiring material, the chemical solution, the pretreatment method, the unnecessary wiring material removing method, and the like, such as forming an Ag plating wiring using a ClO ₄ solution. Further, the depth of the wiring groove formed in the base insulating film, the thickness of the wiring metal material deposited, the concentration of the chemical solution, and the like do not necessarily have to be the values shown in the first embodiment.

Here, referring to FIG. 2, the chemical basis of the effect of performing the pretreatment with the iodine-containing chemical solution before performing the Cu plating will be clarified. In FIG. 2A, reference numeral 6 denotes a barrier metal coated with a Cu seed metal serving as a negative electrode for depositing a plating metal, and reference numeral 8 denotes a barrier metal which is immersed in an iodine-containing chemical solution (KI or HI solution) for a short time. And a thickness of 1 applied to the surface of the negative electrode without any gap.
It is an elementally deposited layer such as an atomic layer to several atomic layers. 7a is Cu ion in the plating solution, 9 is the Cu ion (cation)
An anion consisting of a sulfate group ionically bonded to a chelating agent or a coordinated bond.

As shown in FIG. 2 (a), the volume as referred on the negative side electrode deposited an atom layer, the so atom is oxidized (IO ₃ ^- eluting changes in the plating solution) in Sarezu By applying a potential of a specific region that maintains the adsorption state to the electrode and performing electric field deposition (electroplating) of Cu ions contained in the plating solution, element atoms 8 and Cu ions 7a are formed so as to cover the electrode surface. And Cu ions 7a are separated from the anion 9 by 1 to
BR> passes through the elementally deposited layer 8 as a few atomic layers.

A more specific description is as follows. When the pH of the plating solution is 0, the potential of the electrode is +1.
When the voltage is 195 V or higher, the following reaction occurs, and the iodine atoms are oxidized to IO ₃ ^- and eluted into the plating solution.

[0040]

(Equation 1)

However, since the above reaction does not occur below this potential, in order to carry out the electrolytic deposition of Cu ions while maintaining the iodine-coated layer as described above, the pH of the plating solution must be zero. In this case, the potential of the plating electrode must be 1.195 V or less.

At this time, as shown in FIG. 2B, the anion 9 composed of a sulfate group or a chelating agent, which has a smaller interaction with iodine than the Cu ion 7a,
Cannot be passed through the plating solution, as shown by the arrow, Cu is left in the plating solution and passed through the iodine-deposited layer 8.
Only the ions 7a are deposited between the Cu seed metal covering the barrier metal 6 serving as the negative electrode and the iodine deposition layer 8, and the deposition reaction of the metal film 7 made of Cu proceeds.

As described above, the high-purity Cu is deposited on the Cu seed metal covering the barrier metal 6 composed of the W film.
Is deposited without generating defects, and the iodine-coated layer 8 always exists on the surface of the metal film 7 made of Cu on the seed metal.

As described above, the action of the conventional brightener is described above. The iodine-adhering layer 8 adsorbed on the surface of the Cu plating surface suppresses the growth in the direction perpendicular to the plating surface, and the Cu coating along the plating surface is suppressed. Promotes the growth of the metal film 7 made of. Therefore, the smoothness of the plated surface is remarkably improved by the presence of the iodine coating layer 8. In addition, since the iodine deposition layer 8 is always on the surface of the metal film 7, iodine is not taken into the metal film 7 as an impurity.

The function of the iodine-deposited layer is summarized as follows. For an impurity such as an anion in a plating solution having a smaller interaction with Cu than iodine, the element-adhered layer acts as a barrier so as to be present at the uppermost layer, the anion and the like are eliminated, and Cu after plating is removed. Purity is improved. In addition, the addition of the above-described action alleviates the dependency of the Cu deposition rate on the ion concentration based on the non-uniformity of ion diffusion in the plating solution, and suppresses the generation of cavities in Cu.

In addition, when anodic dissolution is performed after plating or during plating, the coverage of iodine after plating (the number of iodine atoms adsorbed on the surface / the number of surface atoms of the wiring material) is constant. If the value is greater than or equal to the value, a hydrophobic field is formed by iodine, and the formation of the hydrophobic field prevents entry of hydroxide ions into the surface of the metal film. For this reason, the oxidation reaction on the surface of the deposited Cu metal film is suppressed, and only the dissolution reaction can be selectively performed, and the protrusions on the surface of the plated metal Cu are dissolved to reduce the surface step. it can.

Here, the anodic dissolving means that the polarity of the voltage applied to the electrode used for plating is inverted, so that Cu is deposited on the cathode (in the present embodiment, the seed metal covering the barrier metal) by plating. This is an operation of eluting the metal film again into the plating solution. For example, the coordination number of the plating metal atoms is small at the convex portion of the deposition surface, so that the selective dissolution proceeds, and the flatness of the metal film surface is improved. Can be.

In addition, the formation of the hydrophobic field by iodine has the effect of suppressing the oxidation of the seed metal when exposed to the atmosphere before plating and the corrosion reaction of the plated metal when left in the atmosphere after plating.

[0049] Note was mentioned above, the effect of pretreatment intoxicated immersed briefly plating electrode-containing chemical, not only Cu plating using CuSO ₄ solution, substantially also Ag plating using the AgClO ₄ solution It has been confirmed that this also occurs. In addition, good results are obtained for Pd and Al which can be plated.

Next, a second embodiment of the present invention will be described with reference to FIG. On a semiconductor substrate 1 made of, for example, silicon, an SiO ₂ film 2 serving as a base of an embedded wiring is formed by using a CVD method. A contact pad made of Cu for forming a first-layer metal wiring made of Cu using a normal vapor deposition method or a sputtering method and a photolithography method, and connecting the first-layer wiring and an upper-layer wiring at predetermined positions. Form 10.

Next, a 1 μm thick plasma SiO ₂ film 3 is formed on the first layer wiring including the contact pad 10 as an interlayer insulating film of the first layer wiring and the second layer wiring. At this time, the unevenness generated on the surface of the plasma SiO ₂ film 3 by the first layer wiring is flattened by using a normal CMP method or an etch back method.

A resist film (not shown) is formed on the plasma SiO ₂ film 3, and a contact hole pattern is opened at a predetermined position on the contact pad 10 by using ordinary photolithography. Subsequently, using the contact hole pattern formed in the resist film as a mask, the contact pad 10 penetrates through the plasma SiO ₂ film 3 planarized by a normal RIE method.
Was formed.

RIE is performed by O ₂ plasma ashing.
After removing the resist film used as the mask of FIG. 2, as shown in FIG. 3, a barrier metal 6 made of a 0.1 μm thick W film is sputtered on the entire surface of the plasma SiO ₂ film including the inside of the contact hole. It was formed using a method, and further covered with a seed metal (not shown) of Cu having a thickness of several tens nm.

After forming an iodine deposition layer on the entire surface of the seed metal by using the first and second methods described in the first embodiment, the seed metal is made of, for example, CuSO _{4 having a} molar concentration of 5 mM. Using a plating solution containing no element, a 1.0 μm thick Cu
Was formed.

Next, the barrier metal 6 composed of W and the seed metal composed of Cu and the metal film 7 existing outside the contact hole are removed again by the CMP method, and the plasma Si is removed.
On the plug made of the metal film 7 exposed on the surface of the O ₂ film,
A contact pad 11 for a second layer wiring made of Cu is formed by using a normal evaporation method or a sputtering method and a photolithography method, and a contact for connecting the first layer wiring and the second layer wiring on the insulating film 2 is formed. Completed the plug for

In the second embodiment, the barrier metal 6 made of W has an effect of improving the adhesion to the plasma SiO ₂ film as in the case of the first embodiment. It serves to prevent mutual diffusion of the metal material between the pad 10 and the contact plug 7 and to improve the heat resistance and reliability of the wiring. The barrier metal 6 made of W can be used as it is as a plating electrode. However, by further coating the seed metal, the quality of the metal film 7 grown by plating is improved, and the adhesion is further improved.

In the second embodiment, the first and second layer wirings and their contact pads 10 and 11 are
Although the case of forming with u has been described, other metals such as Al can be used, for example. It is apparent from the first embodiment that the first and second layer wirings and their contact pads 10 and 11 can be formed by plating.

Further, as a modified example of the second embodiment,
When forming the wiring groove of the upper plating wiring on the lower contact pad, a contact hole for connecting to the lower contact pad is opened in advance at the bottom of the upper wiring groove, and the wiring groove including the contact hole is formed. Can be covered with a barrier metal and a seed metal, and an upper wiring and a contact plug for connecting the upper wiring and the lower wiring can be formed by a single plating process by a plating method. It is extremely difficult and difficult to bury a metal in a concave portion on a semiconductor substrate having such a complicated three-dimensional structure by other methods.

In the second embodiment, the contact pad 10 is formed on the insulating film 2. However, as shown in FIG. 4, the contact pad 10 is used to connect an element formed on the semiconductor substrate 1 to a wiring. Base diffusion layer 1 as an ohmic electrode of
It can also be formed directly on a. At this time, between the base diffusion layer 1a and the contact pad 10, in order to prevent mutual diffusion with the semiconductor substrate 1, TiSi, TiSi
A barrier metal such as N or TiN is interposed.

Next, a method for forming a metal wiring according to a third embodiment of the present invention will be described with reference to FIGS. Figure 5 (a), the insulating film 2 is formed consisting of the plasma SiO ₂ on a semiconductor substrate 1 made of silicon, a thickness of 0.1μm by using a conventional sputtering on the insulating film 2 A barrier metal 6 made of W and a seed metal (not shown) made of Ag are formed, and a thickness of 0.8 is formed on the surface.
After coating the resist film 12 of μm, a wiring groove 13 penetrating the resist film 12 and reaching the seed metal 6 was formed by using ordinary photolithography.

After forming an iodine deposition layer (not shown) on at least the surface of the Ag seed metal by using the first and second methods described in the first embodiment, for example, the molar concentration is reduced. Using a plating solution that does not contain iodine, such as a 5 mM AgClO ₄ solution, and using the barrier metal 6 as a cathode, by a normal plating method, as shown in FIG. Was formed.

Next, as shown in FIG. 5C, the metal film 7 formed outside the wiring groove 13 is removed by a normal polishing method, and the resist film 12 is removed by a normal RIE method. Further, by removing the barrier metal 6 made of W and the seed metal using the ion milling method, a metal wiring made of Ag can be formed on the semiconductor substrate 1 via the insulating film 2 as shown in FIG. Was.

In the third embodiment, the metal film 7
7 is formed on the insulating film 2. As shown in FIG. 7, a fine wiring or a fine electrode composed of the barrier metal 6 and the seed metal and the metal film 7 is formed directly on the semiconductor substrate 1. You can also.

The structure composed of plated metal wiring shown in FIG. 6 is used not only as a first layer wiring formed on a semiconductor substrate via an insulating film but also as a silicon MOSFE.
It can be used as a gate electrode of a MISFET formed on a T or compound semiconductor substrate. At this time, if the sectional shape of the gate electrode having a gate height larger than the gate length is formed by plating, the gate resistance can be greatly reduced, and a high-performance device can be obtained.

The plated metal wiring directly formed on the semiconductor substrate as shown in FIG. 7 is used not only as an insulating substrate such as sapphire, but also as a first layer wiring on a compound semiconductor substrate such as semi-insulating GaAs. , Low resistance MESFE
It can be used as a T gate electrode or as an emitter or base electrode of a low-resistance bipolar transistor.

In the third embodiment, the barrier metal is useful for improving the adhesion when the metal film of the plated wiring is formed on the insulating film, and when the metal film is formed directly on the semiconductor substrate, the semiconductor and the metal are used. Helps prevent interdiffusion with the film. When the gate electrode of the MESFET is used, a good Schottky barrier can be formed between the gate electrode and the channel layer on the semiconductor substrate.

In the third embodiment, as a wiring metal material, a seed metal on a sputtered W film and Ag as a metal film for plated wiring, and as a chemical for forming an iodine deposition layer by the second method. KI, A
Although a normal polishing method was used to remove the unnecessary wiring material from gClO ₄ , other wiring materials, chemicals, pretreatment methods, and unnecessary wiring material removing methods can be used. Also, the thickness of the resist film, the thickness of the deposited metal film, the concentration of the chemical solution, and the like do not necessarily have to be the values shown in the third embodiment.

The present invention is not limited to the above embodiment. In the first to third embodiments, as a material for plating or a seed metal, the main component is Cu,
Metals made of Ag, Pd, and Al can be used.
In addition, WSi is used as a barrier metal material in addition to W.
N, WN, TiN, TiW, Zr, ZrN, Ta, Ta
N can be used. In addition, various modifications can be made without departing from the spirit of the present invention.

[0069]

As described above, by using the method of embedding a metal film in a recess formed on a semiconductor substrate by plating, wiring of a power semiconductor device having a large sectional area and excellent heat resistance, or a semiconductor device By forming an iodine-adhering layer on the surface of the cathode before forming the fine wirings, fine electrodes, etc., the purity and the density of the metal embedded in the concave portions can be remarkably improved. Further, by using this method, the problem of forming a cavity in the metal embedded in the concave portion is completely avoided.

After the plating with the elemental coating layer as described above, or by performing anode dissolution as a treatment during the plating, the projections on the surface of the plated metal are selectively eluted.
Variations in surface steps are suppressed. If the coverage of iodine after plating is equal to or more than a certain amount, a hydrophobic field is formed, and a corrosion reaction due to standing in the air is suppressed. As described above, by providing the iodine-adhering layer on the surface of the seed metal serving as the cathode in advance, wiring and electrodes of the semiconductor device can be formed by the plating metal embedding method with high yield and high reliability.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a buried metal wiring according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing the operation of the iodine-coated film according to the present invention.

FIG. 3 is a process cross-sectional view of a buried metal wiring according to a second embodiment of the present invention.

FIG. 4 is a process cross-sectional view of a modified example of the embedded metal wiring according to the second embodiment of the present invention.

FIG. 5 is a process sectional view of a metal wiring according to a third embodiment of the present invention.

FIG. 6 is a sectional view of a metal wiring according to a third embodiment of the present invention.

FIG. 7 is a sectional view of a modified example of the metal wiring according to the third embodiment of the present invention.

FIG. 8 is a process sectional view showing a problem of the conventional embedded metal wiring.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 1a ... Diffusion layer 2, 3 ... Insulating film 4, 12 ... Resist film 5, 13 ... Wiring groove 6 ... Barrier metal 6a ... Metal electrode film 7 ... Metal film 8 ... Iodine coating layer 9 ... Anion 10 First layer contact pad 11 Second layer contact pad 14 Cavity in buried metal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/288 C25D 5/34 C25D 7/12 H01L 21/3205

Claims (7)

(57) [Claims] An insulating film is formed on a semiconductor substrate, a groove is formed in the insulating film, an inner surface of the groove and an upper surface of the insulating film are covered with a barrier metal, and a surface of the barrier metal is seed metal. After pretreatment of coating the surface of the seed metal with iodine, electroplating is performed using the seed metal as a cathode to form a metal film that is stacked on the seed metal and fills a groove. A method of manufacturing a semiconductor device, comprising removing a barrier metal, a seed metal, and a metal film deposited outside a groove. 2. A barrier metal is formed on a semiconductor substrate via an insulating film, a surface of the barrier metal is covered with a seed metal, a resist film is formed on a surface of the barrier metal, and a resist film is formed on the resist film. After forming a groove-shaped opening to reach and expose the surface of the seed metal to the bottom surface of the opening and coating at least the surface of the seed metal with iodine, electroplating is performed using the seed metal as a cathode. Forming a metal film that fills the opening by laminating on the seed metal exposed on the bottom surface of the opening; removing the metal film deposited outside the opening; A method of manufacturing a semiconductor device, further comprising removing the barrier metal and the seed metal remaining under the resist film. 3. The method according to claim 2 , wherein the barrier metal is formed directly on the semiconductor substrate. 4. A first metal film is patterned on a semiconductor substrate via a first insulating film, and a second insulating film is formed on the semiconductor substrate on which the first metal film is patterned. Forming a contact hole penetrating through the second insulating film and reaching the first metal film; covering the inside of the contact hole and an upper surface of the second insulating film with a barrier metal; Is further coated with a seed metal, and after a pretreatment of coating the surface of the seed metal with iodine, the seed metal is electroplated as a cathode to be laminated on the seed metal and fill the contact holes. Forming a second metal film, removing the barrier metal, the seed metal, and the second metal film deposited outside the trench, and exposing the upper portion of the contact hole; The method of manufacturing a semiconductor device, characterized in that the third metal film pattern formed on the second metal film. 5. The method according to claim 4, wherein the first metal film is formed by patterning directly on the semiconductor substrate. 6. The seed metal and the metal film according to any one of claims 1 , 2 and 3 , and the seed metal and the second metal film according to claim 4 and 5 , wherein the main components are Cu, respectively. ,
A method for manufacturing a semiconductor device, comprising: any one of Ag, Pd, and Al. 7. The barrier metal according to any one of claims 1 to 5 W, WSiN, WN, TiN, TiW,
A method of manufacturing a semiconductor device, wherein the method is any one of Zr, ZrN, Ta, and TaN.