498517 A7 B7 五、發明説明（1 【發明領域】： 本發明有關於一種半導體封裝件，尤指一種在導線 架上覆晶接置半導體晶片之導腳連接型半導體封裝件。 【發明背景】： 為因應電子產品輕薄短小的開發趨勢，現今半導體 裝置多朝向低成本、高性能以及高度集積化之方向發展， 惟在半導體裝置之製造成本、性能性及記憶容量上力求改 良之餘，半導體裝置的體積以及整體厚度亦要求儘量精 巧，QFN ( Quad-Flat Non-leaded )封裝件因其成品整體 尺寸僅略大於其内所封裝之半導體晶片且得以低成本之導 線架形式（Leadframe Based)成批製作，現已成為傳統 封裝製品的主流。 經濟部智慧財產局員工消費合作社印製 製作QFN半導體封裝件一般係先在一具有晶片座及 多數導腳之導線架上接設有至少一片·半導體晶片，而後逐 一打線以多條金線提供半導體晶片以及該等導腳之間電性 導接’最後用一封裝膠體包覆該晶片。然而實施金線打線 作業時’常因導腳分布過於密集亦或晶片佈局（Lay out ) 複雜等因素導致打線後線弧彼此交錯穿插，使得金線間太 過靠近而發生電性干擾（Electric Interference );另外， 進行膠體封裝時 '較長的線弧隹往馬法承受模流衝擊而產 生金線偏移（Wire Sweep )甚至相互觸碰引發短路（Sh〇n ) 等問題。 再者，隨著覆晶型（Flip Chip )半導體封裝件的製程 發展愈綠成熟’應用鲜錫凸塊（Solder Bumps)回鮮至鋒 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 1 1638 498517 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（2 墊上作為電性藕接方法已曰趨普遍。相較於傳統銲接作業 逐一打線的導電方式，銲錫凸塊採用自動對位498517 A7 B7 V. Description of the invention (1 [Field of invention]: The present invention relates to a semiconductor package, in particular to a lead-pin-type semiconductor package in which a semiconductor chip is mounted on a lead frame. [Background of the Invention]: In order to cope with the development trend of thin, light and short electronic products, today's semiconductor devices are mostly developed towards low cost, high performance, and high integration. However, while improving the manufacturing cost, performance, and memory capacity of semiconductor devices, Volume and overall thickness are also required to be as delicate as possible. Because the overall size of the QFN (Quad-Flat Non-leaded) package is only slightly larger than the semiconductor chip packaged in it, it can be produced in batches in a low-cost leadframe based form. , Has become the mainstream of traditional packaging products. QFN semiconductor package printed and produced by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is generally first provided with at least one semiconductor chip on a lead frame with a chip holder and most guide pins. Then one by one wire to provide semiconductor chips and multiple guide pins with multiple gold wires "Electrical conductive connection" finally covered the chip with a packaging gel. However, when gold wire bonding operations are performed, often the lead pins are too densely distributed or the chip layout (Lay out) is complicated. , So that the gold wires are too close to each other to cause electrical interference (Electric Interference); In addition, when the gel is encapsulated, the 'longer wire arcs' are subjected to the impact of the mold current to the Marfa and the gold wires are even offset (Wire Sweep). It will cause problems such as short circuit (Shon). Furthermore, with the development of Flip Chip semiconductor packages, the process is greener and more mature. 'Solder Bumps' are applied to the paper size. China National Standard (CNS) A4 specification (210 x 297 mm) 1 1 638 498 517 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (2 pads have become more common as electrical connection methods. Compared to Conducting wires one by one for traditional soldering operations, solder bumps are automatically aligned
Angnment) —次楂接完成將更為省時省工；有鑑於此， 美國專利第5,677,567號案，以啊 Assembly，，揭露一種導線架覆晶技術（FiipAngnment) — the completion of the second connection will save time and labor; in view of this, US Patent No. 5,677,567, ah Assembly, discloses a wire frame flip chip
Leadframe)。如第5圖所示，是種覆晶到導線架上之封裝 裝置4包括一如鋼等金屬材質製成之導線架（未圖示）， 主由多數長短不一之導腳42所構成；複數片半導體晶片 43，其具有一作用表面43〇及一非作用表面431，且該作 用表面430上接置有多數之銲接銲墊432 ;多個銲錫凸塊 44,係植設於該等銲接銲墊432上，俾使晶片作用表 面430採面朝導腳42方式，在該等導腳42正反兩面上各 回銲固，接一晶片43 ;以及一形成於導腳42上用來包覆該 等半導體晶片43、之封裝膠體45。 ^ 此項技術之特徵在以覆晶方式將該半導體晶片43導 電銲接至該等導腳42上。回銲作業中當該等錫鉛合金（一 般為錫63/鉛37合金所構成之質軟金屬）材質之銲錫凸 塊44加熱達到一定溫度後，會發生潰縮（c〇Uapse)並 與該導腳42銲結接觸部421間產生瞬間金屬共熔 (Eutectic )，進而導引銲錫凸塊44及導腳42銲結接觸部 421間形成一層牢固銲結之，，界面合金共化物，， (Intermetallic Compound)薄層（未圖示），即係濕潤步 驟（Wettmg)。惟因該導線架（未圖示）係由銅等可焊性 金屬製成’具備優良的濕潤特性（Wetability )，使得輝錫 I紙張尺度適用中闘家標準（CNS)A4規格（21G X 297公愛) ~ --— 2 1638 -----------------¾----------------------，玎--------------------^ (請先閲讀背面之注意事項再塡寫本頁各攔) 498517 A7 B7 五、發明説明（3 ) 凸塊44銲妥至導線架（未圖示）上導腳42預設位置（即 銲、。接觸邛42 1 )後，仍然持續發生潰縮，熔融銲錫凸塊 44無限制地向外擴張灘滯於導腳42表面上，如第6圖所 示。銲錫凸塊過度潰縮的結果不僅令銲結接合部位產生脆 性（Brittleness)極易導致銲結結構破裂甚至電性失能； 同時半V體曰曰片與導腳間之高度差亦會因銲錫凸塊過度形 變（Def0rmatlon)而遽減，嚴重妨礙後續製程之實施。 基於上述問題，如第7圖所示，美國專利第6,〇6〇,769 號案”Flip Chip 〇n Leads Device，，另揭示一種於導腳42預 认位置上施加一銲料罩幕47 ( s〇lder Mask)，其上並開設 有至少一預設口徑之開口 47〇，俾供該等銲錫凸塊料對 應植接。該項技術特點係利用銲料罩幕47上之開口尺寸 S來限制銲錫凸塊44的潰縮量。當銲料罩幕47上的開口 (請先閲讀背面之注意事嗜再填寫本頁各攔) 裝 470 π 徑 愈 大 時’愈能允許銲·锡凸塊44往外擴 張（ 即 潰 縮量 愈 大 )， 相 對地該等銲錫凸塊44之船垂高度h 就愈 小 j 藉由 決 定銲 料 罩幕47之開口口徑控制銲錫凸塊 44 潰 縮 經 濟 量， 即 可 預 先 定義半導體晶片43與導腳42間之 T%度 差 4 Μ 部 智 避免銲 錫 凸 塊 出現過度潰縮之情形。 慧 財 產 但 於 導 線 架金屬表面上施以一銲料罩幕需 要經 過 的 局 員 製程 處 理 ( 如 網點印刷（Screen Printing)或光 微影 圖 案 工 消 費 化（ Photo-] lithographic Patterning)等）極為繁 瑣， 且 成 合 本極 昂 故 而 實際量產上相當困難。如若以改變 銲錫 凸 塊 十工 印 製 本身 材 質 組 成 ’例如調高錫錯合金之錯比例（錫 5/錯 95) 來提 高 鲜 錫 凸 塊溶點，雖能避免銲錫凸塊過度潰 縮， 該 本紙張尺度適用中國國家標準各（210 297公爱)-----1~ - 3 1638 -訂 .線 498517Leadframe). As shown in FIG. 5, a package device 4 that is flip-chip bonded to a lead frame includes a lead frame (not shown) made of a metal material such as steel, and is mainly composed of a plurality of guide legs 42 of different lengths; A plurality of semiconductor wafers 43 having an active surface 43 and a non-active surface 431, and the active surface 430 is connected with a plurality of solder pads 432; a plurality of solder bumps 44 are implanted in these solders On the bonding pad 432, the wafer active surface 430 is faced to the guide pin 42, and the front and back sides of the guide pin 42 are soldered back to each other, and a wafer 43 is connected; and a guide pin 42 is formed for covering. The semiconductor wafers 43 and the encapsulants 45. ^ The feature of this technology is that the semiconductor wafer 43 is conductively soldered to the guide pins 42 in a flip-chip manner. When the solder bump 44 made of tin-lead alloy (generally a soft metal composed of tin 63 / lead 37 alloy) is heated to a certain temperature during reflow operation, it will collapse (c〇Uapse) An instantaneous metal eutectic occurs between the soldering contact portions 421 of the guide pins 42, and further, a strong solder joint is formed between the solder bump 44 and the soldering contact portions 421 of the guide pins 42. Intermetallic Compound) thin layer (not shown), that is, the wet step (Wettmg). However, because the lead frame (not shown) is made of a solderable metal such as copper, it has excellent wettability, making the tin tin I paper size applicable to the China Standard (CNS) A4 specification (21G X 297) Love) ~ --- 2 1638 ----------------- ¾ ----------------------, 玎-------------------- ^ (Please read the precautions on the back before transcribing each block on this page) 498517 A7 B7 V. Description of the invention (3) Bump 44 After soldering to the preset position of the upper guide pin 42 of the lead frame (not shown) (ie, soldering. Contact 邛 42 1), the collapse continues, and the molten solder bump 44 expands outward without restriction. The surface of the foot 42 is shown in FIG. 6. The result of excessive collapse of the solder bumps not only causes brittleness at the joints of the solder joints, which can easily lead to the cracking of the solder joint structure or even electrical disability. At the same time, the height difference between the half-V body chip and the guide pin will also be caused by soldering. Excessive deformation of the bumps (Def0rmatlon) reduces them, which seriously hinders the implementation of subsequent processes. Based on the above problem, as shown in FIG. 7, US Patent No. 6, 〇6〇, 769 "Flip Chip On Leads Device," further discloses a method of applying a solder mask 47 on a predetermined position of the guide pin 42 ( solder Mask), which is provided with at least one preset caliber opening 47o, for the corresponding solder bumps to be planted. This technical feature is the use of the opening size S on the solder mask 47 to limit The amount of shrinkage of the solder bump 44. When the opening on the solder mask 47 (please read the precautions on the back before filling in the blocks on this page), the larger the diameter of 470 π is, the more solder soldering is allowed. Expand outward (that is, the larger the amount of collapse), the smaller the vertical height h of the solder bumps 44 is. The more economical the collapse of the solder bumps 44 can be controlled by determining the opening diameter of the solder mask 47. The T% difference between the semiconductor wafer 43 and the guide pin 42 is defined in advance as 4 MW. To avoid excessive shrinkage of the solder bumps, it is necessary to pass a proprietary process to apply a solder mask on the metal surface of the lead frame. Processing (eg net Screen printing or photo-lithographic patterning is extremely cumbersome, and the cost is very high, so it is very difficult to mass-produce it. If you change the solder bumps, you can print the material itself. The composition 'for example, the tin ratio of tin alloy is increased (tin 5/95) to increase the melting point of fresh tin bumps, although the solder bumps can be prevented from shrinking excessively. Love) ----- 1 ~-3 1638-Order. Line 498517
經濟部智慧財產局員工消費合作社印製 方法之鲜錫凸塊成本往往增加兩倍以上。 【發明概述】： 本發明之主要目的係、提供—種晶片座與導腳間產生 適當高度差之導線架，使一半導體晶片以多數鲜錫凸塊回 鲜至該等導腳上時，得藉晶片座阻擋而抑制焊錫凸塊過度 潰縮，俾確保封裝結構之晶片與導腳間維持預設高度，並 可提昇銲錫凸塊的銲接信賴性之半導體封裝件。 本發明之另一目的係提供一種具有優良散熱功能之 晶片座之導線架，使一半導體晶片藉多數銲錫凸塊回銲至 該導線架上後’晶片與晶片座間相互接合而令晶片表面熱 量得藉晶片座快速釋除，進而增進封裝件整體散熱效能之 半導體封裝件。 為達引揭及其他目的’本發明抑制過度潰縮之半導 體封裝件係包括：一如鋼等金屬材質之導線架，其具有一 日日片座及夕數導腳’其中該晶片座高度須大於該等導腳厚 度’且晶片座與導腳間之高度差不得超過提供覆晶之鲜錫 凸塊的錯垂局度’復於該莫腳卜猫土 忑¥腳上預先定義出複數個提供銲 錫凸塊對應接置之輝結接觸部；一絕緣性導熱夥黏劑，係 塗佈於該晶片座頂面，以供回銲後晶片與晶片座間之黏 接’至少一片半導體晶片，藉以該等銲錫凸塊將晶片覆晶 回銲至導腳之銲結接觸部上’以及—形成於該導線架上用 以包覆該半導體晶片之封裝膠體。 上述封裝裝置施以回銲加熱達—定溫度後，低炼點 之質軟銲錫凸塊開始溶融潰縮，惟鋼質材料導線架具備優 G張尺度適用中國國家標準χ 297公jyThe cost of fresh tin bumps printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs tends to more than double. [Summary of the invention]: The main purpose of the present invention is to provide a lead frame that generates an appropriate height difference between the wafer holder and the guide pins, so that a semiconductor wafer can be refreshed to these guide pins with most fresh tin bumps. The semiconductor package which prevents the solder bump from being excessively collapsed by the chip holder blocking, and ensures a preset height between the chip and the lead of the packaging structure, and can improve the soldering reliability of the solder bump. Another object of the present invention is to provide a lead frame of a wafer holder with excellent heat dissipation function, so that a semiconductor wafer can be re-soldered to the lead frame by a plurality of solder bumps. A semiconductor package that is quickly released by a chip holder, thereby improving the overall heat dissipation performance of the package. For the purpose of revealing and other purposes, the semiconductor package for suppressing excessive collapse of the present invention includes: a lead frame made of metal such as steel, which has a day-to-day chip holder and a number of guide pins. Greater than the thickness of these guide feet 'and the height difference between the wafer holder and the guide feet must not exceed the misalignment of the fresh tin bumps provided by the flip chip'. Provide solder bumps corresponding to the glow junction contacts; an insulating thermal conductive adhesive is applied to the top surface of the wafer holder for bonding between the wafer and the wafer holder after re-soldering. The solder bumps re-bond the wafer to the solder joint contacts of the guide pins' and-the package gel formed on the lead frame to cover the semiconductor wafer. After the above packaging device is subjected to reflow heating to a fixed temperature, the low-melting-point soft solder bumps begin to melt and collapse, but the steel material lead frame has excellent G-gauge dimensions and applies to Chinese national standards χ 297 male jy
(請先閲讀背面之注意事項再塡寫本頁各攔) •裝 ;訂· .線 1638 498517 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（5 ) 良的濕潤特性（Wetability )，會持續引導銲錫凸塊潰縮， 使得半導體晶片受本身重量牵引而逐漸下移；當半導體晶 片壓接至絕緣性導電膠黏層後，晶片移動會受到較大高度 之晶片座阻擋而停滯，迫使銲錫凸塊停止繼續潰縮而維持 一固定高度。 藉由晶片座與周圍導腳平面之高度差來決定銲錫凸 塊的潰縮量’能讓晶片與導腳間保有適當距離俾利後續製 程進行；並且’藉由晶片座阻擋以抑制銲錫凸塊持續潰縮， 亦能避免鋅結接合部位因過度潰縮導致脆性產生，確保銲 結結合部位之結構強度以及電性品質。 【圖式簡單說明】： 以下兹以具體實施例配合所附圖式詳細說明本發明 之特點及功效： 第1圖係為本發明第一實施例之QFN半導體封裝件 之剖面示意圖； 第2A圖係為本發明第一實施例之半導體封裝件中該 導線架之上視圖； Λ 第2Β圖係為第2Α圖剖面線2Β_2Β所示之封裝結構 剖面示意圖； 第2C至2D圖係為本發明第一實施例之半導體封裝 件之製作流程圖； 第3Α圖係為本發明第二實施例之Qfn半導體封裝 件之剖面示意圖； 又 第3B圖係為本發明第二實施例之半導體封裝件局部 7紙張尺度適用中國國家標準（CNS)八4規格⑵〇 x 297公 -------— 請 先 閲 讀 背 面 之 注 意ί考i 再 I 填 ·· 寫 I 本 丨丨Ϊ : 攔 ： 訂(Please read the precautions on the back before transcribing each page of this page) • Binding; Ordering · Line 1638 498517 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (5) Good Wetability (Wetability ), Will continue to guide the solder bump to collapse, so that the semiconductor wafer is gradually moved down by its own weight; when the semiconductor wafer is crimped to the insulating conductive adhesive layer, the wafer movement will be blocked by the larger height of the wafer holder and stagnate. To force the solder bumps to stop collapsing and maintain a fixed height. Determining the amount of solder bump shrinkage by the height difference between the chip holder and the surrounding guide pin planes 'allows the chip and the guide pins to maintain an appropriate distance to facilitate subsequent processes; and' blocking by the chip holder to suppress solder bumps Continued collapse can also avoid the occurrence of brittleness caused by excessive collapse of the zinc junction joints, ensuring the structural strength and electrical quality of the joints. [Brief description of the drawings]: The following is a detailed description of the features and effects of the present invention with specific embodiments and the accompanying drawings: FIG. 1 is a schematic cross-sectional view of a QFN semiconductor package according to the first embodiment of the present invention; FIG. 2A It is a top view of the lead frame in the semiconductor package of the first embodiment of the present invention; Λ FIG. 2B is a schematic cross-sectional view of the packaging structure shown by the section line 2B_2B in FIG. 2A; and FIGS. 2C to 2D are the first sections of the present invention. FIG. 3A is a schematic cross-sectional view of a Qfn semiconductor package according to a second embodiment of the present invention; and FIG. 3B is a partial view of a semiconductor package according to the second embodiment of the present invention. The paper size is applicable to China National Standard (CNS) 8 4 specifications ⑵〇x 297 Male ----------- Please read the note on the back first, then I fill in, · write I this book 丨 Ϊ: stop: order
線 8 3 6 498517 A7 B7 五、發明説明（6 剖面放大圖； 第4圖係為本發明第三實施例之半導體封裝件之剖 面示意圖； 第5圖係為美國專利第5,677,567號揭露之半導體封 裝件之剖面示意圖； 第6圖係為習知導線架結構上進行銲錫凸塊回銲之 狀態示意簡圖；以及， 第7圖係為美國專利第6,〇6〇,769號揭露之半導體封 裝件之剖面示意圖。 【發明詳細說明】： 以下即配合第1圖至第3圖以及第4圖分別詳細說 明本發明抑制過度潰縮之半導體封裝件之兩實施例。其 中，尤以晶片座直接電性導接外部裝置之QFN封裝產品 最具實用性，遂將QFN半導體封裝件作為最佳具體例例 釋之。 篇一實施例： 經濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁各攔) 如第1圖所示，本發明第一實施例之抑制過度潰縮 之半導體封裝件1係包括一導線架10,係具有一晶片座u 及其外圍環設之多數導腳12，且該晶片座〗丨高度係大於 該等導腳12厚度俾形成一預設高度差；至少一半導體晶 片13，以其作用表面13〇朝向該晶片座u方式，藉多數 銲錫凸塊14回銲固接至該等導腳12上；一絕緣性導熱膠 黏劑 112 ( Non-conductive thermal adhesive)，用以塗佈 於該晶片座上，俾使回銲完成後該半導體晶片1 3得萨之 本紙張尺度適用中國國家標準（CNS)A4規格（21〇X297公釐） 6 1638 桃517 A7 B7 五、發明説明（7 ) " 黏接於該晶片座11上；以及一形成於該導線架丨〇上用以 包覆該半導體晶片13之封裝膠體15。 參閱第2A圖（上視圖）及第2B圖（剖視圖）所示， 該導線架10係包含一晶片座n及其外圍環設之多數導腳 12,其中該晶片座u及該等導腳12上各具有一晶片承接 面110及一導腳頂面12〇;此導線架1〇係由如銅或鐵鎳 合金等金屬材質製得，藉以習用之衝壓（punch)方法將 該晶片座11中央部衝製成一高度大於導腳12厚度之隆起 部111 ’且其隆起部i i i之晶片承接面i i 〇距離該導腳頂 面120之南度差不得超過該等銲錫凸塊（未圖示）未回銲 前之原始高度’而按預先定義的潰縮量設計之。 經濟部智慧財產局員工消費合作社印製 又在該等導腳頂面120上另界定有至少一個提供該 等婷錫凸塊（未圖示）對應銲接其上之銲結接觸部121， 由於導腳12本身係銅等可焊性強之金屬材質所構成，具 有優良的濕潤特性（Wetability )，遂無須再於該銲結接觸 部121上另鍍銀、鎳等助銲金屬層。待此導線架1〇製作 凡成後’於該晶片座1 1隆起部i J 1之晶片承接面J j 〇上 塗佈一絕緣性導熱膠黏劑（如第2C圖112所示），即能 續行覆晶步驟。 如第2C圖所示，該半導體晶片13，其具有一作用表 面130 (即舖設有多數電子電路與電子元件之晶片表面） 及一相對之非作用表面131，且該作用表面13〇上接設有 複數個銲接銲墊132，以供多數錫鉛合金（如錫63/鉛3 7 等低溶點合金）之質軟金屬銲料（未圖示）銲結其上而形 本紙張尺度相中國國家標準(CNS)A4規格(21^7公釐) 7 1638 498517 五、發明説明（8 f複數個銲錫凸塊14 ;而後’藉以作用表面13〇朝向該 晶片座11方式將該植妥多數銲錫凸塊14之半導體晶片13 對位架接於該等導腳頂Φ 12G而使每—料凸塊Μ均接 置到相對應之銲結接觸部121上。由於該晶片座u隆起 部ηι之隆起高度H2小於鲜錫凸塊14之錯垂高度， 致使半導體晶片13與晶片座u隆起部ln間存在一間隙 t 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 W，遂知回銲實施前該半導體晶Μ 13實懸空於該絕緣性 導熱膠黏層112的上方。 然而，待回銲加熱到一定溫度後，如第2D圖所示， 低熔點合金之質軟銲錫凸塊14開始溶融潰縮（collapse)， 則該半導體晶13受本身重量牽引而逐漸下移。由於導 腳12具有良好濕潤特性，會持續引導鲜錫凸塊μ產生潰 縮導致晶片13不斷向下移動，惟當該半導體晶片13之作 用表面130壓接至絕緣性導電膠黏劑112後，晶片移 動會受到晶片座U隆起部U1的阻擋而停滯，迫使該等 銲錫凸塊14停止繼績潰縮以維持一固定高度，因而晶片 13與導腳12間得保有一適當間距不致妨害後續製程實 施，且該等銲錫凸塊14與導腳12㈤形成之焊結接合部位 更不會因潰縮過度而引發脆性產生。 此外，由於本發明實施例之封裝裝置係為一 qfn半 導體封裝件，因此回銲完成之半導體晶片13藉一導熱膠 黏層112接置至該晶片座n之晶片承接面11〇後，晶片 1 3運作產生的熱量能夠糟由傳熱性佳之晶片座11快速散 除，因此對於封裝件散熱效能之提昇以及晶片性能的：維護 本紙張尺度通用中國國家標準（CNS)A4規格（210 X 297公爱） 498517 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（ 均有裨益。 第二實施彳 ，如帛3A _所示，本發明之半導體封裝件除如同上揭 第一實施例中，以衝壓（Punch )方式製 ., 衣补一具有隆起部 (未圖示）之晶片座（未圖示）外，亦得採用本實施例製 法’選擇在該等導腳22上，半姓（Half_etching)形成複 數個提供銲錫凸塊24植置之銲結接觸部222，且該銲許 接觸部222之深度乃係配合銲錫凸塊24之潰縮量預製= 成。當此封裝裝置2進行回銲步驟時，如第3B圖所示， 該等銲錫凸塊24熔融潰縮導致晶片23下移；則該半導體 晶片23之作用表面230壓接至絕緣性導熱膠黏劑212後， 晶片23移動會受到晶片座21的阻擋而停滯。因此，利用 半姓方式令使該晶片座21與銲結接觸部222間構成一適 當高度差H3仍可獲得與前實施例晶片座隆起部（未圖示' 相同之功效，俾有效地控制銲錫凸塊之潰縮。 第三實施例： 如第4圖所示，本發明第三實施例之半導體封裝件 其結構大致同於前述第一實施例，惟不同處在於該覆晶結 構係應用 QFP ( Quad Flat Package )或 TSOP ( Thin Smal]Line 8 3 6 498517 A7 B7 V. Description of the invention (6 enlarged sectional view; Figure 4 is a schematic cross-sectional view of a semiconductor package according to a third embodiment of the present invention; Figure 5 is a semiconductor package disclosed in US Patent No. 5,677,567 Figure 6 is a schematic diagram showing the state of solder bump reflow on a conventional lead frame structure; and Figure 7 is a semiconductor package disclosed in US Patent No. 6,060,769 [Detailed description of the invention]: The following is a detailed description of two embodiments of the semiconductor package for suppressing excessive shrinkage of the present invention with reference to Figs. 1 to 3 and 4 respectively. Among them, the wafer holder directly QFN packaging products that are electrically connected to external devices are the most practical, so QFN semiconductor packages are taken as the best concrete example. Article 1 Example: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the back first) (Notes on this page are to be filled out again.) As shown in FIG. 1, the semiconductor package 1 for suppressing excessive collapse according to the first embodiment of the present invention includes a lead frame 10 and a wafer holder u. The majority of the guide pins 12 and its peripheral ring are provided, and the height of the wafer seat is greater than the thickness of the guide pins 12 to form a preset height difference; at least one semiconductor wafer 13 with its active surface 13 facing the wafer seat. In the u method, most of the solder bumps 14 are re-welded and fixed to the guide pins 12; an insulating non-conductive thermal adhesive 112 (Non-conductive thermal adhesive) is used to coat the wafer base, and the back After soldering, the semiconductor wafer 1 3 The paper size of Tessa is applicable to the Chinese National Standard (CNS) A4 (21 × 297 mm) 6 1638 Peach 517 A7 B7 V. Description of the invention (7) " Adhesion to the wafer A base 11; and an encapsulant 15 formed on the lead frame for covering the semiconductor wafer 13. Referring to FIG. 2A (top view) and FIG. 2B (cross-sectional view), the lead frame 10 is It includes a wafer holder n and a plurality of guide pins 12 arranged on its periphery. The wafer holder u and the guide pins 12 each have a wafer receiving surface 110 and a guide pin top surface 120. The lead frame 10 is Made from metal materials such as copper or iron-nickel alloys ) Method The central portion of the wafer base 11 is punched into a raised portion 111 ′ having a height greater than the thickness of the guide pin 12, and the wafer receiving surface ii of the raised portion iii of the wafer is not greater than 120 degrees south from the top surface of the guide pin. The original height of the solder bump (not shown) before re-soldering is designed according to a predefined amount of shrinkage. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed on the top surface 120 of these guide pins. At least one solder joint contact portion 121 provided with these Ting tin bumps (not shown) is provided, and the guide pin 12 itself is made of a highly solderable metal material such as copper, and has excellent wettability characteristics. ), It is no longer necessary to plate another soldering metal layer such as silver or nickel on the solder contact 121. After the lead frame 10 is manufactured, an insulating and thermally conductive adhesive (as shown in FIG. 2C and FIG. 112) is coated on the wafer receiving surface J j 〇 of the raised portion i J 1 of the wafer base 11, that is, Can continue the flip-chip step. As shown in FIG. 2C, the semiconductor wafer 13 has an active surface 130 (ie, a wafer surface on which most electronic circuits and electronic components are laid) and an opposite non-active surface 131, and the active surface 13 is connected to the active surface 130. There are a plurality of solder pads 132 for most soft solders (not shown) of most tin-lead alloys (such as low melting point alloys such as tin 63 / lead 3 7) to be bonded thereon. Standard (CNS) A4 specification (21 ^ 7 mm) 7 1638 498517 V. Description of the invention (8 f plurality of solder bumps 14; then 'the active surface 13 is directed toward the wafer base 11 way to implant the majority of the solder bumps. The semiconductor wafer 13 counter-frame of block 14 is connected to the tops of these guide pins Φ 12G, so that each material bump M is connected to the corresponding soldering contact portion 121. Because of the bulge of the raised portion η of the wafer holder u The height H2 is smaller than the staggered height of the fresh tin bumps 14, resulting in a gap between the semiconductor wafer 13 and the bump ln of the wafer holder u. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed W, and it was known that the semiconductor crystal Μ 13 is suspended in the insulation guide Above the adhesive layer 112. However, after the reflow is heated to a certain temperature, as shown in FIG. 2D, the soft solder bump 14 of the low melting point alloy begins to melt and collapse, and the semiconductor crystal 13 is affected by itself. The weight is pulled and gradually moved down. Because the guide pin 12 has good wetting characteristics, it will continuously guide the fresh tin bump μ to collapse and cause the wafer 13 to continue to move downward, but when the active surface 130 of the semiconductor wafer 13 is crimped to insulation After the conductive adhesive 112, the wafer movement will be stopped by the bump U1 of the wafer holder U1, forcing the solder bumps 14 to stop shrinking to maintain a fixed height, so the wafer 13 and the guide pin 12 must be maintained. An appropriate distance does not hinder the implementation of subsequent processes, and the joints formed by the solder bumps 14 and the guide pins 12㈤ will not cause brittleness due to excessive collapse. In addition, the packaging device of the embodiment of the present invention is A qfn semiconductor package, so after the reflowed semiconductor wafer 13 is connected to the wafer receiving surface 110 of the wafer holder n by a thermally conductive adhesive layer 112, the heat generated by the operation of the wafer 13 can be The problem is quickly dissipated by the wafer holder 11 with good heat transfer performance, so for the improvement of the heat dissipation efficiency of the package and the performance of the wafer: maintenance of this paper standard Common Chinese National Standard (CNS) A4 specification (210 X 297 public love) 498517 A7 B7 Economy Printed by the Consumers ’Cooperative of the Ministry of Intellectual Property Bureau. 5. Description of the invention (both are beneficial. The second implementation, as shown in 3A _, except that the semiconductor package of the present invention is punched (Punch) as in the first embodiment disclosed above. ) System. In addition to a wafer holder (not shown) with a bulge (not shown), the method of this embodiment can also be used to select the guide pins 22 and the half name (Half_etching) to form a plurality. A solder contact portion 222 provided with solder bumps 24 is provided, and the depth of the solder contact portions 222 is prefabricated with the collapse amount of the solder bumps 24. When the packaging device 2 performs the re-soldering step, as shown in FIG. 3B, the solder bumps 24 melt down and cause the wafer 23 to move downward; then, the active surface 230 of the semiconductor wafer 23 is crimped to the insulating thermally conductive adhesive After the agent 212, the movement of the wafer 23 is blocked by the wafer holder 21 and stops. Therefore, by using the half-name method to make a suitable height difference H3 between the wafer holder 21 and the soldering contact portion 222, the same effect as that of the wafer holder raised portion (not shown in the previous embodiment) can be obtained, and the solder can be effectively controlled. The collapse of the bumps. Third embodiment: As shown in FIG. 4, the structure of the semiconductor package of the third embodiment of the present invention is substantially the same as that of the first embodiment, except that the flip-chip structure uses QFP. (Quad Flat Package) or TSOP (Thin Smal)
Outline Package )等封裝方式，形成一具有多數如j形或 翼形（Gull Wing)外導腳32之半導體封裝件3。利用衝 壓方式在多數導腳32上形成向下下沉之銲結接觸部322 亦得使該晶片座31之晶片承接面310與導腳32間形成一 配合銲錫凸塊34潰縮量之適當高度差，而達成與上述各 (請先閲讀背面之注意事項‘再塡寫本頁各攔) 訂· •線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 9 1638 11 5 8 9 A7 B7 五、發明説明（10 ) 實施例同等之功效。 以上所述僅為本發明之較佳實施例而已，並非用以 限定本發明之實質技術内容範圍。本發明之實質技術内容 係廣義地定義於下述之申請專利範圍中。任何他人所完成 之技術實體，若與下述之申請專利範圍定義者係完全相 同，或為一等效之變更，均將視為涵蓋於此專利範圍之中。 【符號標號說明】： 經濟部智慧財產局員工消費合作社印製 1，2,3,4 半導體封裝件 10 導線架 11，21，31 晶片座 110,310 晶片承接面 111 晶片座隆起部 112,212,312 絕緣性導熱膠黏層 12,22,32,42 導腳 120,320 導腳頂面 121 銲結接觸部 421 導腳金屬接觸面 222,322 淺槽 13,23,33,43 半導體晶片 130,230,430 晶片作用表面 131,331,431 晶片非作用表面 132,432 銲接銲墊 14,24,34,44 鲜錫凸塊 15,25,35,45 封裝膠體 36 内嵌式散熱件 47 銲料罩幕 470 銲料罩幕開口 Hl，h 銲錫凸塊高度 H2 晶片座隆起部高度 H3 晶片座與銲結接觸部之高度差 W 晶片與隆起部間隙 S 銲料罩幕開口尺寸 -----------------^----------------------’玎--------------------^ (請先閱讀背面之注意事項再塡寫本頁各攔) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 10 1638Outline Package) and other packaging methods to form a semiconductor package 3 with a large number of J-shaped or wing-shaped (Gull Wing) outer guide pins 32. Forming a sinking solder contact portion 322 on most of the guide pins 32 by stamping also requires an appropriate height of the solder bumps 34 to be formed between the wafer receiving surface 310 of the wafer base 31 and the guide pins 32. Poor, and achieved the above (please read the notes on the back first, and then write the blocks on this page) Order · • The paper size of the thread applies the Chinese National Standard (CNS) A4 (210 X 297 mm) 9 1638 11 5 8 9 A7 B7 V. Description of the invention (10) The embodiment has the same effect. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of the following patent applications. Any technical entity completed by others that is completely the same as the definition of the scope of patent application below, or an equivalent change, will be considered to be covered by this patent scope. [Symbol description]: Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, 1, 2, 3, 4 Semiconductor packages 10 Lead frames 11, 21, 31 Wafer holders 110, 310 Wafer receiving surfaces 111 Wafer holders 112, 212, 312 Insulating thermal adhesive Adhesive layer 12, 22, 32, 42 Guide pin 120, 320 Top of guide pin 121 Soldering contact 421 Guide metal contact surface 222, 322 Shallow grooves 13, 23, 33, 43 Semiconductor wafer 130, 230, 430 Wafer active surface 131,331,431 Wafer non-active surface 132,432 Solder Solder pads 14, 24, 34, 44 Fresh tin bumps 15, 25, 35, 45 Encapsulated gel 36 Embedded heat sink 47 Solder mask 470 Solder mask opening H1, h Solder bump height H2 Wafer bump height H3 The difference in height between the wafer holder and the junction contact W The gap between the wafer and the bump S Solder mask opening size ----------------- ^ --------- ------------- '玎 -------------------- ^ (Please read the precautions on the back before writing each (Block) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 10 1638