TW498432B - Photoresist protect oxide material - Google Patents

Abstract

A photoresist protect oxide material can be applied on a semiconductor device, particularly on a sub-micron semiconductor device, in which the photoresist protective oxide layer material comprises a Si-rich chemical vapor deposited oxide having a refractive index of about 1.57 to 1.6, to prevent Si atoms from diffusing from the polysilicon film layer to the photoresist protective oxide layer.

Description

498432 V. Description of the invention (1) Field of the invention: The present invention relates to the manufacturing process of integrated circuit elements, and particularly provides a coating method of photoresist protect oxide (RPO) to eliminate polycrystalline stone Void defects are generated. BACKGROUND OF THE INVENTION: The manufacture of complementary metal-oxide-semiconductor (CMOS) devices is a well-established semiconductor technology. With the continuous shrinking demand of semiconductor elements, in order to obtain better element performance at a more competitive cost, the size of semiconductor elements must be continuously reduced, and the thickness of the different semiconductor material film layers used to manufacture semiconductor elements must also be reduced. Must be continuously lowered. When forming complementary metal-oxide-semiconductor elements on the surface of a substrate, elements of different polarities, such as complementary metal-oxide-semiconductor elements and N-channel metal-oxide-semiconductor (NM0S) elements, can be fabricated on the surface of a substrate and treated as Part of a continuous manufacturing process. That is, some of these different components can be processed according to different manufacturing processes. For example, some components have low-resistance contacts for self-aligned silicide (salicide) of complementary metal-oxide semiconductor devices. Manufacturing process; however, other components also manufactured on the same substrate surface have not undergone the self-aligned metal silicide low-resistance contact manufacturing process for complementary metal-oxide semiconductor devices. Therefore, when manufacturing a complementary metal-oxide-semiconductor device on a substrate surface,

Page 5 498432 V. Description of the invention (2) The manufacturing process required for different components is somewhat different. Usually, a photoresist protective oxide layer must be coated on some components. An example of the difference in the manufacturing process of a complementary metal-oxide-semiconductor device on the surface of a substrate can be described by taking the fabrication of self-aligned contacts on the source / drain region of the complementary metal-oxide-semiconductor device and the gate electrode as examples. A complementary metal-oxide-semiconductor device fabricated by covering a photoresist protective oxide layer on the completed gate structure (including fabrication of the gate spacer) (the complementary metal-oxide semiconductor device is formed on a substrate surface) The complementary metal-oxide-semiconductor device can be divided into: a device that needs to perform an electrical contact process of self-aligned metal silicide and a device that does not need to perform an electrical contact process of self-aligned metal silicide. Among the above-mentioned components that do not need to perform the self-aligned metal silicide electrical contact manufacturing process, a photolithography process can be used to cover a photoresist layer thereon, and the self-aligned metal lithosol electrical contact needs to be performed In the manufacturing process, the photoresist layer is used as a mask to remove the photoresist protective oxide layer thereon. In this way, the exposed surface after the photoresist protective oxide layer is removed, the electrical contact process of the self-aligned metal silicide can be performed separately. As the size of components continues to shrink, the thickness of the photoresist protective oxide layer must be further reduced, and the quality of the deposited photoresist protective oxide layer must be further improved. The quality of the photoresist protective oxide layer is usually obtained by using parameters such as Field-to-Breakdown and Charge-to-Breakdown. One of the problems encountered in the generation of sub-micron device sizes is: the interface between the polycrystalline silicon film layer and the photoresist protective oxide layer used to manufacture the gate structure 498432 V. Invention Description (3) There are holes. Therefore, in order to prevent the above-mentioned holes from being generated, the present invention provides a method for controlling the quality of the photoresist protective oxide layer. For related know-how, please refer to the following US invention patents: (1) For the related description of the photoresist protective oxide layer, please refer to US Patent No. 6,207,492 (Tz e n g e t a 1 ·). (2) For a description of the anti-reflective coating (ARC) layer of silicon rich oxide, please refer to US Patent No. 6,174,590 (I yereta 1 .) And Patent No. 6,16, 7 2 2 (Hsu). (3) For other related technologies, please refer to US Patent No. 6,194,258 (Wuu) and Patent No. 6, 1 8 7,6 5 5 (Wang Purpose and Summary of the Invention: The main purpose of the present invention is to provide a photoresist A method for forming a protective oxide layer to avoid forming a hole between the photoresistive protective oxide layer and the polycrystalline silicon layer of the gate structure thereunder. The photoresistive protective oxide layer of the new material provided by the present invention is applied to a semiconductor device, particularly It is applied to semiconductor elements with sub-micron size. The material of the photoresist protective oxide layer of the present invention contains a silicon-rich chemical vapor phase 498432 V. Description of the invention (4) The deposited oxide has a refractive index of about 1 5 7 ~ 1.6 can prevent silicon atoms from diffusing from the polycrystalline silicon film layer into the photoresist protective oxide layer. Detailed description of the invention: Please refer to FIG. 1 ', which is a cross-sectional view of a semiconductor wafer. Element structure: a semiconductor substrate surface 10. Two gate structures 12 and 14 are manufactured on the semiconductor substrate surface 10. An insulating region (such as a field oxide region or The trench trench isolation area 16 is manufactured between two gate structures 12 and 14 to electrically isolate the two gate structures 12 and 14 from each other. A gate oxide layer 1 8, manufactured on the surface of the semiconductor substrate 10, which includes the use of chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or semiconductor The substrate surface 10 is formed by being exposed to an oxidizing environment, wherein the gate oxide layer 18 has a thickness of about 300 to 500 angstroms, and preferably has a thickness of about 400 angstroms. Two gate structures 1 The gate electrodes 20 of 2 and 14 are made of polycrystalline silicon. After depositing the material film layer of gate electrode 20 on the surface of gate oxide layer 18, they are performed together with gate oxide layer 18. The gate junction 498432 shown in FIG. 1 is formed by the etching process. 5. Description of the Invention (5) The gate spacer 22 is formed on the sidewalls of the gate oxide layer 18 and the gate electrode 20. Lightly doped The drain / source electrodes 2 1 and 2 3 are formed by implanting impurity ions on the surface of the semiconductor substrate 10, and they are self-aligned. The gate electrode 20 at the gate structure 12. Lightly doped drain / source electrodes 25 and 27 are formed by implanting impurity ions on the surface of the semiconductor substrate 10 and are self-aligned to the gate. The gate electrode 20 of the electrode structure 14 is formed by implanting impurity ions on the surface of the semiconductor substrate 10, and it is self-aligned with the gate structure 12. The source / drain electrodes 35 and 37 are formed by implanting impurity ions on the surface of the semiconductor substrate 10, and are self-aligned to the gate structure 14. Please refer to FIG. 2, which is a cross-sectional view of a semiconductor wafer. In addition to including all the components in FIG. 1, the following components have been added: Photoresist protective oxide layer 2 4, which is deposited on the gate structure 1 2, 1 4 and exposed. The resulting semiconductor substrate surface 10 is used as a protection for the underlying film layer during subsequent processes. After the pattern transfer and development, the photoresist mask 26 is formed by forming a photoresist film layer on the surface of the photoresist protective oxide layer 24, and then removing a part of the photoresist film layer, and a part of the photoresist film layer The removal method can be achieved by wet stripping with an oxygen plasma and then using an aqueous solution of sulfuric acid, hydrogen peroxide and sodium hydroxide. The method for forming the photoresist protective oxide layer 24 includes chemical vapor deposition, low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition. If plasma enhanced chemical vapor deposition is used to form photoresist protection Oxide layer 2 4

Page 9 498432 V. Description of the invention (6) (If lower process temperature is required, plasma enhanced chemical vapor deposition method is needed), its thickness is about 3 0 ~ 5 0 0 angstroms, which is better. The thickness is about 4 0 Angstroms. In the present invention, the preferred material for the photoresist protective oxide layer 24 is silicon-rich CVD oxide, which has a preferred refractive index of about 1 · 5 7 ~ 1 · 6 ， The refractive index of the conventional conventional silicon dioxide film layer is about 1. 4 6. With the pattern transfer and development of the photoresist mask 26 shown in FIG. 2, the foregoing goal of applying different process steps to different gate structure elements can be achieved. For example, a portion of the photoresist protective oxide layer 24 not covered by the photoresist mask 26 is etched away, and the gate structure 12 is exposed to perform a self-aligned metal silicide process on the surface 10 of the semiconductor substrate. If the gate structure 12 described above is implanted with impurity ions, a lightly doped region and a non-source / source region of the gate structure 12 are formed, where the lightly doped region is self-aligned to the gate structure 12 Gate electrode, and the drain / source region is self-aligned to the gate structure 12. Since the photoresist protective oxide layer 24 on the gate structure 14 is not exposed to the impurity ion implantation, the photoresist protective oxide layer 24 on the gate structure 14 will not be damaged. The material of the photoresist protective oxide layer 24 used in the present invention includes silicon-rich CVD oxide. According to conventional experience, if a silicon-rich chemical vapor deposition oxide is used as the material of the photoresist protective oxide layer 24, the photoresist protective oxide layer 2 4

Page 10 498432 V. Description of the invention (7) The interface between the polycrystalline silicon film layer 2 0 of the square gate structure 12 and 14 can avoid the occurrence of holes. The cause of this phenomenon is the refractive index of the silicon-rich chemical vapor deposition oxide layer, which is approximately 1.57 to 1.6. Such a refractive index can prevent Shi Xi atoms from migrating from the polycrystalline ^ Xi film layer 20 into the photoresist protective oxide layer 24 of the chemical vapor deposition oxide made of rich Shixi, thus avoiding the polycrystalline silicon film Holes are created in layer 20. Experiments have confirmed that the use of silicon-rich chemical vapor deposition oxides as the material of the photoresist protective oxide layer 2 4 can consider the need to reduce the size of the component, that is, a thinner photoresist protective oxide layer 2 4 is necessary . The present invention is applied to a preferred embodiment of a sub-micron CMOS device, and has a channel length ranging from 0.18 μm or less. In order to further emphasize the advantages provided by the present invention, please refer to FIGS. 6 and 7, which show a cross-sectional view of a gate structure. As shown in Figure 6, a film layer 2 4 ′ made of a conventional oxide is deposited as a photoresistive protective oxide layer. It can be seen from FIG. 6 that there is a phenomenon that molecules in the multi-crystal layer 20 used as the gate electrode migrate into the film layer 2 4 ′. Therefore, there is a phenomenon between the film layer 2 4 ′ and the multi-crystal layer 20. Holes 3 9 were created on the interface. The gate structure 12 shown in FIG. 2 has been subjected to additional processing, that is, the film layer 2 4 ′ has been removed from the surface of the gate structure 12 described above. Generally, this additional treatment is used for self-aligned metal silicide processes, such as depositing a cobalt (Co) layer on the exposed surface of the gate structure 12, of course, including holes 3 9 on the surface of the gate structure 12. Also covered by drilling layers. In this way, the initial fragmentation (CoS i x) will be formed in the holes 39 of the gate structure 12, which is the main cause of the collapse of the gate oxide integrity (GO I). the reason.

Page 11 498432 V. Description of the invention (8) As shown in Figure 7, if the material of the photoresist protective oxide layer is a silicon-rich chemical vapor deposition oxide, then the holes 3 9 shown in Figure 6 will not It is formed on the interface between the photoresist protective oxide layer and the polycrystalline layer 20. Please refer to FIG. 3, which shows the cross-sections of the gate structures 12 and 14 after removing a part of the photoresist protective oxide layer 24 made of silicon-rich chemical vapor deposition oxide according to the photoresist mask 2 6. Illustration. Here, the exposed photoresist protective oxide layer 24 is etched by a buffered hydrofluoric acid wet etching process, and it needs to be in contact with an acidic solution at an elevated temperature. For example, the solution used for wet etching may be phosphoric acid, nitric acid, acetic acid, etc., and its temperature may be about 30 to 50 degrees Celsius.

Please refer to FIG. 4, which shows cross-sectional views of the gate structures 12 and 14 after the cobalt layer is deposited on the contact area of the gate structure 12. The region where the cobalt layer is deposited includes the surface of the drain / source region and the surface of the gate structure 12. The cobalt layer 44 deposited on the exposed surface of the gate structure 12 in FIG. 4 is then subjected to a tempering process to cause the cobalt layer 44 to react with the silicon surface below it to form cobalt silicide. One embodiment of the formation of the cobalt layer 44 can be formed at a temperature of about 25 to 300 degrees Celsius by using either a sputtering method or a chemical vapor deposition method to form about 50 to 150 angstroms. Thickness (preferably about 80 angstroms). Whereas, the ancient layer 44 in FIG. 4 will be formed after the tempering process as shown in FIG. 5, and the lithoxide layer 46 will be formed as shown in FIG. A rapid thermal tempering process (RTA) with an operating time of about 20 to 60 seconds under an atmospheric or nitrogen environment at 500 to 850 degrees (the pressures are all at atmospheric pressure)

Page 12 498432 V. Description of Invention (9)). Please refer to FIG. 5, which shows a cross-sectional view of the gate structures 12 and 14 after applying a tempering process to the cobalt layer 44 and removing the photoresist mask 26. The above-mentioned method for removing the photoresist mask 26 can use a conventional photoresist removal method, such as using sulfuric acid and mixing sulfuric acid with other oxidizing agents such as hydrogen peroxide to remove the photoresist. After the photoresist mask 2 6 is stripped, the wafer can be immersed in an environment at a temperature of about 100 to 150 degrees Celsius for about 5 to 10 minutes, and then cleaned with deionized water and used. Dry it with nitrogen. Stripping of inorganic photoresists, such as sulfuric acid mixtures, is highly effective for post removal of photoresist residues. Compared with organic photoresist stripping, the above method is more effective and has a longer immersion time to obtain a cleaner and less residual wafer surface. It can be clearly seen from the above process procedure that because silicon-rich chemical vapor deposition oxide is used as the material of the photoresist protective oxide layer 24, holes will not be formed in the polycrystalline silicon layer 2 of the gate structure 12 0 on the surface, thus avoiding the complex structure of the gate structure 1 2 of the polycrystalline silicon layer 2 0 on the surface of cobalt silicide deposited on the hole, which will not cause the gate oxide integrity (Gate 0 X ide Integrity , GO I). The above are only the preferred embodiments of the present invention, and do not limit the scope of patent application of the present invention;

Page 13 498432

Page 498 432 Brief Description of Drawings Figure 1 is a cross-sectional view of a semiconductor wafer, showing the steps of forming two gate structures separated from each other on a semiconductor substrate according to an embodiment of the present invention; Figure 2 is a cross-sectional view of a semiconductor wafer Shows a step of depositing a photoresist protective oxide layer on the entire semiconductor substrate and then forming a photoresist mask on a gate structure according to an embodiment of the present invention; FIG. 3 is a cross-sectional view of a semiconductor wafer, showing According to an embodiment of the present invention, the step of removing a portion of the photoresist protective oxide layer without the photoresist cover is covered; FIG. 4 is a cross-sectional view of a semiconductor wafer. Step of depositing a cobalt layer in the contact area of the covered gate structure; FIG. 5 is a cross-sectional view of a semiconductor wafer, showing that the formed cobalt layer is subjected to a tempering process and the photoresist mask is removed according to an embodiment of the present invention Steps; FIG. 6 is a cross-sectional view of a semiconductor wafer, showing that according to an embodiment of a conventional invention, a film layer made of a conventional oxide is used as a photoresist Holes were created on the surface of the polycrystalline silicon film layer of the gate structure due to the oxide protection layer; FIG. 7 is a cross-sectional view of a semiconductor wafer, showing that according to an embodiment of the present invention, a silicon-rich chemical vapor deposition oxide is used As a photoresist protective oxide layer, holes can be avoided on the surface of the polycrystalline silicon film layer of the gate structure. Drawing number part:

Page 15 498432 Simple illustration of the surface ·, 4 .—- 8 of, ·, 11 ·, 2 6 ο bottom r—H r—Η layer c ^ l base structured polarized body junction region oxygen conductivity pole edge pole Half gate absolute gate gate gap wall 2 2; lightly doped drain / source 2 2 3, 2 5, 2 7; source / non-pole 3 1, 3 3, 3 5, 3 7; material is Photoresist protective oxide layer 2 4 of rich chemical vapor deposition oxide; Material is photoresist protective oxide layer 2 4 'of traditional oxide; photoresist mask 2 6; holes 3 9; starting layer 4 4; drill的 碎 物 层 4 6。 The fragmented layer 4 6.

Claims (1)

498432 VI. Application Patent Scope 1. A method for forming a protective oxide layer on at least one gate structure, wherein the at least one gate structure is manufactured on the surface of a substrate, the method includes at least the following steps: providing a substrate, At least one gate structure is manufactured on the surface of the substrate. The at least one gate structure includes a gate dielectric layer and a polycrystalline stone layer on the gate dielectric layer. The at least one gate structure A self-aligned impurity ion implantation has been provided, and a gate spacer is provided on a sidewall of the at least one gate structure; a protective oxide layer is deposited on the surface of the at least one gate structure, and the protective oxide layer The material includes a silicon-rich chemical vapor deposition oxide having a refractive index of about 1.5 7 to 1.6. 2. The method according to item 1 of the patent application range, wherein the method for depositing the protective oxide layer includes a chemical vapor deposition method or a low pressure chemical vapor deposition method. 3. The method according to item 1 of the patent application, wherein the method for depositing the protective oxide layer includes a plasma enhanced chemical vapor deposition method. 4. The method according to item 1 of the patent application range, wherein the thickness of the protective oxide layer is about 300 to 500 angstroms, and the preferred thickness is about 400 angstroms. 5. The method of claim 1, wherein the at least one gate structure includes a metal-oxide-semiconductor field-effect transistor (MOSFET) device on a silicon substrate. Page 17 498432 6. Application for patent scope 6. The method according to item 5 of the patent application scope, wherein the channel length range of the above-mentioned metal-oxygen half field-effect transistor element is in the range of 0.8 micrometer or less than 0.8 micrometer. 7. The method according to item 1 of the patent application range, wherein the above-mentioned substrate includes a silicon substrate, and at least as little as the physical contact with the material. The metal is a semi-substrate of a self-forming siQul seed body. The last 8 yuan pole gate of its method in Haihai-5 is the first. At least there are: the basic steps listed in the table below to the bottom of the method to the bottom of the method. The basic requirements for the supply of the meter for the meter are as follows, which means that the electrode is reduced by the first contact of the pole gate, and the quasi-pole is broken. On the pole surface of the electric pole, the gate of the second pole is in contact with the second pole, and the second pole is reduced. At least the broken metal and the gold pole are quasi-electrical, and the pole pole is supplied by one pole. Need to be less than one by one should do less and when 'have fixed pole construction refers to the electrical system has been gated on the pole has been recharged one pole of the gate on the second layer of the first dielectric a dielectric pole to the gate should be connected to the pole And it consists of a layer of electricity, a dielectric layer and a few gates to one that should be included. Electrode fragmentation has been provided with self-aligned impurity ion implantation, and a gate spacer is provided on the side walls of the at least one first gate electrode and the at least one second gate electrode; a protective oxide layer is deposited on On the surface of the at least one first gate electrode, on the surface of the at least one second gate electrode, and on the exposed surface area of the substrate, the material of the protective oxide layer includes a refractive index of about P.18 498432 VI. Silicon-rich chemical vapor deposition oxide with a patent scope of 1.5 7 ~ 1.6; a photoresist mask is provided on the surface of the protective oxide layer, and the photoresist mask covers the A surface of the at least one second gate electrode and exposing the protective oxide layer deposited on the surface of the at least one first gate electrode; removing the protective oxide layer deposited on the surface of the at least one first gate electrode to Exposing the surface of the at least one first gate electrode, leaving the protective oxide layer deposited on the surface of the at least one second gate electrode; depositing a metal layer on the exposed surface of the at least one first gate electrode Tempering the metal layer to form a metal oxide layer on a contact area between the metal layer and the at least one first gate electrode; and removing the photoresist mask to expose and deposit on the at least one The protective oxide layer on the surface of the second gate electrode. 9. The method according to item 8 of the application, wherein the method for depositing the protective oxide layer includes a chemical vapor deposition method or a low pressure chemical vapor deposition method. 10 · The method according to item 8 of the scope of patent application, wherein the method for depositing the protective oxide layer includes a plasma enhanced chemical vapor deposition method. 11. The method according to item 8 of the scope of patent application, wherein the thickness of the protective oxide layer is about 300 to 500 angstroms, and the preferred thickness is about 400 angstroms. 1 2. The method of claim 8 in the scope of patent application, wherein at least one of the above second Page 19 498432 6. Scope of patent application The gate electrode includes a metal-oxide-semiconductor field-effect transistor (MOSFET) element on a silicon substrate. 13. The method according to item 12 of the scope of patent application, wherein the channel length range of the above-mentioned metal-oxygen half-field-effect transistor element is 0.18 microns or less. 14. The method according to item 8 of the patent application, wherein the at least one second gate electrode includes a metal-oxide-semiconductor field-effect transistor (MOSFET) element on a silicon substrate. 15. The method according to item 14 of the scope of patent application, wherein the channel length range of the above-mentioned metal-oxide-semiconductor half-field-effect transistor element is 0.18 micrometers or less. 16. The method according to item 8 of the patent application, wherein the substrate comprises a silicon substrate. 17. The method according to item 8 of the scope of patent application, wherein the material of the metal layer deposited on the exposed surface of the at least one first gate electrode includes a starting material. 1 8. The method according to item 8 of the scope of patent application, wherein the method of tempering the metal layer described above includes an atmosphere of about 500 to 850 degrees Celsius or a nitrogen environment (the pressure is an atmospheric pressure), A heat recovery time of about 20 to 60 seconds Page 20 498432 VI. Scope of patent application Fire. 19. The method according to item 8 of the patent application, wherein the method for removing the protective oxide layer deposited on the surface of the at least one first gate electrode comprises applying a buffered hydrofluoric acid wet etching process. Page 21