494521 五 經濟部中央標準局員工消費合作社印製 A7 B7 發明説明（1 ) 發明背景 1·發明領域 本發明係關於一種牵導體元件用之負載板，尤指一種 用以測試各種不同型式封裝之多封裝測試負載板。 本多封裝測試負載板申請案係以韓國申請案號No. S0720/1995爲基礎，其倂於此以爲所有目的之參考。 2·相關技術說明 在半導體元件之製造中，於將此種積體電路裝置裝設 入使用此等裝置之設備前，較佳先測試元件之操作特性。 該晶片測試系統一般而言以晶圓狀態型式與封裝狀態型式 爲特徵。因爲半導體元件可透過前述測試而具有利之良 率，故此種測試對半導體元件之製程而言係不可或缺者。 透過測試所發現之半導體元件中之缺陷可被補救，因此可 提供製造商完美的元件，而無法回復者則予以棄置。前述 之封裝狀態測試係以組裝方法測試包覆於一封裝中之主要 晶片。該封裝狀態測試係於被包裝之設置於負載片上之主 要晶片上進行。一種傳統負載板係被設計以測試一種型式 之封裝。換言之，一種負載板係用以測試相同型式之封裝。 若欲測試封裝之個別接腳配置根據主晶片之內部電路設計 而彼此不同，而每一種封裝形式彼此類似，則應使用一種 適合於每一型式欲測試封裝之負載板。當一種型式之封裝 以一種負載板測試時，可增進其測試精準度，且需要大量 負載板以測試各式不同的封裝，導致總生產成本之增加。 2 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 494521 A7 B7 五、發明説明（2 ) 發明槪沭 因此，本發明之一目的在於提供一種可測試各式不同 封裝之多封裝測試負載板。 本發明之另一目的在於提供一種可測試彼此結構相似 但接腳配置不同之封裝之多封裝測試負載板。 爲了達成上述目的，本發明提供一種半導體記憶裝置 用之多封裝測試負載板，其包括第一插孔元件，具有第一 預定數目之插孔；第二插孔元件，具有第二預定數目之插 孔；以及第三插孔元件，具有該第一預定數目之插孔；藉 此，若測試第一型式之封裝，則將該等封裝裝設於該第一 插孔元件與該第二插孔元件之一部分上，若測試第二型式 之封裝，則將該等封裝裝設於整個第一插孔元件與第三插 孔元件上，藉以利用單一負載板測試各種不同型式之封 裝。 簡單圖式說明 本發明之這些及各種特徵與優點將參閱以下之詳細說 明配合所附圖式而有較佳之了解，其中： 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 第一圖顯示根據本發明用以測試複數個皺縮雙排包裝 (SDIP)之具插孔負載板； 第二圖顯示根據本發明用以測試複數個四面扁平包裝 (QFP)之具插孔負載板； 第三A圖顯示用於第一圖與第二圖之每一負載板中跳 接線之狀態；以及 494521 A7 B7 i、發明説明（3 ) 第三B圖顯示沿D-D’線所取之截面圖 較佳實施例之詳細說明 本發明之一較佳實施例將參閱所附圖式加以詳細說 明。 第一圖顯示根據本發明用以測試複數個皺縮雙排包裝 (SDIP)之具插孔負載板。 請參閱第一圖，第一插孔元件10包含第一預定數目之494521 A7 B7 printed by the Consumer Cooperatives of the Central Bureau of Standards of the Five Ministry of Economics (1) Background of the Invention 1. Field of the Invention The present invention relates to a load board for lead-conducting components, especially a package for testing various types of packages. Package test load board. This multi-package test load board application is based on Korean Application No. S0720 / 1995, which is hereby incorporated by reference for all purposes. 2. Description of related technology In the manufacture of semiconductor devices, it is preferred to test the operating characteristics of the device before installing such integrated circuit devices into equipment using such devices. The wafer test system is generally characterized by a wafer state type and a package state type. Because semiconductor devices can have a favorable yield through the aforementioned tests, such tests are indispensable for the manufacturing process of semiconductor devices. Defects found in semiconductor components through testing can be remedied, thus providing the manufacturer with perfect components, and those who cannot respond are discarded. The aforementioned package state test is an assembly method for testing a main chip enclosed in a package. The package state test is performed on a main wafer packaged on a load chip. A conventional load board is designed to test a type of package. In other words, a load board is used to test the same type of package. If the individual pin configurations of the package to be tested are different from each other according to the internal circuit design of the main chip, and each package is similar to each other, a load board suitable for each type of package to be tested should be used. When a type of package is tested with a load board, the test accuracy can be improved, and a large number of load boards are required to test a variety of different packages, resulting in an increase in total production cost. 2 This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling out this page) 494521 A7 B7 V. Description of the invention (2) Therefore, one of the inventions The purpose is to provide a multi-package test load board that can test a variety of different packages. Another object of the present invention is to provide a multi-package test load board that can test packages with similar structures but different pin configurations. In order to achieve the above object, the present invention provides a multi-package test load board for a semiconductor memory device, which includes a first socket component having a first predetermined number of sockets; a second socket component having a second predetermined number of sockets Holes; and a third socket element having the first predetermined number of sockets; thereby, if the first type of package is tested, the packages are installed in the first socket element and the second socket On a part of the component, if the second type of package is tested, the packages are mounted on the entire first socket component and the third socket component, so as to test a variety of packages with a single load board. Brief illustration of these and various features and advantages of the present invention will be better understood with reference to the following detailed description in conjunction with the accompanying drawings, of which: Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back first) (Fill in this page again.) The first diagram shows a load-bearing board with a socket for testing a plurality of shrinkable double-row packages (SDIP) according to the present invention. The second diagram shows a test for a plurality of four-sided flat packages (QFP) according to the present invention. Load plate with jack; Figure A shows the state of the jumper wire used in each load board of the first and second pictures; and 494521 A7 B7 i. Description of the invention (3) Figure B shows along D A detailed description of a preferred embodiment of a cross-sectional view taken along the line D 'will be described in detail with reference to the accompanying drawings. The first figure shows a socketed load board for testing a plurality of shrunk double-row packages (SDIP) according to the present invention. Referring to the first figure, the first jack element 10 includes a first predetermined number of
(請先閱讀背面之注意事項再填寫本頁) '條 ~ &即18個形成於負載板左邊之插孔，而第二插孔元件 有第二預定數目之插孔，即15個位於其右邊之插孔。 第二插孔元件胃形成之第三插孔元g 30具有該第 一預定數目之插孔备加18個插孔。 /馨。’ 從第一插孔元件10與第二插孔頂部開始之15 個插孔被用以測試具30個接腳之36 Mp。 第二圖顯示根據本發明用以測試複數個四面扁平包裝 (QFP)之具插孔負載板。 如第二圖中所示，第四插孔元件40被形成以具有第四 預定數目之插孔，即20個插孔，第五插孔元件50被形成 以具有第五預定數目之插孔，即26個插孔。 經濟部中央標準局員工消費合作社印製 該第四插孔元件40係用以測試具20個接腳之20 QFP，而該第五插孔元件50係用以測試具24個接腳之24 QFP。 第一圖與第二圖之負載板間之區別如下所述。 如前所述，第一圖與第二圖之負載板係分別用以測試 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 494521 A7 _ _B7____ 五、發明説明（4 ) SDIP與QFP。對第一圖之負載板而言，第一插孔元件1〇 同爲不同型式之封裝測試所用，而在第二圖中’無插孔元 件供同爲不同型式之封裝測試所用。然而，第二圖中所示 插孔構造之技術槪念類似於第二圖之插孔構造者。 第三A圖顯示所用跳接線之狀態，而第三B圖顯示沿 D-D’線所取之截面圖。 請參閱第三A與第三B圖，有三個供應電壓VDD施加 所至之VDD插孔，以及三個接地電壓GND施加所至之GND 插孔。其上裝設有測試接腳之測試通道形成於VDD插孔與 GND插孔間。 轉到第三B圖，供應電壓VDD施加所至之VDD線以 及接地電壓GND施加所至之GND線分別形成於不同層 上。因此，該測試通道可藉由短路A-C連接至該接地電壓 GND。 該具發明性之多封裝測試負載板可不需其它負載板而 測試不同型式之封裝。而且，藉由跳接線，該具發明性之 負載板可對彼此型式相似但接腳之使用彼此不同之封裝進 行測試。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 因此，應了解者爲本發明並不限於此處所揭之所思及 可執行本發明之最佳模式之特殊實施例，除了如附申請專 例範圍中所定義者外，本發明並不限於說明書中所述之特 定實施例。 5 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐）(Please read the precautions on the back before filling out this page) 'Article ~ & that is, 18 jacks formed on the left side of the load board, and the second jack component has a second predetermined number of jacks, that is, 15 Right jack. The third jack element g30 formed by the second jack element stomach has the first predetermined number of jacks plus 18 jacks. / 馨。 / Xin. The 15 jacks starting from the top of the first jack element 10 and the second jack are used to test 36 Mp of 30 pins. The second figure shows a socketed load board for testing a plurality of quad flat packaging (QFP) according to the present invention. As shown in the second figure, the fourth jack element 40 is formed to have a fourth predetermined number of jacks, that is, 20 jacks, and the fifth jack element 50 is formed to have a fifth predetermined number of jacks, That is, 26 jacks. The fourth jack component 40 printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is used to test 20 QFP with 20 pins, and the fifth jack component 50 is used to test 24 QFP with 24 pins . The differences between the first and second load plates are described below. As mentioned above, the load plates of the first and second pictures are used to test the paper size. The Chinese national standard (CNS) A4 specification (210X297 mm) is applicable. 494521 A7 _ _B7____ 5. Description of the invention (4) SDIP and QFP. For the load board in the first figure, the first jack component 10 is also used for different types of packaging testing, while in the second figure, the 'no jack component' is used for the same type of packaging testing. However, the technical concept of the jack structure shown in the second figure is similar to that of the jack structure shown in the second figure. The third diagram A shows the state of the jumper used, and the third diagram B shows a cross section taken along the line D-D '. Referring to the third A and third B diagrams, there are three VDD jacks to which the supply voltage VDD is applied, and three GND jacks to which the ground voltage GND is applied. A test channel provided with a test pin is formed between the VDD jack and the GND jack. Turning to the third diagram B, the VDD line to which the supply voltage VDD is applied and the GND line to which the ground voltage GND is applied are formed on different layers, respectively. Therefore, the test channel can be connected to the ground voltage GND by shorting A-C. The inventive multi-package test load board can test different types of packages without other load boards. Moreover, by means of jumpers, the inventive load board can be tested on packages that are similar in type to each other but use different pins. Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) Therefore, it should be understood that the present invention is not limited to what is disclosed here and the best mode for implementing the invention The special embodiments are not limited to the specific embodiments described in the specification, except as defined in the scope of the attached application. 5 This paper size applies to China National Standard (CNS) A4 (210X 297mm)