494409 A7 _____B7__ r 1 1 -- _ 五、發明說明（/ ) 本發明之背景 本發明之領域 本發明有關於用於半導體記憶裝置的自復新振盪器， 而特別的是，有關於自復新振盪器，其能夠藉由感測由於 漏電流所引起的記憶體記憶胞資料之遺失，以及藉由控制 復新的週期，而將在待機模式下的功率消耗最小化。 因此’根據本發明的自復新振盪器能夠應用於實現自 復新操作的所有半導體記憶裝置。 背景技術之說明 一般而言，”自復新”意味著動態的隨機存取記憶體 DRAM本身具有一個預定的週期，並且執行自復新的操作， 藉以在待機模式下保持儲存於記憶體記憶胞中的資料。 隨著晶片密度因DRAM製造技術的發展而增加，已經 發展出了高積體的DRAMs，諸如256Mb的DRAM以及1Gb 的DRAM。所以，DRAM的位元數目增加，因而導致在復 新操作期間中的功率消耗急遽地增大。此乃是由於：儘管 記憶胞的數目增加，然而組成其記憶胞的記憶胞電容器之 電容量並無修改或降低。因此，假使DRAM的積體層級增 加了四倍，則在復新操作期間中的功率消耗同樣也會增加 將近四倍。 復新功率消耗的增加起因於DRAM積體程度的增加， 乃是在半導體技術的發展領域中的其中一個主要問題。特 別是在設有記憶胞的系統中，諸如在筆記型個人電腦中， 待機模式下的功率消耗對記憶胞的使用時間，會產生相當 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) · .線· 494409 % A7 ______ B7__ 五、發明說明CV ) 地影響。 在傳統的技術中，一種具有預定週期的振盪器用來執 行自復新的模式，並且根據所預定的週期來執行其復新的 操作。在此，由於在DRAM記憶胞中的資料保持時間很容 易受到溫度的影響，而在局於常溫一個預定的層級下，根 據DRAM記憶胞中的資料保持時間，來決定所預定的週 期，其中的資料保持時間雖然在常溫或低溫下維持數秒之 久，然而在高溫下則單單只是維持將近0.1秒之久。 所以，在高溫下，其自復新週期乃是藉由相當短的資 料保持時間來決定的，因而會變得較短。此意味著經常性 地執行其復新操作。因此，可能會增加功率的消耗。 然而，相當受到自復新功率消耗影響的筆記型PC，通 常在常溫下使用。因此，傳統根據高溫的資料保持時間來 決定復新週期的自復新振盪器具有一種缺點：不必要地增 加了在待機模式下的功率消耗。 本發明之槪要 所以，本發明的目的乃是藉由控制其自復新週期能夠 隨著溫度而改變，以及藉由避免經常性地執行不必要的自 復新週期，藉以提供一種能夠將待機模式下的功率消耗最 小化之自復新振盪器。 爲了實現本發明以上所說明的目的，而設有一種自復 新振盪器，其包含：一個控制信號的產生機構，其機構感 測所輸入的信號之電位變化，並且，根據一個致能信號當 變導體記憶裝置進入自復新的模式時致能，產生一個具有 5 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱^ — " (請先閱讀背面之注意事項再填寫本頁) # -t-rOT . •線 494409 A7 ♦ ' Γ______Β7___ 五、發明說明（^ ) f靖先閱讀背面之注意事項再填寫本頁) 預定脈波寬度的寫入操作之控制信號；一個記憶胞丨奠_ $ 構，其機構回授寫入操作的控制信號、執行資料的寫 作、並且根據溫度的變化而將輸出端的電位放電；^ & 個比較機構，根據致能信號而有所選擇地將其機構致#， 其機構比較第一輸入信號以及第二輸入信號，並且將 後的輸出信號輸出至控制信號產生機構的第一輸入端，g 中的第一輸入信號爲記憶胞模擬機構的輸出信號，而第二 輸入信號則是一個參考的電位。 此外，根據本發明的自復新振盪器可以進一步地包含 一個波形控制機構，其機構連接到控制信號產生機構的一 個輸出端、根據致能信號有所選擇地將其機構致能、藉由 控制輸入信號的脈波寬度來控制輸出信號的波形、並且改 變復新的週期。 附圖之簡略說明 藉由參照附圖，將會更爲了解本發明，而僅只是經由 闡述來提供其附圖，因而其並不限制本發明，其中： 圖1爲一個方塊圖，根據本發明，闡述自復新振盪器 的整個架構； 圖2爲一個詳細的電路圖，闡述一個如圖1所示的記 憶胞模擬器； 圖3爲一個詳細的電路圖，闡述一個如圖1所示的比 較器； 圖4爲一個詳細的電路圖，闡述一個如圖1所示的控 制信號產生器； 6 .本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 494409 一 A7 _____B7_ 五、發明說明（if ) 圖5爲圖4的操作時序圖； I丨丨——#.! (請先閱讀背面之注意事項再填寫本頁) 圖6爲一個詳細的電路圖，闡述一個如圖4所示的信 號變化感測單元之實施例； 圖7爲圖6的操作時序圖； 圖8爲一個詳細的電路圖，闡述一個如圖4所示的延 遲記憶胞之實施例； 圖9爲一個詳細的電路圖，闡述一個如圖1所示的波 形振盪器； 圖10爲圖9的操作時序圖；以及 圖11顯示根據本發明的自復新振盪器之模擬結果。 較佳實施例之細節說明 藉由參照附圖，將詳細地說明根據本發明的較佳實施 例之自復新振盪器。 線· 圖1爲一個方塊圖，闡述根據本發明的自復新振盪器 之整個架構。如同其中所示的，其自復新振盪器包含：一 個控制信號產生器14,其感測從之前的比較器12所輸入 的信號(det)之變化，並且在自復新模式開始之時，根據一 個將操作致能的操作控制信號(en)，而產生一個具有預定脈 波寬度的寫入操作之控制信號(wi〇 ; —個記憶胞模擬器10， 其回授寫入操作的控制信號(wr)、執行資料的寫入操作、 並且根據溫度的變化，將輸出端(stg)的電位放電；一個比 較器12 ’根據控制信號產生器14的操作控制信號(en)，有 所選擇地將之致能，其比較器比較第一輸入信號以及第二 輸入信號’並且將比較後的輸出信號(det)輸入至控制信號 7 本紙張尺度適用中國國家標準（CNS)A4規格（21G X 297公爱) ---- 494409 A7 ------- -B7_ 五、發明說明（^) 產生器14的第一輸入端，其中的第一輸入信號爲記憶胞模 擬器10的輸出信號(stg)，而第二輸入信號則是在預定的電 位位準下由外部所提供的一個參考電位Vref;以及一個波 形控制器16 ’其連接到控制信號產生器14的輸出端、根 據操作控制信號(en)有所選擇地將其致能、藉由控制輸出信 號(det)的脈波寬度來控制輸出信號的波形、並且改變復新 的週期。 圖2、3、4和9爲分別闡述記憶胞模擬器10、比較器 12、控制信號產生器14、以及波形控制器16的詳細電路圖。 此時參照其附圖，將說明根據本發明的自復新振盪器。 如圖2所示的記憶胞模擬器1〇包含：一個記憶胞模擬 單元21，感測由於漏電流所引起的記憶胞資料之遺失；以 及一個資料寫入單元23,其有關於記憶胞模擬單元21的 資料遺失之感測行爲，在來自控制信號產生器14的輸出信 號(wr)之控制下，藉由對輸出端(stg)電位的放電作用，執行 資料之寫入操作。 記憶胞模擬.單元21包含複數個的N通道MOS電晶體 MN11〜MNln，它們的源極連接到一個位元線預先充電電壓 Vblp的施加端，其Vblp施加端保持在電源電壓Vdd以及 接地電壓Vcc之間的一個預定電壓位準，並且將它們的閘 極共同接地，而複數個的N通道MOS電晶體MN11〜MNln 則是以並聯的形式連接；以及複數個的記憶胞電容器C11-Cln，其並聯連接於節點N1以及接地之間，而節點N1則 是共同連接於多數個N通道MOS電晶體MN11〜MNln的汲 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) · -線 494409 A7 ________B7____ 五、發明說明（t ) 極與接地之間。 (請先閱讀背面之注意事項再填寫本頁) 此外，資料寫入單元23包含：電源供應裝置MP21、 MP22，其根據從控制信號產生器14所產生的寫入操作控 制信號(wr)，有所選擇地供應電源電壓Vdd以及位元線預 先充電電壓Vblp ;以及複數個的N通道MOS電晶體 MN21〜MN2n，其並聯連接於電源供應裝置MP21、MP22的 共源極端與記憶胞模擬單元21的輸出節點N1之間，並且 分別地連接它們的閘極’藉以接收寫入操作的控制信號 (wr)。在此，一個P通道的MOS電晶體用來充當其電源供 應裝置。如圖2所示的記憶胞模擬單元21則是一個當DRAM 記憶胞處於待機模式狀態時的電路架構。 •線 此外，記憶胞模擬器1〇使用經由記憶胞模擬單元21 之輸出節點N1所輸出的信號(stg)，來充當之後的比較器12 之第一輸入信號。所以’由於將用於DRAM記憶胞的記憶 胞電容器之容量當作很小，大約爲25fF，而將複數個的記 憶胞電容器C11〜Cln以及複數個的N通道MOS電晶體 MN11〜MNln並聯連接，藉以避免誤操作的發生。 此外，資料寫入單元23對寫入操作的控制信號(wr)之 高態脈波有所反應、將電源電壓Vdd供給輸出節點N1、並 且執行相同於將資料寫入DRAM記憶胞的操作。更爲詳細 地，當寫入操作的控制信號(wr)爲低態時，則連接到位元 線預先充電電壓Vblp應用端的P通道MOS電晶體MP22便 會導通，藉以將位元線預先充電電壓Vblp供給複數個並聯 連接的N通道MOS電晶體MN21〜MN2n之共汲極端。相反 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 494409 A7 __B7 五、發明說明（q ) (請先閱讀背面之注意事項再填寫本頁) 地，假使寫入操作的控制丨目號(WI*)爲局恕、’則連接到電源 電壓Vdd應用端的P通道MOS電晶體MP1導通’藉以將 電源電壓Vdd供給多數個並聯連接的N通道MOS電晶體 MN21〜MN2n之共汲極端。 然而，複數個的N通道M〇S電晶體MN21〜MN2n只有 當寫入操作的控制信號(w〇爲高態（電位超過’Vdd+Vt’)時才 導通。所以，電源電壓傳輸至輸出節點N1，並因此以電源 電壓Vdd對輸出信號(stg)充電。 雖然組成記憶胞模擬單元21的複數個N通道MOS電 晶體MN11〜MNln之共閘極端接地，然而次臨界電流仍存 在而流經於MOS電晶體，並且由於接面而產生少許的漏電 流，等等諸如此類。週邊的溫度與處理顯著地影響其漏電 流。 藉由上述的操作而充電或放電的記憶胞模擬器10之輸 出信號(stg)，傳輸至比較器12，充當其第一輸入信號。 .線 圖3爲一個闡述比較器12的詳細電路圖。比較器12 包含一個致能單元31，根據自復新振盪器的操作控制信號 (en)之狀態，決定是否要致能一個操作；一個差動放大單元 35，受控於致能單元31的輸出端N1之電位，並且比較以 及放大記憶胞模擬器10的輸出信號(stg)與參考電位Vref; 一個分壓器33，連接於致能單元31以及差動放大單元35 之間，藉由電壓的相減而產生一個預定的電位Vdd-Vt，並 且將參考電位Vref傳輸，以充當差動放大單元35的第一 輸入信號；以及一個輸出驅動單元37，受控於致能單元31 10 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） 494409 B7___ 五、發明說明) 的輸出端N1之電位，並且緩衝以及輸出來自差動放大簞$ 35的輸出信號。 此時將說明如圖3所示的每個單元31、33、35、37之 詳細架構與操作。 首先，致能單元31包含：一個反相器131，其將整個 操作控制信號(en)反相；一個P通道MOS電晶體MP31，其 閘極連接到反相器131的輸出端，而其源極則連接到鼙源 電壓的應用端；一個電阻R31，其連接於P通道的MOS電 晶體MP31和節點N1之間，並且限制電流量I ;以及〜個 N通道的MOS電晶體MN31，其連接於節點N1和接地電顧 之間，而其汲極和閘極則共同連接到節點N1。 在致能單元31之中，當控制信號(en)爲高態時，則籍 由反相器131將其反相爲低態，並且將所反向的信號供給p 通道的MOS電晶體MP31的閘極。因此，經由電阻R31， 將電源供給輸出節點N1。所以，對比較器12的整個操作 致能。 然而，假使以低態位準供應控制信號(en)，則會藉由 反相器131，而將其反轉爲高態，並且供給P通道MOS電 晶體MP31的閘極。因此，p通道MOS電晶體MP31關斷， 並且電源無法供應。所以，.比較器12無法運作。494409 A7 _____B7__ r 1 1-_ V. Description of the invention (/) Field of the invention The present invention relates to a self-recovery oscillator for a semiconductor memory device, and in particular, to a self-recovery oscillator The oscillator can minimize the power consumption in the standby mode by sensing the loss of the memory cell data due to the leakage current, and by controlling the refresh cycle. Therefore, 'the resettable oscillator according to the present invention can be applied to all semiconductor memory devices which perform a reset operation. Description of the background Generally speaking, "self-renewal" means that the dynamic random access memory DRAM itself has a predetermined cycle and performs a self-renewal operation so as to keep the memory cells stored in the memory in the standby mode. Information. As the density of wafers has increased due to the development of DRAM manufacturing technology, highly integrated DRAMs have been developed, such as 256Mb DRAM and 1Gb DRAM. Therefore, the number of bits of the DRAM increases, resulting in a sharp increase in power consumption during the refresh operation. This is because despite the increase in the number of memory cells, the capacitance of the memory cell capacitors that make up its memory cell has not been modified or reduced. Therefore, if the DRAM integration level is quadrupled, the power consumption during the refresh operation will also be nearly quadrupled. The increase in refresh power consumption is due to the increase in the degree of DRAM integration, which is one of the major problems in the field of semiconductor technology development. Especially in a system equipped with a memory cell, such as in a notebook personal computer, the power consumption in standby mode on the use time of the memory cell will result in a paper size corresponding to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) · · Line · 494409% A7 ______ B7__ V. Description of the Invention CV). In the conventional technique, an oscillator having a predetermined period is used to perform a self-recovery mode, and its refresh operation is performed according to the predetermined period. Here, because the data retention time in the DRAM memory cell is easily affected by temperature, and at a predetermined level at room temperature, the predetermined period is determined according to the data retention time in the DRAM memory cell. Although the data retention time is maintained at room temperature or low temperature for a few seconds, it is maintained at a temperature of only 0.1 second for a long time. Therefore, at high temperatures, the self-recovery cycle is determined by a relatively short data retention time, and therefore becomes shorter. This means that its refresh operations are performed frequently. Therefore, power consumption may increase. However, notebook PCs, which are quite affected by the power consumption of self-recovery, are usually used at room temperature. Therefore, the conventional self-recovery oscillator that determines the refresh cycle based on the high-temperature data retention time has a disadvantage: it unnecessarily increases the power consumption in the standby mode. The main purpose of the present invention is to control its self-recovery cycle to be able to change with temperature, and to prevent the unnecessary self-recovery cycle from being performed frequently, thereby providing a method that can stand by. The resettable oscillator minimizes power consumption in mode. In order to achieve the above-mentioned purpose of the present invention, a self-recovery oscillator is provided, which includes: a control signal generating mechanism that senses a potential change of an input signal, and, based on an enable signal, The variable-conductor memory device is enabled when it enters the self-recovery mode, and produces a paper with 5 paper sizes applicable to Chinese National Standard (CNS) A4 specifications (210 X 297 public love ^ — " (Please read the precautions on the back before (Fill this page) # -t-rOT. • Line 494409 A7 ♦ 'Γ ______ Β7 ___ V. Description of the Invention (^) f Jing first read the precautions on the back before filling this page) Control signal for the write operation of the predetermined pulse width; one Memory cell structure, its mechanism feedbacks the control signal of the write operation, performs the writing of the data, and discharges the potential of the output terminal according to the change in temperature; ^ & a comparison mechanism, which varies according to the enable signal The mechanism is selected to be #, its mechanism compares the first input signal and the second input signal, and outputs the output signal to the first input terminal of the control signal generating mechanism, g A first input signal the analog output signal of the memory cell means, and the second input signal is a reference potential. In addition, the self-recovery oscillator according to the present invention may further include a waveform control mechanism, the mechanism of which is connected to an output terminal of the control signal generating mechanism, selectively enables its mechanism according to the enable signal, and controls the The pulse width of the input signal controls the waveform of the output signal and changes the period of the refresh. Brief Description of the Drawings The invention will be better understood by referring to the drawings, and the drawings are provided only by way of illustration, so it does not limit the invention, in which: Figure 1 is a block diagram according to the invention Explain the entire architecture of the resettable oscillator; Figure 2 is a detailed circuit diagram illustrating a memory cell simulator shown in Figure 1; Figure 3 is a detailed circuit diagram illustrating a comparator shown in Figure 1 ; Figure 4 is a detailed circuit diagram illustrating a control signal generator as shown in Figure 1. 6. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 494409 A7 _____B7_ V. Invention Explanation (if) Figure 5 is the operation timing diagram of Figure 4; I 丨 丨 —— #.! (Please read the precautions on the back before filling out this page) Figure 6 is a detailed circuit diagram illustrating one as shown in Figure 4 7 is an operation timing diagram of FIG. 6; FIG. 8 is a detailed circuit diagram illustrating an embodiment of the delay memory cell shown in FIG. 4; and FIG. 9 is a detailed circuit diagram , Elaborate one A wave oscillator as shown in FIG. 1; FIG. 10 is an operation timing chart of FIG. 9; and FIG. 11 shows a simulation result of the resettable oscillator according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT By referring to the drawings, a resettable oscillator according to a preferred embodiment of the present invention will be described in detail. Line · Figure 1 is a block diagram illustrating the entire architecture of a resettable oscillator according to the present invention. As shown therein, the self-recovery oscillator includes: a control signal generator 14 that senses changes in the signal (det) input from the previous comparator 12, and at the beginning of the self-recovery mode, According to an operation control signal (en) that enables the operation, a control signal for a write operation with a predetermined pulse width is generated (wi0; a memory cell simulator 10, which feedbacks a control signal for the write operation) (wr), perform a data writing operation, and discharge the potential of the output terminal (stg) according to a change in temperature; a comparator 12 ′ selectively selects a control signal (en) according to an operation control signal generator 14 To enable it, its comparator compares the first input signal and the second input signal 'and inputs the compared output signal (det) to the control signal. 7 This paper size is applicable to China National Standard (CNS) A4 (21G X 297). (Gongai) ---- 494409 A7 ------- -B7_ V. Description of the invention (^) The first input terminal of the generator 14, where the first input signal is the output signal of the memory cell simulator 10 ( stg), and the second input signal is A reference potential Vref provided by the outside at the potential level of the device; and a waveform controller 16 'which is connected to the output terminal of the control signal generator 14 and selectively enables it according to the operation control signal (en), The waveform of the output signal is controlled by controlling the pulse width of the output signal (det), and the refresh period is changed. Figures 2, 3, 4 and 9 illustrate the memory cell simulator 10, comparator 12, and control signal generation, respectively. Detailed circuit diagrams of the controller 14, and the waveform controller 16. At this time, referring to the drawings, the self-recovery oscillator according to the present invention will be described. The memory cell simulator 10 shown in FIG. 2 includes: a memory cell simulation unit 21, sensing the loss of memory cell data due to leakage current; and a data writing unit 23, which has a sensing behavior of data loss of the memory cell simulation unit 21, in the output signal from the control signal generator 14 Under the control of (wr), the data writing operation is performed by discharging the potential at the output terminal (stg). Memory cell simulation. The unit 21 contains a plurality of N-channel MOS transistors MN11 ~ MNln, which are The source of is connected to an application terminal of a bit line precharge voltage Vblp, the application terminal of which Vblp is maintained at a predetermined voltage level between the power supply voltage Vdd and the ground voltage Vcc, and their gates are commonly grounded, and a plurality of N-channel MOS transistors MN11 ~ MNln are connected in parallel; and a plurality of memory cell capacitors C11-Cln are connected in parallel between node N1 and ground, and node N1 is commonly connected to a plurality of N-channel MOS transistor MN11 ~ MNln draw 8 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) · -line 494409 A7 ________B7____ 5 The invention description (t) between the pole and the ground. (Please read the precautions on the back before filling in this page.) In addition, the data writing unit 23 includes: power supply devices MP21 and MP22. According to the writing operation control signal (wr) generated from the control signal generator 14, there are The power supply voltage Vdd and the bit line precharge voltage Vblp are selected to be supplied; and a plurality of N-channel MOS transistors MN21 to MN2n are connected in parallel to the common source terminal of the power supply devices MP21 and MP22 and the memory cell simulation unit 21 The output nodes N1 and their gates are respectively connected to receive a control signal (wr) of a write operation. Here, a P-channel MOS transistor is used as its power supply device. The memory cell simulation unit 21 shown in FIG. 2 is a circuit structure when the DRAM memory cell is in a standby mode. • Line In addition, the memory cell simulator 10 uses a signal (stg) outputted through the output node N1 of the memory cell simulation unit 21 as the first input signal of the comparator 12 thereafter. So 'because the capacity of the memory cell capacitor used for the DRAM memory cell is considered to be small, about 25fF, and a plurality of memory cell capacitors C11 ~ Cln and a plurality of N-channel MOS transistors MN11 ~ MNln are connected in parallel, To avoid misoperation. In addition, the data writing unit 23 responds to the high-state pulse of the control signal (wr) of the writing operation, supplies the power supply voltage Vdd to the output node N1, and performs the same operation as writing data to the DRAM memory cell. In more detail, when the control signal (wr) of the write operation is low, the P-channel MOS transistor MP22 connected to the application line of the bit line precharge voltage Vblp is turned on, thereby precharging the bit line voltage Vblp. A common drain terminal of a plurality of N-channel MOS transistors MN21 to MN2n connected in parallel is provided. On the contrary, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 494409 A7 __B7 V. Description of the invention (q) (Please read the precautions on the back before filling this page) The control number (WI *) is forgiveness. 'The P-channel MOS transistor MP1 connected to the power supply voltage Vdd application terminal is turned on', so that the power supply voltage Vdd is supplied to a plurality of N-channel MOS transistors MN21 ~ MN2n connected in parallel. Take the extreme. However, the plurality of N-channel M0S transistors MN21 to MN2n are turned on only when the write control signal (w0 is high (the potential exceeds 'Vdd + Vt'). Therefore, the power supply voltage is transmitted to the output node N1, and therefore charges the output signal (stg) with the power supply voltage Vdd. Although the common gates of the plurality of N-channel MOS transistors MN11 to MNln constituting the memory cell simulation unit 21 are grounded, a subcritical current still exists and flows through MOS transistor, and a small leakage current due to the interface, etc. The surrounding temperature and processing significantly affect its leakage current. The output signal of the memory cell simulator 10 charged or discharged by the above operation ( stg), which is transmitted to the comparator 12 as its first input signal. Figure 3 is a detailed circuit diagram illustrating the comparator 12. The comparator 12 includes an enabling unit 31, which controls the signal according to the operation of the reset oscillator (en) status, decide whether to enable an operation; a differential amplifier unit 35 is controlled by the potential of the output terminal N1 of the enable unit 31, and compares and amplifies the memory cell simulator 10 The output signal (stg) and the reference potential Vref; a voltage divider 33 is connected between the enabling unit 31 and the differential amplifier unit 35, and a predetermined potential Vdd-Vt is generated by the voltage subtraction, and the reference The potential Vref is transmitted to serve as the first input signal of the differential amplifying unit 35; and an output driving unit 37, which is controlled by the enabling unit 31 10 This paper size applies to the Chinese National Standard (CNS) A4 specification (21〇X 297) Love) 494409 B7___ V. Description of the invention) The potential of the output terminal N1, and buffer and output the output signal from the differential amplifier 箪 $ 35. The detailed structure and operation of each unit 31, 33, 35, 37 shown in Fig. 3 will now be explained. First, the enabling unit 31 includes: an inverter 131 which inverts the entire operation control signal (en); a P-channel MOS transistor MP31 whose gate is connected to the output terminal of the inverter 131 and its source The pole is connected to the application terminal of the source voltage; a resistor R31 is connected between the P-channel MOS transistor MP31 and the node N1 and limits the current amount I; and ~ N-channel MOS transistor MN31, which is connected Between the node N1 and the grounding capacitor, its drain and gate are commonly connected to the node N1. In the enabling unit 31, when the control signal (en) is high, it is inverted to a low state by the inverter 131, and the inverted signal is supplied to the p-channel MOS transistor MP31. Gate. Therefore, power is supplied to the output node N1 via the resistor R31. Therefore, the entire operation of the comparator 12 is enabled. However, if the control signal (en) is supplied at a low state level, it will be inverted to a high state by the inverter 131 and supplied to the gate of the P-channel MOS transistor MP31. Therefore, the p-channel MOS transistor MP31 is turned off, and power cannot be supplied. Therefore, the comparator 12 cannot operate.
分壓器13包含：一個二極體型式的N通道MOS電晶 體MN32，串聯連接於電源vdd應用端和接地電壓之間； 以及一個N通道MOS電晶體MN33，其閘極連接到致能單 元31的輸出節點N1。參考電位Vref經由兩個N通道MOS 11 ϋ氏張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂： 線- 494409 A7 ___B7 ___ 五、發明說明（l ) (請先閱讀背面之注意事項再填寫本頁) 電晶體MN32、MN33的連接節點，供給差動放大單元33 的第一輸入端。在此，所提供的參考電壓Vref爲’Vdd-Vt’(N 通道MOS電晶體的臨界電位）。 此外，差動放大單元35包含：N通道MOS電晶體 MN34、MN35，連接它們的閘極，藉以接收由分壓器33的 操作所產生的參考電位Vref，並且接收來自記億胞模擬器 1〇的最後之輸出信號(stg);—個N通道MOS電晶體MN36， 其連接於兩個N通道MOS電晶體MN34、MN35的共源極 端與接地端之間，其閘極連接到致能單元31的輸出端N1， 並且控制差動放大單元35的操作致能行爲；以及一個P通 道MOS電晶體MP32、MP33，其具有電流鏡架構，而其電 流鏡架構則連接於電源電壓Vdd的應用端以及兩個N通道 MOS電晶體MN34、MN35的每個汲極之間。兩個P通道MOS 電晶體MP32、MP33的閘極共同連接到P和N通道電晶體 MP33、MN35的連接節點N4。 線 在比較以及放大兩個輸入信號(Vref)、（stg)之後，具有 電流鏡架構的差動放大單元35經由輸出節點N，輸出一個 因而產生的數値.，其中的輸出節點N則是P和N通道M〇S 電晶體MP32、MN34的連接節點。 輸出驅動單元37包含:·Ρ和N通道MOS電晶體MP34、 ΜΝ37,其串聯連接於電源Vdd的應用端和接地端Vss之間； 以及兩個串聯連接的反相器132、D3，其將輸出節點N5的 電位緩衝並且輸出至比較器12的最後輸出端(det)。輸出驅 動單元37根據差動放大單元35的輸出信號，來改變其最 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 494409 A7 __ B7 __----- 玉、發明說明（/ D ) 後的輸出端(det)。 圖4爲一個闡述控制信號產生器14的詳細電路圖，其 控制信號產生器14接收來自比較器12的輸出信號(det)與 整個的操作控制信號(en)、感測兩信號(det)、（en)的電位之 變化、並且產生一個具有預定脈波寬度（數十奈秒）的寫入 操作控制信號(wr)。現在將說明其詳細構成。 控制"is號產生窃14包含：第一和第二信號變化的感測 單元41、43，其接收兩個輸入信號(det)、（en)，並且感測它 們的電位之變化；一個NAND邏輯閘NAND41以及一個反 相器141，其二者串聯連接，接收來自第一和第二信號變化 的感測單元41、43的輸出信號(enb_p)、（detbjp)，並對這 兩個輸出信號從事NAND運算，且改變節點N1的電位； 一個閂鎖單元49，其具有由兩個NAND邏輯閘NAND42、 NAND43所組成的RS正反器架構、連接到反相器141的輸 出端、並且閂鎖來自反相器141的輸出信號；一個反相器 142，其將閂鎖單元49的輸出端電位反相、並且將所反相 的輸出信號傳輸至節點N2 ; —個延遲單元45，其將節點N2 的電位延遲一段預定的時間、並且將所延遲的信號回授至 閂鎖單元49的NAND邏輯聞NAND43之第一輸入端；以及 一個位準轉換單元47，其連接到節點N2、並且致使從接地 電位Vss變化至電源電位Vdd的節點N2之信號，轉換成 爲從接地電位變化至大於電源電位一個預定位準的電位 Vpp之局態脈波寫入操作控制信號(wr)。 位準轉換單元47包含：P通道MOS電晶體MP41、 13 (請先閱讀背面之注意事項再填寫本頁) 訂- -線_ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 494409 A7 _____. _B7_ 五、發明說明（丨1 ) (請先閱讀背面之注意事項再填寫本頁) MP42，其連接它們所具有的源極，藉以接收大於電源電壓 一個預定電位的電位Vpp，並且它們所具有的閘極以交叉 連結的架構，連接到汲極；一個N通道MOS電晶體MN41， 其連接於P通道MOS電晶體MP41與節點N2之間，並且 連接它們所具有的閘極，藉以接收電源電壓Vdd ;以及一 個N通道MOS電晶體MN42，其連接於P通道MOS電晶 體MP42與將節點N2電位反相之反相器143的輸出端之間， 而其所具有的閘極與N通道MOS電晶體MN41則共同連接 到電源電壓Vdd的施加端。位準轉換單元47將寫入操作的 控制信號(wr)輸出至P和N通道MOS電晶體MP42、MN42。 圖6和8爲分別闡述於圖4中所敘述的信號變化感測 單元41、43與延遲單元45實施例之電路圖。 -線_ 如圖6所示的，信號變化感測單元41、43包含：奇數 個的反相器(在圖6中有七個反相器161〜167)，其串聯連接， 並且接收、反相、以及延遲一個信號(in) ; P通道MOS電 晶體型式的電容器C21、C22、C23，它們所具有的閘極連 接到以串聯連接的反相器161〜167中第2ιι反相器的輸出端， 而它們的汲極與源極則共同連接到電源電壓Vdd的施加 端；N通道MOS電晶體型式的電容器Cn、C12、C13，它 們所具有的閘極連接到以串聯連接的反相器161〜167中第 2n-l反相器的輸出端，而它們的汲極與源極則共同連接到 接地電壓Vss的應用端；以及一個NAND邏輯閘NAND61， 其對第一輸入信號與第二輸入信號從事NAND運算，並且 將其輸出(outb)，其中的第一輸入信號乃是輸入信號（in)， 14 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 494409 A7 _____ B7______ 五、發明說明（ 而第二輸入信號則是以串聯連接的反相器161〜167輸出端N1 之信號。 圖7爲一個操作的時序圖，顯示如圖6中所示的信號 變化感測單元41、43之操作。當輸入信號(in)的電位如圖7(a) 所示的，從低態轉爲高態時，節點N1的電位則如圖7(b)所 示的，在一段預定的延遲Dtl之後，從高態轉爲低態。如 圖7(c)所示的，藉由NAND邏輯閘利用節點N1之電位作爲 第一輸入信號而行NAND運算，其輸出信號(outb)便會輸出 一個具有與延遲寬度Dtl —樣大的脈波寬度之低態信號。 圖8顯示如圖4所示的延遲單元45之實施例。延遲單 元45包含多數個的反相器181〜188，其乃是串聯連接的延 遲單元；多數個的電阻器R1〜R5,其爲連接於反相器181〜188 之間的延遲單元；多數個的P通道M0S電晶體型式之電容 器C11〜C15，其連接於電源電壓Vdd的應用端與電阻器和 反相器間的每個節點之間；多數個的N通道M0S電晶體型 式之電容器C21〜C25，其連接於電阻器和反相器間的每個 節點與接地Vss之間，藉以執行簡單的時間延遲操作。 ‘Vdd+2Vt’的電位用來充當如圖4所示的位準轉換單元 47之高態電壓Vpp。 圖5爲如圖4所示的·控制信號產生器14之操作時序 圖。當信號(en)、（det)如圖5(a)和5(b)所示的，從低態的Vss 轉爲高態的Vdd時，則信號變化感測單元41、43的輸出信 號(enbj)、（det_p)便產生一個低態信號，藉以如圖5(d)所 示的，將低態的脈波信號輸出至反相器141的輸出節點N1。 15 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂· · 線· 494409 A7 --- -B7 ___ 五、發明說明（1^) (請先閱讀背面之注意事項再填寫本頁) 然後，從節點N2經由如圖4所示的延遲單元45和閂鎖單 元49，將如圖5(e)所示的具有預定脈波寬度之低態脈波信 號輸出。此後，則如圖5(c)所示的，最後的信號(wr)藉由位 準轉換單元47，輸出高態電位的Vpp信號，其中的高態電 位VPP信號則具有相同於如圖5(e)所示的節點N2信號之脈 波寬度。 .線 圖9爲一個闡述如圖1所示的波形控制器16之詳細電 路圖，而圖10則顯示其中每一個單元的波形之操作。如圖 9所示的波形控制器16包含：第一和第二傳輸閘MT9卜 MT92 ’其根據輸入資料(in)的狀態有所選擇地導通；一個 NAND邏輯閘NAND91，其從事操作致能信號(en)與來自第 一傳輸閘MT91的輸出信號之NAND運算，並且將其輸出 至第二傳輸閘MT2的輸入端；一個反相器192，其將來自 NAND邏輯閘NAND91的輸出信號回授至第一傳輸閘“丁91 的輸出節點；兩個反相器193、194，它們的輸入和輸出端 彼此相連接，藉以將第二傳輸閘MT92的輸出端電位，閂 鎖並且輸出至一個輸出端(out);以及一個反相器195，將輸 出端(out)的電位反相，並且將所反相的信號回授至第一傳 輸閛MT91的輸出端。 其因而建構的波形控制器16爲一種用來移除來自比較 器12的輸出信號(det)高態脈波寬度與低態脈波寬度的任務 率差之電路。如同在圖10的操作時序圖中所描述的，於輸 入信號(in)的下降邊緣上，改變輸出信號的電位，藉以產生 具有輸入信號(in)雨倍週期的輸出信號(out)。所以，最後的 16 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 494409 A7 --—------- B7 _____ 五、發明說明（|+) 輸出信號(osc)之頻率變爲來自比較器12輸出信號(det)的頻 率之一半。 圖11描述根據本發明的自復新振盪器之模擬結果。當 記憶胞模擬器10的輸出信號(stg)如圖11(b)所示的，放電 至一個預定的電位位準Vdd-Vt時，則藉由比較器12的參 考電位Vref与Vdd-Vt來感測其行爲，藉以輸出如圖ll(c)所 示的信號(det);而其中的記憶胞模擬器1〇乃是感測由於各 種的原因，諸如電壓位準與處理所產生的漏電流，因而引 起的記憶胞資料之遺失。 接收信號(det)的控制信號產生器14如圖11(d)所示的， 輸出具有預定脈波寬度的高態電位信號Vpp#Vdd+2Vt，來 充當最後的輸出信號(wr)。 回授來自控制信號產生器14的高態電位位準寫入操作 控制信號(wr)之記憶胞模擬器10，在控制信號產生器14的 輸出信號(wr)產生高態電位Vdd的脈波期間中，充電至電 源電位Vdd的位準。記憶胞模擬器10的充電輸出信號(stg) 輸入其後的比較器12。比較器12輸出一個低態的輸出信 號(det)，直到來自記憶胞模擬器10的輸出信號(stg)放電至 低於預定的電壓位準Vdd-Vt。 此後，假使來自記憶胞模擬器10的輸出信號(stg)由於 各種的原因，諸如溫度，而持續地放電，並且因此而降至 Vdd-Vt的位準時，則重複上述的操作，藉以對輸出信號(stg) 重新充電。 具有如圖11(e)所示的波形之最後輸出信號(osc)，變爲 17 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐) ~ (請先閱讀背面之注意事項再填寫本頁) · -線' 494409 A7 _____B7______ 五、發明說明（1^) ——：—：-------—— (請先閱讀背面之注意事項再填寫本頁) 具有如圖11(c)所示的比較器12輸出信號(det)的兩倍週期。 其信號波形意味著，根據溫度、所施加的電壓、以及處理， 藉由比較器12將輸出信號(det)改變爲不同的時序，藉以產 生具有不同週期的復新控制信號(osc)之操作。 如同先前所討論的，根據本發明的自復新振盪器感測 由於漏電流所引起的記憶胞資料之遺失，並且根據記憶胞 的狀態來控制其復新週期，藉以顯著地降低在待機模式期 間的功率消耗。 因此，以記億胞操作的系統之記億胞使用時間，能夠 有效地延長。 線- 因爲可以數種的型式實施本發明而不悖離其精神及主 要特徵，則應該也要了解的是，以上所說明的實施例並不 受限於之前所說明的任何細節，除非另外所詳加指定的， 否則應該廣泛地將其建構於如同在所附的申請專利範圍中 的精神和觀點之內，因而所有的變體和修改皆會是在申請 專利範圍的集合及領域之內，或者藉由所附的申請專利範 圍’因而打算包括如此的集合及領域之等效物。 18 本中國國家標準(CNS)A4規格（210 x 297公釐）The voltage divider 13 includes: a diode-type N-channel MOS transistor MN32, which is connected in series between the power supply vdd application terminal and the ground voltage; and an N-channel MOS transistor MN33, whose gate is connected to the enabling unit 31 Output node N1. The reference potential Vref is via two N-channel MOS 11 scales. Applicable to China National Standard (CNS) A4 (210 X 297 mm) (please read the precautions on the back before filling this page). Order: Line-494409 A7 ___B7 ___ V. Description of the invention (l) (Please read the notes on the back before filling this page) The connection nodes of the transistors MN32 and MN33 are provided to the first input terminal of the differential amplifier unit 33. Here, the reference voltage Vref provided is 'Vdd-Vt' (the critical potential of the N-channel MOS transistor). In addition, the differential amplifying unit 35 includes: N-channel MOS transistors MN34 and MN35, connected to their gates, so as to receive the reference potential Vref generated by the operation of the voltage divider 33, and receive the reference potential Vref from the recorder simulator. The last output signal (stg); an N-channel MOS transistor MN36, which is connected between the common source terminal of the two N-channel MOS transistors MN34, MN35 and the ground, and its gate is connected to the enabling unit 31 Output terminal N1, and controls the operation enabling behavior of the differential amplification unit 35; and a P-channel MOS transistor MP32, MP33, which has a current mirror structure, and the current mirror structure is connected to the application terminal of the power supply voltage Vdd and Between each drain of two N-channel MOS transistors MN34, MN35. The gates of the two P-channel MOS transistors MP32 and MP33 are commonly connected to the connection node N4 of the P and N-channel transistors MP33 and MN35. After the line compares and amplifies the two input signals (Vref) and (stg), the differential amplifier unit 35 with a current mirror structure outputs an resulting number 经由 through the output node N, where the output node N is P Connection node with N-channel MOS transistor MP32, MN34. The output driving unit 37 includes: · P and N-channel MOS transistors MP34 and MN37, which are connected in series between the application terminal of the power supply Vdd and the ground terminal Vss; and two inverters 132 and D3 connected in series, which output The potential of the node N5 is buffered and output to the last output terminal (det) of the comparator 12. The output driving unit 37 changes the maximum 12 paper sizes according to the output signal of the differential amplifying unit 35. The Chinese paper standard (CNS) A4 (210 X 297 mm) is applicable. 494409 A7 __ B7 __----- Jade, The output terminal (det) after the invention description (/ D). FIG. 4 is a detailed circuit diagram illustrating the control signal generator 14. The control signal generator 14 receives the output signal (det) from the comparator 12 and the entire operation control signal (en), the sensing two signals (det), ( en), and generates a write operation control signal (wr) with a predetermined pulse width (tens of nanoseconds). The detailed constitution will now be described. Control "is" generation 14 includes: first and second signal change sensing units 41, 43, which receive two input signals (det), (en), and sense changes in their potentials; one NAND Logic gate NAND41 and an inverter 141, which are connected in series, receive the output signals (enb_p), (detbjp) from the sensing units 41, 43 of the first and second signal changes, and apply the two output signals Engage in NAND operation, and change the potential of node N1; a latch unit 49, which has an RS flip-flop architecture composed of two NAND logic gates NAND42, NAND43, is connected to the output terminal of the inverter 141, and latches An output signal from the inverter 141; an inverter 142 that inverts the potential of the output terminal of the latch unit 49 and transmits the inverted output signal to the node N2; a delay unit 45 that converts the node The potential of N2 is delayed for a predetermined time and the delayed signal is fed back to the first input terminal of the NAND logic NAND43 of the latch unit 49; and a level conversion unit 47 is connected to the node N2 and causes the slave Ground potential Vss Of the power supply potential Vdd to the node N2 of the signal to be converted into changes from the ground potential to the power supply potential is greater than a predetermined level of potential Vpp pulse state of the Board write operation control signal (wr). Level conversion unit 47 includes: P-channel MOS transistor MP41, 13 (Please read the precautions on the back before filling this page) Order--Line _ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Love) 494409 A7 _____. _B7_ 5. Description of the invention (丨 1) (Please read the precautions on the back before filling out this page) MP42, which is connected to the source they have, so as to receive a potential Vpp greater than the power supply voltage by a predetermined potential And their gates are connected to the drain in a cross-connected structure; an N-channel MOS transistor MN41 is connected between the P-channel MOS transistor MP41 and node N2, and the gates they have are connected To receive the power supply voltage Vdd; and an N-channel MOS transistor MN42, which is connected between the P-channel MOS transistor MP42 and the output of the inverter 143 which inverts the potential of the node N2, and the gate The N-channel MOS transistor MN41 is commonly connected to the application terminal of the power supply voltage Vdd. The level conversion unit 47 outputs a control signal (wr) of a write operation to the P and N-channel MOS transistors MP42, MN42. 6 and 8 are circuit diagrams illustrating embodiments of the signal change sensing units 41, 43 and the delay unit 45 described in FIG. 4, respectively. -Line_ As shown in FIG. 6, the signal change sensing units 41 and 43 include: an odd number of inverters (seven inverters 161 to 167 in FIG. 6), which are connected in series, and receive and invert And delay one signal (in); P-channel MOS transistor-type capacitors C21, C22, and C23 have gates connected to the output of the 2nd inverter of inverters 161 to 167 connected in series. Terminals, and their drain and source are connected to the supply terminal of the supply voltage Vdd in common; N-channel MOS transistor-type capacitors Cn, C12, and C13 have gates connected to inverters connected in series The output terminal of the 2n-1th inverter in 161 ~ 167, and their drain and source are connected to the application terminal of the ground voltage Vss in common; and a NAND logic gate NAND61, which is used for the first input signal and the second The input signal is engaged in NAND operation, and it is output (outb). The first input signal is the input signal (in). 14 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 494409 A7. _____ B7______ 5. Description of the invention (and the second input The signal is the signal from the output terminal N1 of the inverters 161 to 167 connected in series. Figure 7 is a timing diagram of the operation, showing the operation of the signal change sensing units 41 and 43 as shown in Figure 6. When the signal is input The potential of (in) is shown in Figure 7 (a). When the potential is changed from low to high, the potential of node N1 is shown in Figure 7 (b). After a predetermined delay Dtl, the potential is changed from high. Turn to the low state. As shown in Figure 7 (c), the NAND logic gate uses the potential of node N1 as the first input signal to perform NAND operation, and its output signal (outb) will output a signal with a delay width Dtl -A low-state signal with a large pulse width. Fig. 8 shows an embodiment of the delay unit 45 shown in Fig. 4. The delay unit 45 includes a plurality of inverters 181 to 188, which are delay units connected in series. ; Most of the resistors R1 to R5 are delay units connected between the inverters 181 to 188; most of the P-channel M0S transistor type capacitors C11 to C15 are connected to the application terminal of the power supply voltage Vdd To each node between the resistor and inverter; most N-channel M0S transistor types The capacitors C21 ~ C25 are connected between each node between the resistor and the inverter and the ground Vss to perform a simple time delay operation. The potential of 'Vdd + 2Vt' is used as shown in Figure 4 High-state voltage Vpp of the level conversion unit 47. Fig. 5 is an operation timing chart of the control signal generator 14 shown in Fig. 4. When the signals (en) and (det) are shown in Figs. 5 (a) and 5 (b) As shown in the figure, when the low state Vss is changed to the high state Vdd, the output signals (enbj) and (det_p) of the signal change sensing units 41 and 43 generate a low state signal, as shown in FIG. 5 (d ), A low-state pulse wave signal is output to the output node N1 of the inverter 141. 15 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Order · · Line · 494409 A7 --- -B7 ___ V. Description of the invention (1 ^) (Please read the precautions on the back before filling in this page) Then, from node N2 via delay unit 45 and latch unit 49 as shown in Fig. 4, there will be reservations as shown in Fig. 5 (e). Low state pulse wave signal output of pulse wave width. Thereafter, as shown in FIG. 5 (c), the final signal (wr) outputs a high-state potential Vpp signal through the level conversion unit 47, where the high-state potential VPP signal is the same as that shown in FIG. 5 ( e) Pulse width of node N2 signal shown. Fig. 9 is a detailed circuit diagram illustrating the waveform controller 16 shown in Fig. 1, and Fig. 10 shows the operation of the waveform of each unit. The waveform controller 16 shown in FIG. 9 includes: the first and second transmission gates MT9 and MT92 'which are selectively turned on according to the state of the input data (in); a NAND logic gate NAND91, which is engaged in operation enable signals (en) NAND operation with the output signal from the first transmission gate MT91, and output it to the input of the second transmission gate MT2; an inverter 192, which feedbacks the output signal from the NAND logic gate NAND91 to The output node of the first transmission gate Ding 91; two inverters 193, 194 whose input and output terminals are connected to each other, thereby latching and outputting the potential of the output terminal of the second transmission gate MT92 to one output terminal and an inverter 195 which inverts the potential of the output terminal (out) and feeds the inverted signal back to the output terminal of the first transmission 閛 MT91. The waveform controller 16 thus constructed is A circuit for removing the task rate difference between the high-state pulse width and the low-state pulse width of the output signal (det) from the comparator 12. As described in the operation timing diagram of FIG. 10, the input signal ( in) on the falling edge, changing the output To produce an output signal (out) with an input signal (in) rain cycle. Therefore, the last 16 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 public love) 494409 A7- --------- B7 _____ 5. Explanation of the invention (| +) The frequency of the output signal (osc) becomes one and a half of the frequency of the output signal (det) from the comparator 12. Figure 11 depicts the self-recovery according to the present invention. The simulation result of the new oscillator. When the output signal (stg) of the memory cell simulator 10 is discharged to a predetermined potential level Vdd-Vt as shown in FIG. 11 (b), the reference of the comparator 12 is used. The potentials Vref and Vdd-Vt are used to sense their behavior, so as to output the signal (det) as shown in Figure 11 (c); and the memory cell simulator 10 is used for sensing for various reasons, such as the voltage level And the leakage current generated by the processing, thereby causing the loss of memory cell data. As shown in FIG. 11 (d), the control signal generator 14 of the received signal (det) outputs a high-state potential signal Vpp having a predetermined pulse width. # Vdd + 2Vt, to serve as the final output signal (wr). Feedback from the control signal generator 14 The memory cell simulator 10 in which the high-state potential level writes the operation control signal (wr) is charged to the bit of the power-source potential Vdd during the pulse period in which the output signal (wr) of the control signal generator 14 generates the high-state potential Vdd. The charging output signal (stg) of the memory cell simulator 10 is input to the following comparator 12. The comparator 12 outputs a low-state output signal (det) until the output signal (stg) from the memory cell simulator 10 is discharged. To below a predetermined voltage level Vdd-Vt. After that, if the output signal (stg) from the memory cell simulator 10 is continuously discharged due to various reasons, such as temperature, and thus drops to the level of Vdd-Vt, the above-mentioned operation is repeated to thereby output the signal. (stg) Recharge. The final output signal (osc) with the waveform as shown in Figure 11 (e) has become 17 paper sizes. Applicable to China National Standard (CNS) A4 (21 × 297 mm) ~ (Please read the note on the back first (Please fill in this page for matters) · -line '494409 A7 _____B7______ 5. Description of the invention (1 ^) ——: —: ——————— (Please read the notes on the back before filling this page) The comparator 12 shown in FIG. 11 (c) has a double period of the output signal (det). The signal waveform means that the output signal (det) is changed to different timing by the comparator 12 according to the temperature, the applied voltage, and the processing, thereby generating the operation of the restoration control signal (osc) with different periods. As previously discussed, the self-recovery oscillator according to the present invention senses the loss of memory cell data due to leakage current, and controls its refresh cycle according to the state of the memory cell, thereby significantly reducing the period during standby mode Power consumption. Therefore, the operating time of a system that operates with a memory cell can be effectively extended. Line-Because the invention can be implemented in several forms without departing from its spirit and main features, it should also be understood that the embodiments described above are not limited to any details previously described, unless otherwise stated Specify it in detail, otherwise it should be broadly constructed within the spirit and perspective as in the scope of the attached patent application, so all variants and modifications will be within the collection and field of patent application scope, Or with the scope of the attached patent application ', it is therefore intended to include such collections and equivalents in the field. 18 Chinese National Standard (CNS) A4 (210 x 297 mm)