TW492168B - Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size - Google Patents

Abstract

Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size. A lower die has keep out areas on its top surface. The keep out areas correspond to two adjacent edges of the lower die. The lower die has bond pads within the keep out areas. An upper die is stacked on the top surface of the lower die such that the bond pads within the keep out areas of the lower die are exposed to accept wire bonds. The configuration of the keep out areas next to adjacent edges of the lower die thus provides flexibility in the design of stacked chip packages because the size of the upper die is not limited by the bond pad configuration of the lower die.

Description

V. Description of the invention "Generally related to integrated circuits, and especially related to the sealing of integrated circuits, sub-devices such as cell phones and notebook computers, are packaged on two printed circuit boards (PCBs). Integrated electronics: Heart ;: a; (or wafer) in the-substrate. The next day grain and the substrate are sealed in a plastic board (PαΓ) and then mounted to another substrate such as-printing The circuit is an on-chip circuit package, which can contain two or less. Can be used? Electronic devices using multi-chip modules $ b ,,, s ,, # Because multi-chip modules usually have several separate Product n: Road-grain 'installed in a horizontally adjacent manner in a single two product two 1 ^ tprtn't f ^ Vf, i-^ ^ Very expensive pottery f. Moreover, the multi-chip module substrate is usually It is made up of ί1 or printed circuit board material before manufacturing. The net product can be: value = # 彳 t, in providing a molding technology with the smallest covering surface and body connection substrate parts, without the need to add expensive Internal power: 1 Λ A configuration of an integrated circuit package, which attempts to reduce the integrated ίΠ :: = Ι Product, said. Integrated circuit sealed magic ... Including h?,: Ie package 'scsp) See Nong u including the integrated integrated circuit die. These piles 492168 V. Description of the invention (2) " 一 " " 'The appropriate chip type package 1 〇1 is formed by stacking several sets of integrated circuit die on a long substrate, wiring, sealing the integrated circuit die, and then cutting the substrate and the sealing package, Separate each stacked chip-type package 1 0. The stomach substrate 110 includes wire-finger fingers 丨 2 connected to the top surface of the substrate 丨 丨 114. Wire-finger fingers 112 are the substrate 11 The conductive area on 〇 provides the integrated circuit die to the position of the substrate 11 〇. The through hole (v 丨 as) 1 i 6 is a conductive inner connection that extends through the substrate 1 1 〇 will conduct conductive micro-traces 1 1 4 Electrically connected to the conductive pad on the bottom surface of the substrate 110. 7. An example of a substrate is a printed circuit board (PCB). The substrate 11 can be other materials such as FR4, BT, and TAB. Tape material, ceramic, sapphire (s0s), or more like OLGA, etc. Stacked chip type package (scsp) 1 shown in Figure 1 〇l is connected to a circuit board (not shown in the figure) with solder balls 1 1 8 which is placed on the (conductive) pad 11 7 on the bottom surface of the substrate 110. Other types of integrated circuit packages may include leads opposite to The die within the package extends laterally to connect to an external circuit board. The figure also shows the first die 120 mounted on the substrate 110. The second die 130 is mounted on the upper surface of the first die 220. Use an adhesive such as epoxy to mount the die. After the first die 120 and the second die 130 were attacked, they were wire-bonded to the substrate. The first die 1 2 0 has a wire bonding pad 122 near its upper surface, and the second die 13 () has a wire bonding pad 32 near its edge. The wire bonding wire 2 4 connects the wire bonding pad 122 of the first die 1 2 0 to the substrate 110, and the bonding wire 134 connects the wire bonding pad 1 2 of the second die 13 2 to the base 1 1 0.

Page 6 492168 V. Description of the invention (3) Figure 2 shows a top view of the circuit package 1 00 after wiring and before sealing. The first die 120 is mounted on a substrate π. The wire bonding pad 1 2 2 is connected to the wire bonding finger connector 112 by the connecting wire 1 2 4. The second die 130 is mounted on the first die 120. The wire bonding pads 1 2 2 on the second die 1 3 0 are connected to the wire bonding finger joints 11 2 by the connecting wires 1 3 4. The area in the center of the first grain 1 2 0 limits the size of the second grain 1 3 0 because the second grain 1 3 0 cannot cover the wire bonding pad 12 2 ° of the first grain 1 2 There are even more problems for the die with wire pads. FIG. 3A shows an integrated circuit die configuration 2000, which includes a first die 220 and a second die 230 stacked on the first die 220. The first and second crystal particles 2 2 0 and 2 3 0 are stacked on the substrate 2 10. The substrate 2 1 0 has wire-finger finger joints 2 1 2 adjacent to two pairs of edges, as shown in FIG. 2. The wire finger joint 2 1 2 corresponds to the wire pad of the first and second die. The first die 2 2 0 has a wire pad 2 22 adjacent to two pairs of edges, rather than adjacent to four sides. The first die 1 2 0 is shown in FIG. 2. In order for the second crystal grains 230 to be stacked on the first crystal grains 220, the size of the second crystal grains 23 0 must fit between the wire pads 2 2 2 of the first crystal grains 2 2 0. Therefore, the size of the second die 230 is limited by the arrangement of the wire pads of the first die 220. FIG. 3B shows an integrated circuit die configuration 200, which includes a first die 220 'and a second die 230' stacked on the first die 220 '. The first and first dies 220 'and 230' are rectangular and have wire pads 22 2 'and 232, respectively, near the opposite sides of the short sides. The grain configuration of 200 allows two grains of the same size to be stacked while still exposing the wire pads of the lower grains, but the rectangular grains must be stacked with their respective axes perpendicular. with

492168 5. In the description of the invention (4), the second die 2 3 0 ′ must be narrow enough to fit between the first wire bonding pad 2 2 2 ′. Therefore, the size of the second die 2 3 0 'is summarized in the invention. In a specific embodiment, a device includes a lower die having an upper adjacent prohibited region on the upper surface. These two adjacent sides of the underlying grain are prohibited. The lower die further encloses an unwired edge region. The two adjacent prohibited areas of an upper die stacked on the lower die are exposed to accept wire bonding. Other features and benefits of the invention will be apparent from the accompanying drawings and detailed description. Simple description of the phoenix style The present invention is illustrated by the examples in the attached drawings and is therefore limited. In the attached drawings: FIG. 1 is a side cross-sectional view of an integrated circuit package that is as skilled as the art. FIG. 2 It is the prior art package of FIG. 1 from the direction of line 2-2 in FIG. 1 # FIG. 3A is a top view of a stacked die configuration of a prior art; 4 is a integrated circuit with a pile of two sides that are closest to each other. The type of electric circuit is as follows. Figure 5 is a perspective view of the specific physical embodiment of FIG. 4; Fig. 6 is an enlarged, partial cross-section of the stack / second of Fig. 4; Fig. 7 is another stack: ::: flattened on a substrate * A cross-sectional view of an embodiment of a body circuit die mounted on A substrate grain 2 2 0 is restricted. The surface and the two stop regions are close to at least one, so that the next, rather than the top view; adjacent to the phase diagram, the specific 492168

FIG. 8 is a plan view of a specific embodiment of a die; FIG. 9 is a specific implementation diagram of another stacked integrated circuit die; and FIG. 10 is a side view of the stacked integrated circuit die of FIG. 9. Detailed description of the invention The following description includes the upper, lower, first, second, etc. · It is for illustration purposes only and is not intended to limit the invention. A specific embodiment of one of these devices can be manufactured, used, or shipped in a number of locations or formats. ° way is

A specific embodiment of an integrated circuit (IC) package that includes at least two integrated circuit dies, providing the flexibility of the integrated circuit (1C) package design. "Different with a unique wire pad configuration allows the stacked die size to be smaller. Big 2 factory, select. The grains of the specific embodiments described herein are stacked in a vertical manner. The bonding pads of the integrated circuit die of the specific embodiments are adjacent to adjacent edges of the integrated circuit die. When an upper crystal grain is stacked on the lower crystal grain, the upper crystal grain is slightly displaced from the lower crystal grain, so that the wire bonding pad of the lower crystal grain is exposed. This underlying die-exposed wire bonding pad can be easily attached to the substrate using conventional wire bonding techniques.

In a specific embodiment, the device includes a lower die having a forbidden region on its upper surface. These prohibited areas have only two adjacent edges close to the underlying grains. The lower die has wire bonding pads only in the prohibited area. The device also includes an upper die stacked on the upper surface of the lower die. The upper grains are located at the lower grains to avoid the forbidden area of the lower grains. In one embodiment, the upper grains are shifted diagonally with respect to the lower grains.

492168 V. Description of the invention (6) Avoid the prohibited area. The next thick Yue private from 4 # 4 目 in, 4, exposure of the wire pad to accept wire. The distribution of the wire bonding pads is as follows: + stacked on the integrated circuit package

The possible configuration of the actual Feng Sang shown in HfB®1 is small. A larger die can be used in a special size package, and the die 1 of ^ reduces the total volume of the package or the surface of the package. With almost unlimited mixing and matching capabilities, we allow the combination of granule groups to perform new production functions. Examples of integrated circuit packages that can perform such stacked die configurations are flash memory packages, which include static random access memory (SRAM) die, or die combinations of different memory technologies. It can also provide strange memory die combinations. For example, a 6 megabyte random access memory die is stacked on top of a 32 megabyte random access memory die to provide a 48 megabyte random access memory. Encapsulation. Also, the integrated circuit die with the logic circuit can be combined with the memory die in the same package /. The increased flexibility provided by the combination of grains provided by the wire bonding pads, as well as the aa grain heap configuration described here, can provide many types of electronic transactions without the current limitations associated with incompatible grain sizes . FIG. 4 shows a specific embodiment of an integrated circuit package 300, which includes stacked integrated circuit dies. The lower die 3 2 0 includes a wire pad 3 2 2 adjacent to the first side 326 and the second side 328. The first side 326 is adjacent to the second side 328. The first and second sides 3 2 6 and 3 2 8 are considered to be threaded edges, because they are used as a threaded line 322 ′ for threading the lower layer 3 2 0 to a substrate (not shown), which is located close to the first edge 326 and

Page 10 492168 V. Description of Invention (7) Second side 328. The upper grains 3 3 0 are stacked on the lower grains 3 2 0 as shown in FIG. 4. A preferred method is to attach the upper grains 3 3 0 to the upper surface 3 2 1 of the lower grains 3 2 0 with an adhesive 3 0 3 such as epoxy resin. The upper die 3 3 0 is stacked or positioned on the lower die 32 0, so that the wire bonding pad 32 2 is exposed and can be used for wire bonding. As shown in FIG. 4, the upper grain 3 3 0 is diagonally shifted or shifted relative to the lower grain 3 2 0. In this shifted stacking configuration, the upper grains 3 3 0 can be the same size or larger than the lower grains 3 2 0 and can be stacked above the lower grains 32 0 without covering the lower grains 32 0. The wire pads 32 2 may overlap. The upper die 3 3 0 includes a wire bonding pad 3 3 2. As shown in FIG. 4, the bonding pads 332 of the upper die 3 3 0 are scattered near the first edge 336 and the second edge 338 of the upper die 3 0. The first side 336 and the second side 338 of the upper die 330 are adjacent to each other. The wire bonding pad 332 is on the upper surface 331 and is close to the first side 336 and the second side 338. The first side 326 and the second side 328 of the lower die 320, and the first side 336 and the second side 338 'of the upper die 330 may be referred to as wire-bonding sides. As shown in FIG. $, The wired edges of the lower die 320 are adjacent to each other, and the wired edges of the upper die 320 are adjacent to each other. Preferably, the upper grains 3 3 0 are positioned on the lower grains 3 2 0 so that the wire edges 3 3 6 and 3 3 8 respectively face the wire edges 32 6 and 328 of the lower grains 32 0. Because the wiring pad 32 2 is distributed close to the adjacent sides of the lower layer grains 32 0, the size of the upper layer grains 3 3 0 can be set to cover almost all the upper surface 321 of the lower layer particles 320, except for the wire pads 322. The surrounding area, such as two $ for further explanation. However, it is not always necessary except for prohibited areas.

Page 11 492168 V. Description of the invention (8) One ^-^ grains 33 0 should cover almost all the upper surfaces of the lower grains 32 0. The upper grains may be at least horizontally larger than the lower grains 3 2 0. . As shown in FIG. 4 ', a part of the upper-layer grain 3 3 0 extends beyond the lower-layer grain 3 2 0, along the second side 32 3 and the fourth side 325. The third side 32 3 and the fourth side 325 may be called non-hits, if ′ because the lower die 3 2 0 does not include the wire bonding pads that are to be approached or adjacent to the third and fourth sides 323 and 325. Figure 8 J integrated circuit package can also include a second upper die (not shown). A second upper grain can be stacked on the upper surface of the upper grain 33 0 in a similar manner to the upper grain 33 0 stacked on the lower grain 32 0. I must consider space and heat Concerns, of course, being able to envy this way = ί tf number should be unlimited. At the same time, the encapsulation f of other particles: U is incorporated into the crystal u including the displacement stack as shown in Fig. 4. For example, a heat slug can be provided in the package to remove Heat removed. … And spider -ΓMaterial = 5af! F body circuit package 3 °° sectional side view. Figure 5 shows 312 ^ ^ ^ ^ ^ ^ ^^ 〇〇 can include: use it. Or (PachUe) of the lead frame, such as-/ make a package including # a with a die paddle in order to be able to accommodate a stack of == four to command = ground to accommodate multiple The lower layer of the stacked body is placed on the substrate 3Π. The upper layer 33 has 492168 V. Description of the invention (9) It is displaced and stacked on the lower layer 3 2 0. Uses such as epoxy resin The adhesive 3 0 3 attaches the lower layer grains 320 to the substrate 310, and also attaches the upper layer grains 3 3 0 to the lower layer grains 3 2 0. The deviation position of the upper layer grains 3 3 0 is exposed to the lower layer The bonding pad 3 2 2 on the die 3 2 0 enables the lower die 3 2 0 to be electrically connected to the substrate 31 0 via the bonding wire 3 24. The bonding wire 324 connects the bonding pad 322 to the bonding finger joint 3 1 2 Fig. 5a shows a prohibited area 329. The prohibited area is defined as the distance A between the second edge 328 of the lower die 320 and the second edge 338 of the upper die 330. The prohibited zone is a monopoly upper die 3 3 0 is a parameter for positioning on the lower die 3 2 0. Sufficient clearance must be provided to allow the wire driver 307 to attach a conductive connection wire to the wire pad 322 on the lower die 320. At the same time, the prohibited area 329 It is determined by the tolerances related to the installation of the upper die 3 3 0 to the lower die 3 2 0. There is also 'When the upper die is pressed on the lower die 3 20, the adhesive 30 3 can be displayed. The bleed out 304 exceeds the edge 338 of the upper die 330. The forbidden area 32 9 (size A) therefore takes into account the vent holes 3 04, tolerances, and the width and size of the die attachment or wire punch 3 0 7 Figure 6 shows the integrated circuit package 3 0 with the lower layer die 3 2 0 and the upper layer die 3 3 0 in a previously described displacement manner. The stacked lower layer die 320 and the upper layer die 3 3 0. It is mounted on the substrate 31. The substrate 3 has wire-finger finger joints 3 1 2 arranged adjacent to the substrate 3 1 0. As shown in FIG. 6, the lower die 320 has a wire-pad 322. On its upper surface 321. The wire pad 322 is located close to or adjacent to the first side 326 and the second side 328 ° side 3 26 and 32 8 each other O The edges 326 and 328 may be referred to as a wire-side 'and the third side 323 and the non-wire side. Such a fourth side edge of the wire 325

Page 13 4 ^ 2108 V. Description of the invention (10) 326 and 328 have thread pads 322, and the product # ± Ms. Li is awkward, and the other is not the thread edges 323 and 325 > 3 2 2, namely, each ab d a μ δ "on the right side ... It is recognized that some of them are not connected with the threaded finger joint wire of the substrate 310. Upper = Qstop zone 3 27 and 32 9, It only corresponds to the two adjacent edges 32 6 and 32 8 of the lower die 320. The lower die 320 has wire bonding pads 322 only in the forbidden areas m and 3 29. The upper die 3 0 0 is stacked on the lower die. On the upper surface 321 of 32 °, to avoid the forbidden areas 32 7 and 329, the bonding pads 322 of the lower layer grains “ο” are exposed to receive the bonding (not shown) for bonding to the bonding fingers 3 1 2 for use. When the lower layer die 320 is mounted on the substrate 31o, the wire-finger finger joint 3 1 2 on the substrate 31o corresponds to the wire pad 3 2 2 of the lower layer die 3 2 0. In a corresponding manner, it means that the lined edges 3 2 6 and 3 2 8 are positioned adjacent to each other along the adjacent sides 3 11 and 3 1 3 of the substrate 3 1 0 and the lined finger joints 3 12. These wire-finger finger joints 3 1 2 correspond in position to the wire edges 3 2 6 and 3 2 8 and wire pads 3 2 2. I should note that the lower grain 3 2 0 and the upper grain 3 330 may be part of a stack of more than two grains. For example, the lower layer grains 3 2 0 and the upper layer grains 3 3 0 may be mounted on another grain (not shown) instead of the base material 3 0 as shown in FIG. 6. The lower die 3 2 0 can be mounted on another die having a wire pad configuration similar to the lower die 3 2 0. Alternatively, the lower die 3 2 0 can be mounted on the back of the other die, that is, the die has the side opposite to the wire pad. At the same time, another layer of grains can also be mounted on the upper layer grains 330 in FIG. 6 in a manner similar to that of the upper layer grains 330 on the lower layer grains 320. Or yes, another layer of grains can also be similar to the second grains 1 3 0 of FIGS. 1 and 2

Page 14 492168 V. Description of the invention (11) --- Mounted on the upper die 330. There are integrated circuit die on the close-to-adjacent sides of the substrate, which provides great flexibility in designing integrated circuit packages, because these die can be stacked without considering the relative die size. The forbidden areas 3 2 7 and 3 2 9 can also be referred to as wire edge areas. The lower layer grain 3 2 0 玎 has at least one non-wired edge region (not shown), and when the upper layer ′ = 33 ° is stacked on the lower layer grain 320, the upper layer grain 330 is covered. The non-wired edges & are opposite to the wired edge regions of the lower die 3 2 0 respectively. In a 'present embodiment', when stacked on the lower die 320, the size of the upper die 330 can be determined to cover at least one non-wired edge region of the lower die 320. The specific embodiment shown in FIG. 6 illustrates a lower layer die 320 having two adjacent non-wired edge regions (not shown) and covered by an upper layer die 300. However, the upper grains do not have to cover any non-wired edge areas. These forbidden areas are arranged close to the adjacent sides of the lower die, thus providing great flexibility in designing a stacked chip package, because the size of the upper die is not limited by the configuration of the wire pads of the lower die, as shown in Figure 1- The restricted package case shown in Figure 3. FIG. 7 shows another embodiment of the integrated circuit package 400, which includes stacked dies as described above. In the specific embodiment shown in FIG. 7, the substrate 4 i 0 is rectangular and includes a space for accommodating two grain groups 4 4 0. The substrate 4 10 has wire finger joints 41 2 'similar to the specific embodiment previously described. The wire finger joints 41 2 are arranged such that the lower grains 4 20 and the upper grains 4 20 with wire pads 4 2 2 and 432 are respectively turned, so that the wire bonding pads of the grain group 44 are corresponding to the wire finger joints 4 1 2 . The substrate 41 can accommodate a plurality of crystal particle groups. Alternatively, the substrate 410 may be another integrated circuit die, and

Page 15 492168 V. Description of the invention (12) The wire finger joint 4 1 2 may be a wire pad. The adjacent edge wire bonding arrangement described herein can be used together with a conventional package 'as shown in FIG. 8 by placing wire bonding pads on three groups of die. FIG. 8 shows a specific embodiment of an integrated circuit package 500, in which the lower crystal grain 5 2 0 has a wire bonding pad 5 2 2 near two adjacent sides, and a wire bonding pad 5 2 2 ′ near a third side. The trace 5 0 9 connects the wire bonding pad 5 2 2 to the wire bonding pad 5 2 2 ′ on the adjacent side. Therefore, the grain 5 2 0 can accept an upper grain 5 3 0 in a displacement manner, as described previously in the specific embodiment in FIGS. 4-6. Alternatively, the lower-layer grain 5 2 0 can accept an upper-layer grain 530, whose size is close to that of the bonding pads 5 2 2 and the bonding pads 5 2 2 near the opposite sides of the lower-layer grain 5 2 0. Wait forbidden interval. 9 and 10 show another specific embodiment of the integrated circuit package 600, in which an upper die 6 3 0 is stacked on a lower die 6 2 0 and the specific embodiment described in FIGS. 4 to 6 similar. The lower die 620 has a wire bonding pad 622 near two adjacent sides, and the upper die 6 30 has a wire bonding pad 6 3 2 near two adjacent sides. The upper die 630 is stacked on the lower die 6 20, so that the wire bonding pad 622 is exposed as a wire bonding finger joint (not shown) on the substrate 6 10 connecting wire. Referring to FIG. 9, the lower grains 6 2 0 and the upper grains 6 3 0 are shifted and stacked in a manner as shown in FIG. 10, and are further stacked on a lower grain 6 65. The bottom layer crystals 65 0 are mounted on the substrate 61 0 with their upper surface 651 facing the substrate 610. The bottom die 650 has a wire bonding pad 652 on the upper surface 651. The bonding pad 65 2 provides an electrical connection between the bottom die 650 and the substrate 610. The electrical connection is provided by a wire 6 24 through a hole 61 6. Line 6 24 is connected to the bottom die 650

Page 16 492168 V. Description of the invention (13) The wire bonding pads 6 5 2 and the base material 6 1 0 wire bonding finger joints 6 1 2. In the foregoing characteristic description, the present invention is described by referring to specific exemplary embodiments. However, there can be different modifications and changes without losing the spirit and scope of the patent application attached to the present invention. The specifications and drawings are for illustration purposes only, and are not intended to limit the invention.

Page 17 492168 Case number 89127377 Amendment Simple illustration

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Claims (1)

492168 Case No. 89127377 Amendment 6. The scope of the patent application area 1 and the stop surface prohibition table, the upper area, the stop particle stop crystal adjoining layer next one or two: the surface of the surface including the surface, the surface of the lower surface is crystallized and on the road surface And electricity meter, there is a spacer on the body with one phase and one material base-at least including the step next to the grain layer next to the adjacent phase, and the grain edge layer near the edge of the line near the non-exposed The upper neighbor of the grain stop crystal forbidden layer in the area is called Yumedong, and the two grains and the Ba are layered on the upper surface of the first grain and the lower layer of the aa layer is below the surface of the adjacent stack surface. The term of the electric volume of the grains in the crystal layer If you want to use the special line, please accept the application. 丄 2 The open side line is called brAr 巳 and the library is a good one. Please go to the application cover to cover the three-grain layer under the grain layer. Its grain crystal circuit electric body. Check the item i of the plot area 3, and hit the 7th non-surrounding range. 7¾ 71 r For each phase, please apply for two electrical layers with 1 electrical layer. If you store the line below, the line member will be called :: The neighboring linehead If you want to cover the two fingers, please cover the line and apply it. If there is a ^; there is a step in the grain one-the grain crystal road is next to the grain line with a grainy finger line. The material should be. In the padding line, hit the grains below the counter-layers, and base them on the bottom of the grain-layers on the surface.-: Bread-containing tables, grains and road surface meters. One kind has a 6-stroke close-up, only the area is restricted, and the area is restricted to the upper surface of the grain. The surface and the surface are adjacent to each other. The grain layer of the crystal base layer must be above the grain layer and the superposition line O: \ 67 \ 67876.ptc Page 19 492168 Amendment No. 89127377 6. Scope of patent application The lower surface is adjacent to the upper surface of the lower grains to avoid the prohibited area, and the wire bonding pads of the lower grains are exposed to accept wire bonding. 7. The integrated circuit die according to item 6 of the patent application, wherein the upper die includes two adjacent wire edges and each of the two adjacent wire edges has a wire pad, and the upper die is arranged toward the lower die. Direction so that the wire edge of the upper layer grains faces the forbidden area of the lower layer grains. 8. The integrated circuit die according to item 6 of the patent application scope, wherein the upper layer grains have a wire bonding pad close to at least two adjacent edges facing the lower layer grain prohibition area. 9 • For the integrated circuit die of item 7 in the scope of the patent application, except that the upper layer grains cover almost all the upper surfaces of the lower layer grains except the prohibited area. 10. The integrated circuit crystal grains according to item 9 of the scope of patent application, wherein the upper crystal grains are larger than the lower crystal grains in at least one horizontal direction, and a part of the upper crystal grains extend outwardly through the lower crystal grains. 1 1. The integrated circuit die according to item 6 of the patent application scope, further comprising a substrate, and when the lower die is mounted on the substrate, a wire finger having a wire finger joint corresponding to the lower die is provided. 1 2. — A kind of integrated circuit die, including: The lower die has a first side adjacent to a second side, a third side opposite to the first side, and a fourth side opposite to the second side. The lower die has an upper surface and The lower surface, the upper surface is relatively spaced apart from a substrate, and further has at least one first wire bonding pad adjacent to the first side and at least one second wire bonding pad adjacent to the second side. There are no wire pads adjacent to it on all sides; and O: \ 67 \ 67876.ptc Page 20 492168 _ Case No. 89127377 Amended 7/22 / 2012_ Sixth, the scope of patent application is an upper grain, with a first side adjacent to a second side, a A third side opposite to the first side and a fourth side opposite to the second side, the upper grains are stacked on the lower grains such that the lower surface of one of the upper grains is adjacent to the upper surface of the lower grains and the upper layer The first, second, first, second, third, and fourth sides of the grains have the same directions as the first, second, third, and fourth sides of the lower grains, respectively. The upper grains are located at Above the lower die, the individual first side is shifted to expose the first wire pad to receive the wire, and the second individual side is shifted to expose the second wire pad to receive the wire. 1 3 · As for the integrated circuit die of item 12 in the scope of the patent application, the third and fourth sides of the upper die cover individual third and fourth sides of the lower die. 1 4. According to the integrated circuit die of item 13 in the scope of the patent application, the third and fourth sides of the upper die extend outwardly from the individual third and fourth sides of the lower die. 1 5. According to the integrated circuit die of item 12 of the patent application scope, further comprising a base material with wire finger joints, when the lower die is mounted on the base material, the wire finger joints are mounted on The substrate is lined with wires corresponding to the underlying crystal grains. 16. According to the integrated circuit die of item 12 in the scope of patent application, the lower die has an upper side and the first and second wire bonding pads are on the upper side, and the middle and upper die are in addition to the first Cover almost all upper sides with a second wire pad outside. Hidden 1 7. According to the integrated circuit die of item 16 of the patent application scope, the upper die is larger than the lower die in at least one horizontal direction, and a part of the upper die extends outwards through the lower die. O: \ 67 \ 67876.ptc Page 21