490848 經濟部中央標準局員工消費合作社印製 26 5 8twfl .doc/006 A7 _B7 五、發明説明（f ) 本發明是有關於一種動態隨機存取記憶體（Dynaimc Random Access Memory，DRAM)電容器的製造方法，且特 別是有關於一種將半球形矽晶粒（Hermsphencal Grained Polysilicon，HSG-Si)應用於兩個並列之柱狀電容器的製造 方法。 在DRAM中，一般利用半導體基底上陣列的電容充電 (Charge)或放電（Discharge)的型態來儲存資料。通常， 以放電形式的電容代表邏輯1，而充電形式的電容代表邏輯 〇之方式，將二進位（Bmary)之單一位元（Bit)資料儲存 在單一電容。記憶體中存取與讀寫動作，係以轉移場效電 晶體（Transfer FET )完成電荷儲存電容與位元線（Bit Line ) 之耦接，且藉由耦接後電荷之移轉而執行。其中位元線與 轉移FET中之源極區（Source)連接，而電荷儲存電容則 與轉移FET中之汲極區（Drain)相連接。字元線信號則供 給轉移FET之閘極，並經由轉移FET使電荷儲存電容之儲 存電極（Storage Electrode)與位元線連接’藉此於電荷儲 存電容與位元線之間，發生電荷轉移的現象。 因此，電容器中電荷的儲存量由記憶電容器之電極表 面積、電極隔離的可靠度，以及在電荷儲存電容器間電容 介電質的介電常數（Dielectric Constant)而決定。然而， 爲了增加資料儲存量，因此積體電路記憶體的儲存密度亦 有逐漸增加的傾向。如果電容器所儲存的電荷愈多’則讀 取放大器在讀取資料時受雜訊的影響將可大大的降低，更 可減少再補充（Refresh)的頻率。而在電荷儲存電容上开多 ---------------ir------- (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X 297公釐） 83. 3. 10,000 經濟部中央標準局員工消費合作社印製 490848 2 6 5 8twfl .doc/006 A7 _B7 _ 五、發明説明（2) 成半球形矽晶粒爲近來增進dram電容値頗常使用的方 法。 第1圖係繪示習知將半球形矽晶粒應用於堆疊形 (Stack)電容器的剖面圖。在半導體基底1〇〇的主動區上， 形成場效電晶體，並以場氧化區101做絕緣隔離’其中場 效電晶體包括閘極結構1〇4與源極/汲極區1〇2、103。然 後於基底1〇〇上形成一絕緣層1〇5,並於此絕緣層105形成 接觸窗開口，並暴露出下方欲與電容器做電性耦接的源極 /汲極區102,然後依序沈積導電物質和形成半球形矽晶 粒，再定義出下電極的區域，以形成圖示之導電層106和 半球形矽晶粒層1〇7。或在導電層1〇6的側邊亦形成半球形 矽晶粒，以增加電容器的表面積（未於圖示中繪出）°最 後再形成介電層108和上電極109，以完成電容器的結構。 然而，如果在導電層106的側壁亦形成半球形矽晶粒’ 則易造成電容器介電層的遺漏電流（LeakaSe Current)變 大，以及崩潰電壓（Breakdown Voltage)變低等問題。但 是，若只有在導電層106上表面形成半球形矽晶粒層1〇7， 則電容器的有效面積不夠大，不足以應付電荷高儲存量的 趨勢，而且再補充時間（Refresh Time)較差。而且，當完 成上述之電容器的製程後，會造成電容器的區域與周邊電 路（PenpheryCnxuits)間存在著高度差，其高度差約相當 於電容器的高度，因此需進行化學機械硏磨製程做平坦 化，以利於後續的製程。 爲了解決堆疊形電容器之有效面積不足的問題，習知 4 本紙張尺度適用中國國家標準（CNS〉A4規格（210X297公釐） 83. 3. 10,000 ---------4^ 裝------訂—----- (請先閲讀背面之注意事項再填寫本頁) 490848 2658twfl .doc/006 A7 經濟部中央標準局員工消費合作社印製 五、發明説明（>) 解決的方法是利用柱狀電容器的結構以增加電容器的有效 面積。第2圖係繪示習知將半球形矽晶粒應用於柱狀 (Cylmder)電容器的剖面圖。其中第2圖中的部份結構、 材質與標號與第1圖相同，在此不多做說明，所形成的柱 狀下電極116結構如圖所示，然而於柱狀下電極Π6的側 壁沒有半球形矽晶粒，而且完成上述之電容器的製程後， 仍會造成電容器的區域與周邊電路間存在著高度差，因此 需進行化學機械硏磨製程做平坦化，以利於後續的製程。 因此本發明的主要目的，就是在提供一種柱狀電容器 的結構.，並充份地利用柱狀電容器的表面積，以增大電容 器的電荷儲存量，且使電容器的區域與周邊電路間幾乎沒 有高度差存在，因此不需平坦化的步驟即可進行後續的製 程，可降低製程的風險。 爲達成本發明之上述目的，本發明提供一種兩個並列 的柱狀DRAM電容器之製造方法，且將半球形矽晶粒應用 於並列的柱狀電容器之結構上。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖係繪示習知將半球形矽晶粒應用於堆疊形電容 器的剖面圖； 第2圖係繪示習知將半球形砂晶粒應用於柱狀電容器 的剖面圖； 5 ---------—------，tr------ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 83. 3.1〇,〇〇〇 經濟部中央標準局員工消費合作社印裝 490848 2658twfl.doc/006 A 7 __B7_ 五、發明説明（+ ) 第3A圖至第3E圖係顯示根據本發明一較佳實施例之 一種DRAM電容器的製造流程剖面圖；以及 第4圖係顯示根據本發明一較佳實施例之一種下電極 區域的罩幕俯視圖。 其中，各圖標號與構件名稱之關係如下： 100、 200 :半導體基底 101、 300 :場氧化區 102、 103、302、303 :源極 / 汲極區 104、304 :閘極結構 30.5 :場效電晶體 105' 311 :絕緣層 106、 314、322 :導電層 107、 317 :半球形砂晶粒層 108、 312、315、315a、321 :介電層 109 :上電極 116、3 1 8 :下電極 309 :厚度 310 :接觸窗開口 320,、320” ：開口 313 :下電極的區域 320 :要餽刻介電層315的區域 321 :覆蓋住介電層315的區域 實施例 第3A圖至第芬·lEJl所示，爲根據本發明一較佳實施 ---------^裝------訂------- (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 83. 3. 10,000 ^0848 ^0848 經濟部中央標準局員工消費合作社印裝 2658twfl.doc/006 A 7 _B7__ 五、發明説明（f ) 例之一種DRAM電容器的製造流程剖面圖。 首先請參照第3A圖，提供一半導體基底300，比如是 ?型矽基底，在其表面形成場效電晶體305。場效電晶體305 係形成於半導體基底300的主動區上，並比如以場氧化區 3〇1做絕緣隔離，或是淺溝渠隔離結構（S1TI)、以及其他 類似此結構者。其中場效電晶體305包括閘極結構304與 源極/汲極區302、303。然後於基底300上依序形成一絕 緣物質，比如氧化物；以及一介電材質，比如氮氧化矽 (Silicon-Oxy-Nitride，SiOxNy)。之後於此絕緣物質和介電 物質中形成接觸窗開口 310,並暴露出下方欲與雩容器做電 性耦接的源極/汲極區302,形成如圖所示之絕緣層311 和介電層312。其中介電層312可做爲後續蝕刻製程時的護 層，以避免後續的蝕刻製程會蝕刻到絕緣層Μΐϋ，因而 可確保絕緣層111344-的絕緣效果。 之後於整個半導體基底300的表面形成一層導電材 質，比如已摻雜的多晶矽，塡滿接觸窗開口 310，並與源極 /汲極區302接觸。之後進行微影蝕刻製程，以定義出下 電極的區域313,並在介電層312上方留下厚度309的導電 材質，形成圖示中之Τ型的導電層314。 然後於整個半導體基底300的表面形成一層介電層 315，其材質比如是氧化物，而其所沈積的的厚度端視所需 之電容大小而決定。 接著請參照第4圖，其繪示下電極區域313的罩幕俯 視圖。圖示之320區域，係爲要蝕刻介電層315的區域， 7 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） " 83. 3. 10,000^ ---------^ 裝------訂------- (請先閲讀背面之注意事項再填寫本頁) 490848 2658twfl.doc/〇〇6 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（G) - 其方法比如是乾餓刻，且以導電層川爲触刻終止層。圖 示之321的區域，係爲覆蓋住介電層315的區域。因此， 經触刻製程後，於下電極_域3n，形成如第3B圖，兩 個開口 320’，以及介電層315a。 接著請參照第3C圖，於介電層3l5a和導電層314的 表面形成一半球形矽晶粒層3Π，並使得開口 MO,形成開 口 320”。其方法比如以以札或以2^爲反應氣源，在介於 非晶取及多晶矽生成溫度之間利用低壓化學氣相沈積法形 成半球形矽晶粒層317。 接著請參照第3D圖，定義半球形砂晶粒層317，以去 除介電層315a上方之半球形矽晶粒層317，使形成半球形 矽晶粒層317a。其中半球形矽晶粒層317&與導電層314共 同形成DRAM電容器的下電極318。其方法比如先於整個 半導體基底300表面覆蓋一層旋塗式玻璃（Spin 〇11 Glass， S〇G)，然後上光阻，用以定義出電容器的部份，並保留 週邊電路部份上方之旋塗式玻璃；接著進行蝕刻製程，用 以將部份的旋塗式玻璃飩刻掉，再繼續蝕刻半球形矽晶粒 層317，而開口 320”內的半球形矽晶粒層317因有旋塗式 玻璃的保護，所以不會受損。 之後進行濕蝕刻製程，用以剝除部份電容器內的介電 層315a和開口 320”內的旋塗式玻璃，以裸露出下電極318 的表面，於是形成兩個並列的柱狀電容器結構。 接著請參照第圖’然後於下電極318所裸露出的 表面上，形成一厚度約爲人〜6〇人的介電層321。介電層 8 ---------II (請先閲讀背面之注意事項再填寫本頁) 訂 -1¾. 本紙張尺度適用中國國家標隼（CNS) 格（2丨〇><297公釐） 83. 3. 10,000 經濟部中央標準局員工消費合作社印製 490848 2658twfl.doc/0〇6 A7 _ B7 五、發明説明（Γ| ) 321可爲氧化矽層、氮化逆_物-氧化览物_( NO)結構、氧化 吃物-氮化乾将-氧化览物ΟΝΟ)結構，或是其他高介電常 數的介電材料，比如五氧化二鉅、給路鈦酸锆鉛（ΡΖΤ)和 爵緦截酸緦鋇（BST)。之後，在介電層321的表面上，形 成導電層322，用以做爲上電極。於是完成DRAM之電容 器。 另外，由於本發明中，電容器的區域與周邊電路間幾 乎沒有高度差存在，因此不需平坦化的步驟即可進行後續 的製程，可降低製程的風險。 本發明除了形成上述之兩個並列的柱狀電容器外，在 電容器平面面積允許的情況下，可以提高並列的密度，形 成兩個以上的並列柱狀電容器。 本發明的特徵如下： (1) 本發明提供一種並列柱狀電容器的製造方法，可 以增加電容器的表面積。 (2) 本發明提供一種將半球形矽晶粒應用於柱狀電容 器結構的方法，並充份地利用柱狀電容器的表面積，·以增 大電容器的電荷儲存量。 (3) 完成本發明的電容器製程後，電容器的區域與周 邊電路間幾乎沒有高度差存在，因此不需平坦化的步驟即 可進行後續的製程，可降低製程的風險。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公ϋ " ~ δΙΤίΟΟΟΟ ---------φ 裝------訂------ (請先閲讀背面之注意事項再填寫本頁)490848 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 26 5 8twfl .doc / 006 A7 _B7 V. Description of the Invention (f) The present invention relates to the manufacture of a dynamic random access memory (Dynaimc Random Access Memory, DRAM) capacitor A method, and in particular, a method for manufacturing a hemispherical silicon grain (HSG-Si) applied to two side-by-side column capacitors. In DRAM, data is generally stored using a charge or discharge type of an array on a semiconductor substrate. Generally, a capacitor in the form of discharge represents logic 1 and a capacitor in the form of charge represents logic 0. A single bit of binary data is stored in a single capacitor. The access, read and write operations in the memory are completed by the transfer field-effect transistor (Transfer FET) coupling between the charge storage capacitor and the bit line, and are performed by the transfer of the charge after the coupling. The bit line is connected to the source region of the transfer FET, and the charge storage capacitor is connected to the drain region of the transfer FET. The word line signal is supplied to the gate of the transfer FET, and the storage electrode of the charge storage capacitor (Storage Electrode) is connected to the bit line through the transfer FET, so that a charge transfer occurs between the charge storage capacitor and the bit line. phenomenon. Therefore, the amount of charge stored in the capacitor is determined by the electrode surface area of the memory capacitor, the reliability of the electrode isolation, and the dielectric constant of the capacitance dielectric between the charge storage capacitors. However, in order to increase the amount of data stored, the storage density of integrated circuit memory also tends to gradually increase. If more charge is stored in the capacitor ’, the reading amplifier will be greatly reduced by the influence of noise when reading data, and the frequency of refresh will be reduced. And on the charge storage capacitor --------------- ir ------- (Please read the precautions on the back before filling this page) This paper size is applicable to China Standards (CNS) A4 specifications (210X 297 mm) 83. 3. 10,000 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 490848 2 6 5 8twfl .doc / 006 A7 _B7 _ V. Description of the invention (2) Hemispherical Silicon die is a commonly used method to increase dram capacitors recently. FIG. 1 is a cross-sectional view of a conventional application of a hemispherical silicon die to a stack capacitor. On the active area of the semiconductor substrate 100, a field effect transistor is formed, and the field oxide region 101 is used for insulation isolation. The field effect transistor includes a gate structure 104 and a source / drain region 102. 103. Then an insulating layer 105 is formed on the substrate 100, and a contact window opening is formed on the insulating layer 105, and the source / drain regions 102 to be electrically coupled with the capacitor below are exposed, and then sequentially A conductive substance is deposited and hemispherical silicon crystal grains are formed, and then a region of the lower electrode is defined to form a conductive layer 106 and a hemispherical silicon crystal grain layer 107 as shown in the figure. Or hemispherical silicon grains are also formed on the side of the conductive layer 106 to increase the surface area of the capacitor (not shown in the figure). Finally, a dielectric layer 108 and an upper electrode 109 are formed to complete the structure of the capacitor. . However, if hemispherical silicon crystal grains are also formed on the sidewalls of the conductive layer 106, problems such as the increase in the leakage current (LeakaSe Current) of the capacitor dielectric layer and the decrease in the breakdown voltage (Breakdown Voltage) are easily caused. However, if only a hemispherical silicon grain layer 107 is formed on the upper surface of the conductive layer 106, the effective area of the capacitor is not large enough to cope with the tendency of high charge storage capacity, and the refresh time is poor. In addition, after completing the capacitor manufacturing process described above, there will be a height difference between the capacitor area and the peripheral circuits (PenpheryCnxuits). The height difference is about the height of the capacitor, so a chemical mechanical honing process is required to flatten it. To facilitate subsequent processes. In order to solve the problem of insufficient effective area of stacked capacitors, 4 paper sizes are applicable to Chinese national standards (CNS> A4 specification (210X297 mm) 83. 3. 10,000 --------- 4 ^ 装- ----- Order —----- (Please read the notes on the back before filling out this page) 490848 2658twfl .doc / 006 A7 Printed by the Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (>) The solution is to use the structure of a columnar capacitor to increase the effective area of the capacitor. Figure 2 is a cross-sectional view showing the conventional application of hemispherical silicon crystals to a cylindrical capacitor (Cylmder). The part structure, material, and numbering are the same as those in Fig. 1. No further explanation is given here. The structure of the formed columnar lower electrode 116 is shown in the figure. However, the side wall of the columnar lower electrode Π6 does not have hemispherical silicon grains, and After the capacitor manufacturing process is completed, there will still be a height difference between the capacitor area and the surrounding circuits, so a chemical mechanical honing process is required to planarize it to facilitate subsequent processes. Therefore, the main purpose of the present invention is to Provide a columnar electricity The structure of the container, and make full use of the surface area of the columnar capacitor to increase the charge storage capacity of the capacitor, and there is almost no height difference between the area of the capacitor and the surrounding circuit, so it can be carried out without a planarization step. Subsequent manufacturing processes can reduce manufacturing process risks. In order to achieve the above purpose of the present invention, the present invention provides a method for manufacturing two side-by-side columnar DRAM capacitors, and applies hemispherical silicon grains to the structure of side-by-side columnar capacitors. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: Figure 1 is a cross-sectional view of the conventional application of hemispherical silicon grains to stacked capacitors; Figure 2 is a cross-sectional view of the conventional application of hemispherical sand grains to columnar capacitors; 5 ---- -------------, tr ------ (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm (Centi) 83.3.1, 〇〇〇〇 Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the People's Republic of China 490848 2658twfl.doc / 006 A 7 __B7_ V. Description of the Invention (+) Figures 3A to 3E show the manufacturing process of a DRAM capacitor according to a preferred embodiment of the present invention And FIG. 4 is a plan view showing a cover of a lower electrode region according to a preferred embodiment of the present invention. The relationship between each icon number and the component name is as follows: 100, 200: semiconductor substrate 101, 300: field Oxidation region 102, 103, 302, 303: source / drain region 104, 304: gate structure 30.5: field effect transistor 105 '311: insulating layer 106, 314, 322: conductive layer 107, 317: hemispherical sand Grain layers 108, 312, 315, 315a, 321: Dielectric layer 109: Upper electrode 116, 3 1 8: Lower electrode 309: Thickness 310: Contact window openings 320 ,, 320 ": Opening 313: Area of lower electrode 320 : Region 321 to feed the dielectric layer 315: an example of a region covering the dielectric layer 315, as shown in FIG. 3A to FIG. 1EJl, which is a preferred implementation according to the present invention --------- ^ Pack -------- Order ------- (Please read the precautions on the back before filling this page) Applicable to China National Standard (CNS) A4 specification (210X 297 mm) 83. 3. 10,000 ^ 0848 ^ 0848 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 2658twfl.doc / 006 A 7 _B7__ V. Description of the invention (f) An example of a DRAM capacitor manufacturing process cross-sectional view. First, referring to FIG. 3A, a semiconductor substrate 300, such as a? -Type silicon substrate, is provided, and a field effect transistor 305 is formed on its surface. The field effect transistor 305 is formed on the active region of the semiconductor substrate 300, and for example, a field oxide region 301 is used for insulation isolation, or a shallow trench isolation structure (S1TI), and others similar to this structure. The field effect transistor 305 includes a gate structure 304 and source / drain regions 302 and 303. Then, an insulating material, such as an oxide, and a dielectric material, such as Silicon-Oxy-Nitride (SiOxNy), are sequentially formed on the substrate 300. Then, a contact window opening 310 is formed in the insulating substance and the dielectric substance, and the source / drain region 302 to be electrically coupled with the plutonium container is exposed below to form an insulating layer 311 and a dielectric as shown in the figure. Layer 312. The dielectric layer 312 can be used as a protective layer in the subsequent etching process to prevent the subsequent etching process from etching to the insulating layer Μΐϋ, thereby ensuring the insulating effect of the insulating layer 111344-. A layer of conductive material is then formed on the entire surface of the semiconductor substrate 300, such as doped polycrystalline silicon, which fills the contact window opening 310 and contacts the source / drain regions 302. Then, a lithographic etching process is performed to define a region 313 of the lower electrode, and a conductive material with a thickness of 309 is left over the dielectric layer 312 to form a T-shaped conductive layer 314 in the figure. A dielectric layer 315 is then formed on the entire surface of the semiconductor substrate 300. The material of the dielectric layer 315 is, for example, an oxide, and the thickness of the deposited layer is determined by the required capacitance. Please refer to FIG. 4, which illustrates a top view of the mask of the lower electrode region 313. The 320 area shown in the figure is the area where the dielectric layer 315 is to be etched. 7 This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) " 83. 3. 10,000 ^ ------- -^ Install ------ Order ------- (Please read the precautions on the back before filling out this page) 490848 2658twfl.doc / 〇〇6 A7 B7 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs System V. Description of the Invention (G)-The method is, for example, dry etching, and the conductive layer is used as the contact termination layer. The region 321 shown is the region covering the dielectric layer 315. Therefore, after the touch-etching process, as shown in FIG. 3B, two openings 320 'and a dielectric layer 315a are formed on the lower electrode_domain 3n. Next, referring to FIG. 3C, a semi-spherical silicon grain layer 3Π is formed on the surfaces of the dielectric layer 315a and the conductive layer 314, and the opening MO is formed to form the opening 320. The method is, for example, using a zirconium or 2 ^ as a reaction gas. The source is to form a hemispherical silicon grain layer 317 between the amorphous and polycrystalline silicon formation temperature using a low pressure chemical vapor deposition method. Next, referring to FIG. 3D, define a hemispherical sand grain layer 317 to remove the dielectric. The hemispherical silicon grain layer 317 above the layer 315a forms a hemispherical silicon grain layer 317a. The hemispherical silicon grain layer 317 & together with the conductive layer 314 forms the lower electrode 318 of the DRAM capacitor. The method is, for example, prior to the whole The surface of the semiconductor substrate 300 is covered with a layer of spin-coated glass (Spin 〇11 Glass, SOG), and then a photoresist is used to define the capacitor portion and retain the spin-coated glass above the peripheral circuit portion; The etching process is used to etch away a part of the spin-coated glass, and then continue to etch the hemispherical silicon crystal layer 317. The hemispherical silicon crystal layer 317 in the opening 320 "is protected by the spin-coated glass. So it won't be damaged. Then, a wet etching process is performed to peel off the dielectric layer 315a in some capacitors and the spin-on glass in the opening 320 "to expose the surface of the lower electrode 318, so as to form two side-by-side columnar capacitor structures. Then refer to FIG. 'And then on the exposed surface of the lower electrode 318, a dielectric layer 321 having a thickness of about ˜60 is formed. The dielectric layer 8 --------- II (Please Please read the notes on the back before filling in this page) Order -1¾. This paper size applies to China National Standards (CNS) (2 丨 〇 > < 297 mm) 83. 3. 10,000 employees of the Central Standards Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative 490848 2658twfl.doc / 0〇6 A7 _ B7 V. Description of the invention (Γ |) 321 can be a silicon oxide layer, a nitride inversion material, an oxide structure, (NO) structure, and an oxide food-nitrogen Drying-oxidation structure (NONO) structure, or other high dielectric constant dielectric materials, such as pentoxide, lead zirconate titanate (PZVT) and barium terbium titanate (BST). Later On the surface of the dielectric layer 321, a conductive layer 322 is formed for use as an upper electrode. Thus, a capacitor for a DRAM is completed. In addition, In the present invention, there is almost no height difference between the area of the capacitor and the surrounding circuit, so subsequent processes can be performed without a planarization step, which can reduce the risk of the process. In addition to forming the two parallel columns described above, the present invention Outside the capacitor, if the planar area of the capacitor allows, the density of the parallel can be increased to form more than two parallel column capacitors. The features of the present invention are as follows: (1) The present invention provides a method for manufacturing a parallel column capacitor, which can Increase the surface area of the capacitor. (2) The present invention provides a method for applying hemispherical silicon crystal grains to a columnar capacitor structure, and makes full use of the surface area of the columnar capacitor to increase the charge storage capacity of the capacitor. (3) ) After the capacitor manufacturing process of the present invention is completed, there is almost no height difference between the capacitor area and the surrounding circuits, so subsequent processes can be performed without the planarization step, which can reduce the risk of the manufacturing process. Although the present invention has a better The examples are disclosed as above, but it is not intended to limit the present invention. Anyone skilled in this art will not Without departing from the spirit and scope of the present invention, various modifications and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. 9 This paper standard applies to China National Standard (CNS) A4 Specification （210X297 公 ϋ " ~ δΙΤίΟΟΟΟ --------- φ Pack ------ Order ------ (Please read the precautions on the back before filling this page)