CN1110850C - Method for making double-crown electric capacitor - Google Patents

Abstract

The present invention relates to a method for making a double-crown electric capacitor, which comprises: a first dielectric layer is formed; the first dielectric layer is patterned and etched to form a contact window opening; a first conducting layer is formed on the first dielectric layer and fills in the contact window opening; a second dielectric layer is formed on the first conducting layer; the second dielectric layer and the first conducting layer are patterned and etched so as to form an intermediate structure on the contact window opening; a second conducting layer is formed; the second conducting layer is patterned and etched so as to form a plurality of gap walls, and at least one part of the second conducting layer positioned above the second dielectric layer is removed; the second dielectric layer is removed; a third dielectric layer is deposited; a third conducting layer is formed on the third dielectric layer.

Description

The manufacture method of double-crown electric capacitor

(Dynamic Random Access Memory, the DRAM) manufacture method of capacitor particularly relate to the manufacture method of a kind of DRAM double-crown electric capacitor (DoubleCrown Capacitor) to the present invention relates to a kind of dynamic random access memory.

The size of dwindling memory cell is arranged at present, with the trend of the amount of storage capacity (Capacity) that increases integrated level (Integration) and DRAM wafer.When the size of DRAM reduced, the capacitance of DRAM capacitor can relatively reduce.

Typical DRAM memory cell comprises holding capacitor (Storage Capacitor) and access transistor (Access Transistor).Along with the arriving of very lagre scale integrated circuit (VLSIC) (ULSI) DRAM element, size of component is more and more little, and for single memory cell, it is very little that available area has become.Can cause the reduction of capacitor area like this, and then cause the minimizing of capacitance.

For very little memory cell, the plate condenser of prior art (Planar Capacitor) is difficult to use reliably.Especially after the size of capacitor reduced, the capacitance of capacitor also can reduce.Cause capacitor to be very easy to be subjected to the influence of alpha-radiation like this.In addition, when capacitance reduces, must increase the frequency of replenishing (Refresh) again by the holding capacitor stored charge.Even use the insulating barrier of special dielectric film layer (Dielectric Film) as capacitor, simple stacked capacitor (StackedCapacitor) still can not provide enough capacitances.

Attempt certain methods in the prior art and solved the problems referred to above.For example, use groove-shaped capacitor (Trench-shape Capacitor) to increase the area of capacitor.The dielectric film layer thickness that reduces capacitor can increase the capacitance of capacitor, but this method is subject to the problem of output (Yield) and reliability (Reliability).

Used dome-type polysilicon grain (Hemispherical-grain Polysilicon recent years on the structure of capacitor; HSG Polysilicon) capacitor of the capacitor of structure and anti-crown (Reverse-crown) structure.The dome-type polysilicon grain can increase the surface area of capacitor bottom electrode (Bottom Plate), and capacitance is increased.Increase the height of stackable unit (Stack Cell), can increase the capacitance of stacked capacitor.Yet because the height of stackable unit is higher than peripheral circuit (PeripheralCircuit) district, this will cause unit planarization (Cell Planarization) and the metal connecting line difficulty to integrated circuit.

When the size of DRAM during, then need new method to make the undersized capacitor of high-capacitance near deep-sub-micrometer (Deep-submicron).

Therefore the invention provides a kind of manufacture method of double-crown electric capacitor.The method comprises the following steps: to form first dielectric layer in substrate, and it is carried out composition and etching, to form contact window; Then form first conductive layer thereon, and insert contact window; On first conductive layer, form second dielectric layer, and second dielectric layer and first conductive layer are carried out composition and etching, to be positioned at the intermediate structure on the contact window at the free zone line of formation on the contact window; On intermediate structure, form second conductive layer afterwards, and it is carried out composition and etching, form clearance wall, and remove to small part second conductive layer and remove second dielectric layer with sidewall in intermediate structure; Then above first conductive layer and second conductive layer, deposit the 3rd dielectric layer and the 3rd conductive layer successively.

For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborates.In the accompanying drawing:

Fig. 1 to Fig. 8 is the profile at the semiconductor-based end that illustrates the formation step of a kind of capacitor according to a preferred embodiment of the invention; And

Fig. 9 is the top view of the intermediate structure of displayed map 4.

At first please refer to Fig. 1, present embodiment is so that (the p type substrate 100 of the monocrystalline of 100〉crystal orientation (Crystallographic Orientation) is an example.(Field Oxide, FOX) district 102 is with the usefulness as isolation (Isolation) to use traditional method to make thick oxidation.Generally speaking, the manufacturing of field oxide region 102 is to come etching of silicon nitride (SiN)/silica combination layer via photoetching (Photolithography) and dry ecthing (Dry Etching) step.When photoresist (Photoresist) be removed and wet-cleaned (Wet Clean) after, under oxygen containing environment, carry out thermal oxidation (Thermal Oxidation), to form field oxide region 102, its thickness is about 3,000 to 8,000 dusts.

At first, in substrate 100, form grid (Gate) 104, with the grid of the access transistor that is used as the DRAM unit.Traditionally, grid 104 comprises gate oxide (Gate Oxide) and gate electrode (GateElectrode).In the present embodiment, gate oxide can form under oxygen containing environment.Perhaps, can use other known oxide chemistries compositions and step to form gate oxide.In the present embodiment, the thickness of gate oxide is about 30 to 200 dusts.Gate electrode is formed by polycrystalline silicon substances.As known in the art, the formation method of polysilicon can use low-pressure chemical vapor deposition (LPCVD) method to form when source of the gas with methane (Si1ane).The thickness of polysilicon is about 1,000 to 5,000 dust.

Continuation is used traditional method with reference to Fig. 1 in substrate 100, such as Low Pressure Chemical Vapor Deposition, form dielectric layer 112.The thickness of dielectric layer 112 is about 1,000 to 2,000 dust, and its preferable material is a silica.Then, on dielectric layer 112, use traditional method to form one deck silicon nitride layer 114.In the present embodiment, silicon nitride layer 114 is to utilize the Low Pressure Chemical Vapor Deposition deposition, uses dichlorosilane (SiH ₂Cl ₂) work as deposition gas, between in 700 to 800 ℃ on boundary, pressure is about O.1 to 1 torr its temperature approximately.The thickness of silicon nitride layer 114 is approximately between boundary's in 50 to 200 dusts.The formation of silicon nitride layer 114 is the usefulness as etch stop layer (Etching Stop Layer).

Afterwards, silicon oxide layer deposited 116 on silicon nitride layer 114, and its formation method also is a Low Pressure Chemical Vapor Deposition.And silicon oxide layer 116 is also as the usefulness of etch stop layer.

Then please refer to Fig. 2, utilize traditional lithography corrosion process to limit node contact window (NodeContact Opening) 118.Preferred node contact window 118 is positioned at the top center place, source electrode (Source) district of access transistor, and its diameter is about 0.4 micron.Eating thrown silicon oxide layer 116, silicon nitride layer 114 and dielectric layer 112 successively are to form node contact window 118.For example, can on silicon oxide layer 116, deposit a photoresist layer.Then, the photoresist layer is exposed and develop (Develope), to expose node contact window 118.At last, can come etching oxide layer 116, nitration case 114 and dielectric layer 112, until the source area that exposes access transistor via anisotropic etching (Anisotropic Etching) step of one or many.

Then please refer to Fig. 3, deposition one deck polysilicon layer 120 on silicon oxide layer 116, and insert in the node contact window 118.In the present embodiment, polysilicon layer 120 is by traditional chemical vapor deposition (CVD) method deposition.In the present embodiment, the thickness of polysilicon layer 120 is about 2,000 dusts.

On polysilicon layer 120, deposit another layer oxide layer 122 afterwards.Oxide layer 122 is preferably by boron-phosphorosilicate glass (Borophosphosilicate Glass; BPSG) or tetraethoxysilane (Tetraethylorthosilicate; TEOS) form.Oxide layer 122 is at this BPSG/TEOS layer 122 preferably.The formation method of this BPSG/TEOS layer 122 is to utilize traditional chemical vapor deposition method, and its thickness is about 1,000 to 3,000 dust.

Then please refer to Fig. 4, use traditional photoetching technique that BPSG/TEOS layer 122 and polysilicon layer 120 are carried out composition and etching.As shown in Figure 4, between two perimeters (Outer Section) 125, form zone line 123.Perimeter 125 is expanded to far exceeding node contact window 118 places, and in the present embodiment, about 0.4 micron from the border extended of node contact window 118.Remove the polysilicon layer 120 and the BPSG/TEOS layer 122 that are positioned at outside the perimeter 125.And with the etch stop layer of oxide layer 116 as etching polysilicon layer 120.

In addition, an intermediate structure shown in Figure 4 (Intermediate Structure) is remaining polysilicon layer 120 and BPSG/TEOS layer 122 profile along the A-A face of Fig. 9.Fig. 9 is the top view of the intermediate structure of Fig. 4, and as shown in Figure 9, polysilicon layer 120 and BPSG/TEOS layer 122 are one cylindric (Cylindrical Shape).Among another embodiment, the shape of polysilicon layer 120 may be the shape (Closed Shape) of any enclosed, comprises triangle (Triangular), square (Square) or the like.

It should be noted that zone line 123 has a diameter less than node contact window 118, and in a preferred embodiment, its diameter is about 0.3 micron.This will allow to do preferably between the part that all polysilicon layers 120 keep and electrically contact.

Then please refer to Fig. 5, utilize traditional chemical vapour deposition technique above oxide layer 116 and BPSG/TEOS layer 122, to deposit one deck polysilicon layer 124, and insert in the zone line 123.Polysilicon layer 124 preferred thickness are about 500 dusts.In addition, the polysilicon layer 124 at zone line 123 does not fill up it fully.Polysilicon layer 124 sidewall and the bottom of zone line 123 of should only conformally adhering preferably.

Then deposit, expose and development photoresist layer 126, make 126 interior section that covers zone line 123 and perimeter 125 of photoresist layer.Preferably photoresist layer 126 is positioned at the top, center of zone line 123.

Then please refer to Fig. 6, use photoresist layer 126 when mask (Mask), polysilicon layer 124 is carried out anisotropic etching, can use any traditional polysilicon etching technique, with the clearance wall 124b of the exterior side wall that forms clearance wall 124a and perimeter 125.And polysilicon layer 124 parts that remain in photoresist layer 126 below do not come to harm.In addition, and with oxide layer 116 and BPSG/TEOS layer 122 as etch stop layer.

Then please refer to Fig. 7, use traditional oxide wet etch method to remove BPSG/TEOS layer 122 and oxide layer 116.For example, can use diluted hydrofluoric acid (Dilute HF) solution when etchant (Etchant).Afterwards, above remaining polysilicon layer 120,124,124a and 124b, the dome-type polysilicon grain layer 127 that deposition one deck mixes.As known in the art, the dome-type polysilicon grain helps the increase of the surface area of electrode for capacitors.Dome-type polysilicon grain layer 127 can use traditional chemical vapour deposition technique or traditional seeding method (Seeding Method).

Utilize the method, will form the bottom storage node of capacitor.Surface area that it should be noted that memory node has increase, to be used for stored charge.Generally, can above bottom storage node, deposit the skim dielectric layer afterwards, and deposition one deck polysilicon layer is to form the last memory node of capacitor.These traditional steps are with brief being described as follows.

Then please refer to Fig. 8, above polysilicon layer 120, polysilicon layer 124, clearance wall 124a, clearance wall 124b and silicon nitride layer 114, form skim dielectric layer 129.Preferred thin layer dielectric layer is oxide/nitride combination layer, oxide/nitride/combination of oxides layer or tantalum oxide (TantalumOxide) layer.At last, deposit spathic silicon layer 128 is to form the last memory node of capacitor.So finish the manufacturing of double-crown electric capacitor of the present invention.

Though the present invention discloses as above in conjunction with a preferred embodiment; but it is not in order to limit the present invention; those skilled in the art can make various changes and retouching without departing from the spirit and scope of the present invention, so protection scope of the present invention should be defined by accompanying Claim.

Claims (12)

1. manufacture method that forms double-crown electric capacitor in a substrate, this method comprises the following steps:

In this substrate, form one first dielectric layer;

This first dielectric layer of composition and etching is to form a contact window;

On this first dielectric layer, form one first conductive layer, and insert this contact window;

On this first conductive layer, form one second dielectric layer;

This second dielectric layer of composition and etching and this first conductive layer, forming an intermediate structure on this contact window, this intermediate structure has a zone line that is positioned at the sky on this contact window;

On this intermediate structure, form one second conductive layer;

This second conductive layer of composition and etching forms a plurality of clearance walls with the sidewall in this intermediate structure, and remove be positioned at this second dielectric layer top to this second conductive layer of small part;

Remove this second dielectric layer;

Deposition one the 3rd dielectric layer above this first conductive layer and this second conductive layer; And

On the 3rd dielectric layer, form one the 3rd conductive layer.

2. the method for claim 1, wherein this first dielectric layer and this second dielectric layer are formed by silica.

3. the method for claim 1 also is included in the step that forms a dome-type polysilicon grain layer that mixes on this first conductive layer and this second conductive layer.

4. the method for claim 1, wherein this first conductive layer, this second conductive layer and the 3rd conductive layer are formed by polycrystalline silicon substances.

5. the method for claim 1, wherein this dielectric layer is selected from a group, and this group comprises nitride/oxide layer, oxide/nitride/oxide and tantalum oxide layers.

The method of claim 1, wherein the width of this zone line less than the width of this contact window.

7. the method for claim 1, wherein during this second conductive layer of formation, at this zone line reservation opening of part.

8. manufacture method that forms the bottom storage node of capacitor in a substrate, this method comprises the following steps:

In this substrate, form one first dielectric layer;

On this first dielectric layer, form an etch stop layer;

On this etch stop layer, form one second dielectric layer;

This second dielectric layer of composition and etching, this etch stop layer and this first dielectric layer are to form a contact window;

On this second dielectric layer, form one first conductive layer, and insert this contact window;

On this first conductive layer, form one the 3rd dielectric layer;

Composition and etching the 3rd dielectric layer and this first conductive layer, to form an intermediate structure, this intermediate structure covers this contact window, and has the zone line of an opening to be positioned at this contact window;

On this intermediate structure, form one second conductive layer, and conformally cover this zone line;

This second conductive layer of composition and etching forms a plurality of clearance walls with the sidewall in this intermediate structure, and remove be positioned at the 3rd dielectric layer top to this second conductive layer of small part; And

Remove the 3rd dielectric layer.

9. method as claimed in claim 8, wherein, this first dielectric layer, this second dielectric layer and the 3rd dielectric layer are formed by silica.

10. method as claimed in claim 8, wherein, this etch stop layer is formed by silicon nitride.

11. method as claimed in claim 8, wherein, this first conductive layer and this second conductive layer are formed by polycrystalline silicon substances.

12. method as claimed in claim 8 also comprises the step that deposits a dome-type polysilicon grain layer that mixes.

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