A7 457708 • ·. f 681 6twf, doc/008 五、發明說明（I ) 本發明是有關於一種半導體之製造方法，且特別是有 關於一種記憶體電路中溝渠電容器之製造方法。 對於記憶體元件，例如動態隨機快取記憶體（Dynamic Random Access Memory，DRAM)。其利用在基底上大量 的電容器之帶電荷及不帶電荷來儲存二進位資料。一個電 容器代表一記憶位元，對於其儲存之二進位資料「〇」或 「1」分別代表電容器「帶電荷」或「不帶電荷」的狀態。 藉由轉移場效電晶體（Transfer Field Effect Transistor， TFET)，DRAM中讀/寫的動作可被完成，其中轉移場效電 晶體(TFET)之源極連接位元線（Bite Line，BL)，其汲極連 接電容器，其閘極連接字元線（Word Lhie，WL)。經由轉 移場效電晶體（TFET)，此位元線通入一電壓使電容器帶電 荷，並且轉移場效電晶體(TFET)以字元線有選擇性之控制 其成主動或被動，如此就完成寫入之動作。另一方面’如 果想要讀取已被儲存之二進位資料，將位元線切換至比較 器電路（Comparator Circuit)或讀出放大器（Sense Amplifier)，以確定電容器之電壓狀態，做爲讀取之動作。 因此電容器中的電荷儲存是dram中基本的記憶體特性。 電容器中之電荷儲存是取決於電容器中之電容。電容 是依據儲存電極之儲存面積、電容器上電極及下電極間之 絕緣可靠度和介電質之介電常數而定。爲了能夠儲存更多 資料，而增加記憶體元件中之電容器密度。電容器密度增 加將導致儲存電荷減少。如果儲存電荷能留在高處’可有 效的降低讀取時雜訊對讀出擴大器的影響’並且不需經常 3 ----------— ι,'-Ί裝---— — — — — — · · <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 457708 _16twf~ oc 00_B7_____ 五、發明說明（V) 對電容器施加電壓。 當集積度增加時，dram中之記憶儲存單元尺寸相對 的會減少。在習知技術中’電容器尺寸減小會造成電容降 低’如果電容降低，起因於α粒子之軟性誤差（Soft error) 發生機率會上升。因此，要求電容器必須減少其尺寸但又 要維持一定之電容是很重要的。爲了達到此目的，而提出 了不同的電容器結構。 溝渠電谷器就是一種習知的设計形式。在美國專利第 6025225號中已揭露一種溝渠電容器。第1圖與第2圖所 繪示爲一種習知溝渠電容器之結構示意圖。在半導體中之 溝渠電容器一般是當作電極使用，例如是接地電極。此種 設計中，形成溝渠電容器之方法係在半導體基底50上形 成一溝渠52，接著在半導體基底50周圍表面上形成一層 電容器介電層62’最後形成電容器電極70以塡滿溝渠52。 溝渠中之電容器電極連接至金氧半導體（Metal-Oxide Semiconductor，M0S)電晶體而完成記憶體記憶胞。金氧 半導體電晶體可設計成如第2圖所示之橫向彤式或如第1 圖所示之縱向形式。 不論何種形式之金氧半導體電晶體，基底中之溝渠周 圍表面可進行額外之蝕刻製程而形成半球形(Hemispherical) 導電結構。此半球形導電結構可以增加電荷儲存區域，進 而導致電容增加。然而，在溝渠周圍表面形成具有較佳特 性之半球形導電結構以及形成具有較佳均勻性之電容器介 電質薄膜之方法仍在發展中。 4 (請先閲讀背面之注意事項再填寫本頁) 裝--------訂-------！0 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） B7 157 70 8 681 6twf.doc/008 五、發明說明（> ) 本發明提供一種記憶體電路中溝渠電容器之製造方 法。此方法包括在基底中形成一溝渠，而此溝渠在基底中 也當作電容器電極。之後在基底上沈積一層與基底表面共 形之第一導電層，以及第一導電層上形成半球形晶粒層 (Hemispherical Grain，HSG)。接著在半球形晶粒層上進行 一氣相蝕刻製程，以便於至少擴大半球形晶粒間之間隙。 最後形成一電容器介電層覆蓋整個基底，並以第二導電層 當作另一個電容器電極覆蓋在基底上以塡滿溝渠。 上述之氣相蝕刻製程可以蝕刻半球形晶粒層而擴大半 球形晶粒間之間隙。此製程不只可以增加電容器之儲存區 域，也可以在間隙外形上產生一較爲平滑之表面。而使隨 後形成之電容器介電層以較爲均勻以及較爲共形之形狀而 更容易的沈積至半球形晶粒層。 氣相蝕刻製程使用包括鹵素化合物之酸性氣體蝕刻 劑，例如是氫氟酸(HF)或氫氯酸(HC1)，可有效的蝕刻半球 形晶粒層。 第一導電層可例如是經合適摻雜之複晶矽層或非晶矽 層。並且第一導電層在溝渠之周圍表面與基底有電性接 觸。第一導電層不但有助於形成半球形晶粒層，還可保護 溝渠。在氣相蝕刻製程期間，可能造成半球形晶粒的晶粒 間隙之過蝕刻，第一導電層可在氣相鈾刻中防止溝渠被蝕 刻。 充分瞭解上述之先前技術敘述及下列之較佳實施例， 以進一步提供發明專利範圍之解釋。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 (請先閱讀背面之注意事項再填寫本頁) « — — — Ilf — «ΙΙΙΙΙΙΙ- 經濟部智慧財產局員工消費合作社印製 A7 B7 IS7708 68 1 6twf.doc/008 五、發明說明（彳） 圖式之簡單說明： 讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，並進一步提供發明專利範圍之解釋，下文特舉一較 佳實施例，並配合所附圖式，作詳細說明如下：. 第1圖所繪示爲習知具有溝渠電容器之下電極之縱向 金氧半導體電晶體之示意圖。 第2圖所繪示爲習知具有溝渠電容器之下電極之橫向 金氧半導體電晶體之示意圖。 第3A圖至第3E圖所繪示爲根據本發明之一較佳實 施例具有溝渠電容器之下電極之縱向金氧半導體電晶體之 製造流程示意圖β 第4圖所繪示爲根據本發明之一較佳實施例之溝渠電 容器示意圖。 第5圖所繪示爲根據本發明之一較佳實施例具有溝渠 電容器之橫向金氧半導體電晶體示意圖。 第6A圖至第6B圖所繪示爲根據本發明之一較佳實 施例半球形晶粒層在氣相蝕刻前與氣相蝕刻後之結構示意 圖。 圖式之標示說明： 50、100 :基底 52、110 :溝渠 54、56、58、102、104、106 :摻雜層 60 :半球形晶粒 62、122 :電容器介電層 (請先閱讀背面之注意事項再填寫本頁) 裝·--I--— t 訂---------. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（2〗0 X 297公釐） B7 467708 6816twf.doc/008 五、發明說明（< ) 64 ·•閘極 66 :源極/汲極區 68 :電晶體 70、124 :電極 72 :內連線 108 :絕緣層 112 :介電層 114:絕緣間隙壁 116、120 :導電層 118、120a :半球形矽晶層 121 :間隙· 實施例 本發明是有關於以半球型晶粒結構形成溝渠電容器之 方法。特別是應用氣相蝕刻製程在晶粒間增加半球形晶粒 結構之間隙。不但可增加電容器之儲存區域，也可以在間 隙外形產生較平滑之表面。因此使隨後形成之電容器介電 胃以較爲均勻以及較爲共形之形狀而更容易的沈積至半球 形晶粒靥。 下述爲本發明之一說明例，第3A圖至第3E圖所繪示 胃根本發明之一較佳實施例形成溝渠電容器下電極之縱 1金氧半導體電晶體之製造流程示意圖。請參照第3A圖， &供〜半導體基底100。基底100例如是N-型半導體。當 开夕成〜縦向金氧半導體電晶體時，例如是在基底具有一層 N+摻雜層丨〇2、—層p_型摻雜層i〇4 一以及另一層摻 表紙張尺㈣財 <請先閱讀背面之注$項再填寫本頁) 裝--------訂ί 經濟部智慧財產局員工消費合作杜印製 297公釐） B7 457708 68 1 6twf.doc/008 五、發明說明（G) 雜層106 g情況下，摻雜層106與摻雜層102當作兩源極 /汲極區，摻雜層104爲金氧半導體場效電晶體之主體， 並且接著在金氧半導體場效電晶體上提供一通道區。之後 在基底100上形成一層絕緣層108以覆蓋摻雜層106。最 後定義基底100與絕緣層108而形成一溝渠110。 請參照第3B圖，形成一層介電層112,以塡滿溝渠110 較低之位置，介電層112例如是氧化矽層。使用介電層112 當作蝕刻終止層，在溝渠110之側壁上形成至少覆蓋P-型 摻雜層104以及摻雜層106之絕緣間隙壁114。較佳的是 絕緣間隙壁114亦覆蓋摻雜層102之側壁的部分。形成絕 緣間隙壁114之方法例如是先在基底上沈積一層犧牲絕緣 層，接著回鈾犧牲絕緣層。 請參照第3C圖，接著移除介電層112，移除方法例 如是溼式蝕刻。之後在基底100上形成一層與基底100地 形表面共形之導電層116，並且至少覆蓋溝渠110側壁上 直接暴露之部分。導電層116與基底100在摻雜層102有 電性接觸。例如是以熱處理進行擴散，使摻雜層.102之N-型摻質進入導電層116。然而導電層116也可能包括例如 是一層經合適摻雜之複晶矽層以及非晶矽層。其中導電層 116之厚度例如是loo埃至1〇〇〇埃左右。之後在導電層116 上形成半球形晶粒層118。形成半球形晶粒層118之方法 例如是低壓化學氣相沈積法（Low Pressure Chemical Vapor Deposition，PECVD)。最後選擇性的移除在溝渠110以外 之部分導電層116以及部分半球形晶粒層118,或者在溝 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 (請先閲讀背面之注意事項再填窝本頁) -"、 I — ！ ！ 1 訂·！ -^v 經濟部智慧財產局員工消費合作社印製 A7 B7 457708A7 457708 • ·. F 681 6twf, doc / 008 V. Description of the Invention (I) The present invention relates to a method for manufacturing a semiconductor, and more particularly to a method for manufacturing a trench capacitor in a memory circuit. For a memory element, for example, a dynamic random access memory (Dynamic Random Access Memory, DRAM). It uses the charged and uncharged capacitors on a large number of capacitors on the substrate to store binary data. A capacitor represents a memory bit. For binary data "0" or "1" stored in it, it means that the capacitor is "charged" or "non-charged". With the transfer field effect transistor (TFET), the read / write operation in the DRAM can be completed. The source of the transfer field effect transistor (TFET) is connected to the bit line (BL). Its drain is connected to a capacitor, and its gate is connected to a word line (Word Lhie, WL). Via the transfer field-effect transistor (TFET), a voltage is applied to this bit line to charge the capacitor, and the transfer field-effect transistor (TFET) selectively controls its active or passive character line, which is completed. Write action. On the other hand, if you want to read the binary data that has been stored, switch the bit line to a comparator circuit or sense amplifier to determine the voltage status of the capacitor as a read. Action. Therefore, the charge storage in the capacitor is a basic memory characteristic in the dram. The charge storage in a capacitor depends on the capacitance in the capacitor. Capacitance is based on the storage area of the storage electrode, the reliability of the insulation between the capacitor's upper and lower electrodes, and the dielectric constant of the dielectric. In order to be able to store more data, the capacitor density in the memory element is increased. An increase in capacitor density will result in a reduction in stored charge. If the stored charge can be left high, it can effectively reduce the effect of noise on the read amplifier during reading, and does not need to be often 3 ------------ ι, '-Ί 装- -— — — — — — · < Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with China National Standard (CNS) A4 (210 X 297) (%) A7 457708 _16twf ~ oc 00_B7_____ V. Description of the invention (V) Apply voltage to the capacitor. When the degree of accumulation increases, the size of the memory storage unit in the dram will decrease relatively. In the conventional technology, 'capacity reduction will cause capacitance reduction'. If the capacitance reduction occurs, the probability of occurrence of soft errors due to alpha particles will increase. Therefore, it is important to require capacitors to be reduced in size while maintaining a certain capacitance. To achieve this, different capacitor structures have been proposed. Trench electrical valley device is a known design form. A trench capacitor has been disclosed in U.S. Patent No. 6025225. Figures 1 and 2 show the structure of a conventional trench capacitor. Trench capacitors in semiconductors are generally used as electrodes, such as ground electrodes. In this design, a trench capacitor is formed by forming a trench 52 on the semiconductor substrate 50, then forming a capacitor dielectric layer 62 'on the surface surrounding the semiconductor substrate 50, and finally forming a capacitor electrode 70 to fill the trench 52. The capacitor electrode in the trench is connected to a Metal-Oxide Semiconductor (MOS) transistor to complete the memory cell. The metal-oxide semiconductor transistor can be designed in a horizontal type as shown in FIG. 2 or a vertical form as shown in FIG. 1. Regardless of the form of the metal-oxide semiconductor transistor, the surface around the trench in the substrate may be subjected to an additional etching process to form a hemispherical conductive structure. This hemispherical conductive structure can increase the charge storage area, resulting in an increase in capacitance. However, methods for forming a hemispherical conductive structure with better characteristics on the surface around the trench and forming a capacitor dielectric film with better uniformity are still being developed. 4 (Please read the precautions on the back before filling this page) Install -------- Order -------! 0 Printed by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives The paper size is applicable to the Chinese National Standard (CNS) A4 (210x 297 mm) B7 157 70 8 681 6twf.doc / 008 V. Description of the invention (>) The invention provides A method for manufacturing a trench capacitor in a memory circuit. This method includes forming a trench in the substrate, and the trench also acts as a capacitor electrode in the substrate. A first conductive layer conforming to the surface of the substrate is deposited on the substrate, and a hemispherical grain layer (HSG) is formed on the first conductive layer. Then, a gas phase etching process is performed on the hemispherical grain layer so as to at least enlarge the gap between the hemispherical grains. Finally, a capacitor dielectric layer is formed to cover the entire substrate, and the second conductive layer is used as another capacitor electrode to cover the substrate to fill the trench. The gas phase etching process described above can etch the hemispherical grain layer to enlarge the gap between the hemispherical grains. This process can not only increase the storage area of the capacitor, but also create a smoother surface in the gap shape. The capacitor dielectric layer formed later is more easily and uniformly deposited on the hemispherical grain layer. The gas phase etching process uses an acid gas etchant including a halogen compound, such as hydrofluoric acid (HF) or hydrochloric acid (HC1), to effectively etch the hemispherical grain layer. The first conductive layer may be, for example, a suitably doped polycrystalline silicon layer or an amorphous silicon layer. And, the first conductive layer is in electrical contact with the substrate on the surface surrounding the trench. The first conductive layer not only helps to form a hemispherical grain layer, but also protects the trenches. During the vapor-phase etching process, over-etching of the grain gap of the hemispherical grains may be caused, and the first conductive layer can prevent the trenches from being etched in the gas-phase uranium etching. Fully understand the foregoing description of the prior art and the following preferred embodiments to further provide an explanation of the scope of the invention patent. This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) «— — — Ilf —« ΙΙΙΙΙΙΙΙ A7 B7 IS7708 68 1 6twf.doc / 008 V. Description of the invention (彳) Brief description of the drawings: To make the above and other objects, features, and advantages of the present invention more obvious and easier to understand, and further provide the scope of invention patents. Explained below, a preferred embodiment is given below, in conjunction with the accompanying drawings, and described in detail as follows: Figure 1 shows a conventional schematic diagram of a vertical gold-oxide-semiconductor transistor having an electrode below a trench capacitor. Figure 2 is a schematic view of a conventional lateral MOS transistor with a lower electrode of a trench capacitor. Figures 3A to 3E show a lower electrode with a trench capacitor according to a preferred embodiment of the present invention Schematic diagram of the manufacturing process of a vertical metal oxide semiconductor transistor β Figure 4 shows a schematic diagram of a trench capacitor according to a preferred embodiment of the present invention. Figure 5 shows According to a preferred embodiment of the present invention, a schematic diagram of a lateral MOS transistor having a trench capacitor is shown in Figs. 6A to 6B. A hemispherical grain layer according to a preferred embodiment of the present invention is etched in a vapor phase. Schematic diagram of the structure before and after the vapor phase etching. Labeling and description of the drawings: 50, 100: substrate 52, 110: trench 54, 56, 58, 102, 104, 106: doped layer 60: hemispherical grains 62, 122 : Capacitor dielectric layer (please read the precautions on the back before filling this page) Installation · --I --— t Order ---------. This paper is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Standards apply to China National Standard (CNS) A4 specifications (2) 0 X 297 mm B7 467708 6816twf.doc / 008 V. Description of the invention (<) 64 · • Gate 66: Source / Drain Region 68: Electrical Crystals 70, 124: electrodes 72: interconnects 108: insulating layers 112: dielectric layers 114: insulating spacers 116, 120: conductive layers 118, 120a: hemispherical silicon crystal layers 121: gaps. Examples The present invention has A method for forming a trench capacitor with a hemispherical grain structure, especially using a vapor phase etching process to increase the grain size Hemispherical grain structure gap. Not only can increase the storage area of the capacitor, but also produce a smoother surface in the shape of the gap. Therefore, the subsequent formation of the capacitor dielectric stomach with a more uniform and conformal shape is easier The following is an illustrative example of the present invention, and Figures 3A to 3E show a preferred embodiment of the fundamental invention of the stomach. The vertical electrode of a gold oxide semiconductor is used to form the lower electrode of a trench capacitor. Schematic diagram of crystal manufacturing process. Referring to FIG. 3A, & supply to semiconductor substrate 100. The substrate 100 is, for example, an N-type semiconductor. When Kaixi Cheng ~ directional metal oxide semiconductor transistor, for example, there is a layer of N + doped layer 〇 02-p p-type doped layer i 〇 4 and another layer of doped paper on the substrate ; Please read the note on the back before filling in this page.) Packing -------- Order the Consumer Cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs, printed 297 mm) B7 457708 68 1 6twf.doc / 008 5 2. Description of the invention (G) In the case of a 106 g doped layer, the doped layer 106 and the doped layer 102 are regarded as two source / drain regions, and the doped layer 104 is the main body of a gold oxide semiconductor field effect transistor, and then A metal oxide semiconductor field effect transistor provides a channel region. An insulating layer 108 is then formed on the substrate 100 to cover the doped layer 106. Finally, the substrate 100 and the insulating layer 108 are defined to form a trench 110. Referring to FIG. 3B, a dielectric layer 112 is formed to fill the lower portion of the trench 110. The dielectric layer 112 is, for example, a silicon oxide layer. Using the dielectric layer 112 as an etch stop layer, an insulating spacer 114 covering at least the P-type doped layer 104 and the doped layer 106 is formed on the sidewall of the trench 110. Preferably, the insulating spacer 114 also covers a portion of the sidewall of the doped layer 102. The method of forming the insulating spacer 114 is, for example, firstly depositing a sacrificial insulating layer on the substrate, and then returning the uranium sacrificial insulating layer. Referring to FIG. 3C, the dielectric layer 112 is removed, and the removal method is, for example, wet etching. A conductive layer 116 conforming to the ground surface of the substrate 100 is then formed on the substrate 100, and at least a portion directly exposed on the sidewall of the trench 110 is covered. The conductive layer 116 is in electrical contact with the substrate 100 on the doped layer 102. For example, the heat treatment is used to diffuse the N-type dopant of the doped layer .102 into the conductive layer 116. However, the conductive layer 116 may also include, for example, a suitably doped polycrystalline silicon layer and an amorphous silicon layer. The thickness of the conductive layer 116 is, for example, about 100 Angstroms to about 1000 Angstroms. A hemispherical grain layer 118 is then formed on the conductive layer 116. A method for forming the hemispherical grain layer 118 is, for example, a Low Pressure Chemical Vapor Deposition (PECVD) method. Finally, selectively remove part of the conductive layer 116 and part of the hemispherical grain layer 118 outside the trench 110, or in the trench 8 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm> (please first Read the notes on the back and fill in this page)-", I — !!! 1 Order!-^ V Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 457708
6816twf.d〇c/00S 五、發明說明（9 ) 渠110以外之部分導電層116以及部分半球形晶粒層118 可在稍後之移除絕緣層108與絕緣間隙壁Π4中移除。移 除方法例如是化學機械硏磨法（Chemical Mechanical Polishing，CMP)。 半球形晶粒層118在習知技術中是用於增加電容器之 電荷儲存區域。然而可利用進一步之蝕刻改善半球形晶粒 層118。請參照第3D圖，進行氣相蝕刻製程蝕刻半球形 晶粒層118，以便於擴大晶粒間之間隙。第6A圖至第6B 圖顯示蝕刻機構。請參照第6Α圖，在氣相蝕刻前，於導 電層116上形成具有許多晶粒之半球形晶粒層118，且在 晶粒間之間隙並不是平滑的。在此情況下，如果在半球形 晶粒層118上形成電容器介電層，在晶粒間的間隙上的沈 積品質會較差，而造成電容器之品質會較差。接著請參照 第6Β圖，在半球形晶粒層上進行氣相蝕刻製程。在氣相 蝕刻後，可有效的蝕刻半球形晶粒層。在此情況下，使晶 粒間之間隙121較平滑且較擴大。然後，可在間隙121上 隨後形成較爲均勻之電容器介電質薄膜。此外也增加了電 荷儲存區域。另外，如果間隙121產生過蝕刻，導電層116 可以保護被導電層116覆蓋之溝渠表面。一般以經蝕刻之 半球形晶粒層118與導電層116當作導電層120。具有非 等向性蝕刻特性之上述氣相蝕刻製程在氣體之狀態下可有 效的蝕刻半球形晶粒而擴大晶粒間之間隙。 再回到第3D圖，在氣相触刻後，形成包括經蝕刻之 半球形晶粒層118以及導電層U6之導電層120。半球形 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公爱1 -----I-----{、裝 i — ！ — ·— 訂·! — ！ (請先閱讀背面之注意事項再填窝本頁) 經濟部智慧財產局員工消費合作社印製 B7 4iT708 6S 1 6twf,doc/0〇8 五、發明說明） 晶粒層118包括半球形晶粒矽晶層。可利用鹵素化合物例 如是氫氟酸(HF)與氫氯酸(HC1)進行有效率的蝕刻。絕緣層 108可在蝕刻製程中保護基底i〇〇。絕緣間隙壁114可以 防止錯誤之接觸至金氧半保體場效電晶體。 請參照第3E圖，移除絕緣層1〇8以及絕緣間隙壁114， 因此也移除了在絕緣間隙壁114上之部分半球形晶粒層 118以及部分導電層ι16。在此步驟中，摻雜層1〇2當作 下電極使用而形成溝渠電容器之下電極。最後依照習知技 術*在半球形晶粒層120上形成一層電容器介電質薄膜以 及形成另一電容器電極塡滿溝渠而完成溝渠電容器。 請參照第4'圖所顯示未包括縱向電晶體之溝渠電容 器。在溝渠之地形表面上形成經氣相蝕刻之半球形晶粒層 120a’接著在半球形晶粒層i2〇a上形成一層電容器介電 層122,電容器介電層122之材質例如是氧化/氮化/氧化 (ΟΝΟ)介電層與氧化/氮化(on)介電層。之後形成一電極124 塡滿溝渠。當基底100作爲溝渠電容器電極時，電極124 之材質例如是複晶政。. 在相同之情況下形成溝渠電容器，第5圖所繪示爲根 據本發明之一較佳實施例具有溝渠電容器之橫向金氧半導 體電晶體示意圖。請參照第5圖在溝渠電容器旁邊之基底 100例如是？型基底上形成一橫向金氧半導體電晶體68。 電晶體68之一源極/汲極以內連線72連接至電極124。基 底100當作另一個電容器電極。此外應用溝渠電容器在記 憶體元件之橫向金氧半導體電晶體中之技術爲熟習此技藝 (請先閱讀背面之注意事項再填寫本頁) 裝------{訂---I ----- _經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4577086816twf.doc / 00S V. Description of the Invention (9) Part of the conductive layer 116 and part of the hemispherical grain layer 118 other than the channel 110 can be removed later in the insulating layer 108 and the insulating spacer Π4. The removal method is, for example, Chemical Mechanical Polishing (CMP). The hemispherical grain layer 118 is conventionally used to increase the charge storage area of a capacitor. However, further etching can be used to improve the hemispherical grain layer 118. Referring to FIG. 3D, a vapor phase etching process is performed to etch the hemispherical grain layer 118 so as to expand the gap between the grains. 6A to 6B show an etching mechanism. Referring to FIG. 6A, before the vapor phase etching, a hemispherical grain layer 118 having many grains is formed on the conductive layer 116, and the gap between the grains is not smooth. In this case, if a capacitor dielectric layer is formed on the hemispherical grain layer 118, the deposition quality on the gaps between the grains will be poor, resulting in poor capacitor quality. Next, referring to FIG. 6B, a vapor phase etching process is performed on the hemispherical grain layer. After the vapor phase etching, the hemispherical grain layer can be effectively etched. In this case, the gap 121 between the crystal grains is made smooth and enlarged. Then, a relatively uniform capacitor dielectric film may be subsequently formed on the gap 121. There is also an increase in charge storage area. In addition, if the gap 121 is over-etched, the conductive layer 116 can protect the surface of the trench covered by the conductive layer 116. The etched hemispherical grain layer 118 and the conductive layer 116 are generally used as the conductive layer 120. The aforesaid vapor phase etching process having anisotropic etching characteristics can effectively etch hemispherical crystal grains in a gas state to expand the gap between the crystal grains. Returning to FIG. 3D again, after the vapor-phase etching, a conductive layer 120 including an etched hemispherical grain layer 118 and a conductive layer U6 is formed. Hemispherical 9 This paper size is in accordance with Chinese National Standard (CNS) A4 specifications (210 χ 297 Public Love 1 ----- I ----- {, installed i —! — — — Order ·! —! (Please first Read the notes on the back and fill in this page again.) Printed by B7 4iT708 6S 1 6twf, doc / 0008, Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs. 5. Description of the invention) The grain layer 118 includes a hemispherical grain silicon layer. Efficient etching can be performed using halogen compounds such as hydrofluoric acid (HF) and hydrochloric acid (HC1). The insulating layer 108 can protect the substrate 100 during the etching process. The insulating spacer 114 prevents erroneous contact with the metal-oxide semiconductor field effect transistor. Referring to FIG. 3E, the insulating layer 108 and the insulating spacer 114 are removed. Therefore, a part of the hemispherical grain layer 118 and a part of the conductive layer ι16 on the insulating spacer 114 are also removed. In this step, the doped layer 102 is used as the lower electrode to form the lower electrode of the trench capacitor. Finally, a capacitor dielectric film is formed on the hemispherical grain layer 120 according to the conventional technique *, and another capacitor electrode is formed to fill the trench to complete the trench capacitor. Refer to the trench capacitor shown in Figure 4 'without the vertical transistor. A vapor-etched hemispherical grain layer 120a 'is formed on the terrain surface of the trench, and then a capacitor dielectric layer 122 is formed on the hemispherical grain layer i2a. Oxidized / oxidized (ONO) dielectric layer and oxidized / nitrided (on) dielectric layer. An electrode 124 is then formed over the trench. When the substrate 100 is used as a trench capacitor electrode, the material of the electrode 124 is, for example, a compound crystal. A trench capacitor is formed under the same conditions. FIG. 5 shows a schematic diagram of a lateral gold-oxide semiconductor transistor having a trench capacitor according to a preferred embodiment of the present invention. Please refer to Figure 5 for the substrate next to the trench capacitor. A lateral metal-oxide-semiconductor transistor 68 is formed on the substrate. One source / drain interconnect 72 of transistor 68 is connected to electrode 124. The substrate 100 serves as another capacitor electrode. In addition, the application of trench capacitors in the lateral metal-oxide-semiconductor transistor of the memory element is familiar with this technique (please read the precautions on the back before filling this page). --- _Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 457708
681 6twfidoc/00S _B7_ 五、發明說明（f) 者所周知，在此不再贅述。 總之，本發明之特徵爲應用一氣相蝕刻製程以增加晶 粒間半球形晶粒結構之間隙。不僅是增加電容器之儲存區 域，還可以在間隙之外形上形成更平滑之表面。此外'，使 隨後形成之電容器介電層以較爲均勻以及較爲共形之形狀 而更容易的沈積至半球形晶粒層。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閲讀背面之注意事項再填窝本頁) 裝 • n n ----訂--- ο. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐）681 6twfidoc / 00S _B7_ 5. The description of the invention (f) is well known and will not be repeated here. In summary, the present invention is characterized by applying a vapor phase etching process to increase the gap of the hemispherical grain structure between the grains. Not only is the storage area of the capacitor increased, but a smoother surface can be formed outside the gap. In addition, the subsequent formation of the capacitor dielectric layer in a more uniform and conformal shape is more easily deposited on the hemispherical grain layer. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling in this page.) Packing • nn ---- Order --- ο. The paper printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese national standard (CNS) A4 specification ( 210 x 297 mm)