484209 經濟部中央標率局員工消費合作社印製 A7 B7 五、發明説明（/ ) 詳細說明： 本發明係有關積體電路中DRAM(Dynamical Random Access Memory)結構的製作方法，尤其是指其中一種圖案 化電容器結構與同時完成介層孔蝕刻製程的方法。 DRAM是半導體產業上一項極爲重要的積體電路元件， 其主要用途乃是作爲儲存資料用之記憶元件，如電腦中之 記憶體。一般而言，DRAM的結構主要由一場效電晶體與一 電容器所構成，其中電容器之主要功能乃在儲存一定量之 電荷，以作爲記憶元件運作時“〇”或“1”存取的依 據。 電容器的結構與製作方法有很多種。圖一顯示其中一 種常見的圓柱型電容器之結構，其製程步驟主要包括有： 1·首先，於一半導體基板10上，依序形成第一介電層20與 第一氮化矽層30; 2·接著，藉由重複微影、蝕刻與薄膜沉積方式，形成圓柱 型之第一導電層結構40 ; 3·最後，再於該第一導電層結構40上，依序形成電容器介 電層41與第二導電層42，而完成圓柱型電容器基本結構 之製作。 在完成上述電容器結構的製作後，通常都需再進行一 次微影與蝕刻之製程步驟，將互相連結之第二導電層分隔 開，以形成單一獨立的電容器區域。不過，由於所形成的 電容器結構，表面凹凸起伏相當大，因此很難形成均勻塗 覆的光阻層，而導致後續蝕刻製程的困擾。 2 (請先閱讀背面之注意事項再填寫本頁) 丁 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 484209 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（>) 針對上述無法在電容器結構表面上，形成均勻光阻層 的問題，本發明乃提出先形成平坦化之介電層，再進行微 影蝕刻的方式，來達到分隔電容器結構，並同時完成介層 孔蝕刻之目的。其中，整個蝕刻製程由於蝕刻深度的關 係，係分兩階段進行。首先，第一次蝕刻係以分隔電容器 結構爲主。而第二次之蝕刻製程則配合間隙壁之製作’以 完成整個介層孔之蝕刻製程。其製程步驟主要包括有：首 先，於一包含有基板、第一介電層、第一氮化砍層、第一 導電層、電容器介電層與第二導電層之電容器結構上’依 序形成平坦化之第二介電層與均勻被覆之第二氮化矽層； 然後，利用光阻圖案，經第二氮化矽層、第二介電層'第 二導電層、電容器介電層、第一導電層與第一氮化矽層’ 進行第一次介層孔的蝕刻，以分隔電容器結構，該第一二欠 介層孔蝕刻之製程終點，係控制於第一介電層之上；之 後，形成一均勻被覆之第三氮化矽層，然後進行回蝕刻’ 以在介層孔兩側形成間隙壁結構；最後，進行第二次介層 孔蝕刻，而完成介層孔之製作。 以下以圖示及圖號詳細說明本發明實施之情形。 (一)圖示說明 圖一係爲一習知技藝之剖面結構圖，顯示d圓柱型電容器 之基本結構。 圖二係爲本發明製作進行中之剖面結構圖，顯示圖一之結 構，再形成第二介電層與第二氮化矽層後的情形° 3 — 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ▼裝.484209 A7 B7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (/) Detailed description: The present invention relates to a method for manufacturing a DRAM (Dynamicical Random Access Memory) structure in integrated circuits, especially one of the patterns Capacitor structure and method for simultaneously completing via hole etching process. DRAM is an extremely important integrated circuit component in the semiconductor industry. Its main use is as a memory component for storing data, such as the memory in a computer. Generally speaking, the structure of a DRAM is mainly composed of a field effect transistor and a capacitor. The main function of the capacitor is to store a certain amount of charge as a basis for "0" or "1" access when the memory element is operating. There are many types of capacitor structures and manufacturing methods. Figure 1 shows a structure of one of the common cylindrical capacitors, the process steps of which mainly include: 1. First, a first dielectric layer 20 and a first silicon nitride layer 30 are sequentially formed on a semiconductor substrate 10; 2 · Next, a cylindrical first conductive layer structure 40 is formed by repeating lithography, etching, and thin film deposition methods; 3 · Finally, a capacitor dielectric layer 41 and a capacitor dielectric layer 41 are sequentially formed on the first conductive layer structure 40 The second conductive layer 42 completes the fabrication of the basic structure of the cylindrical capacitor. After the capacitor structure is completed, it is usually necessary to perform another lithography and etching process step to separate the interconnected second conductive layers to form a single independent capacitor region. However, due to the formed capacitor structure, the surface unevenness is quite large, so it is difficult to form a uniformly coated photoresist layer, which causes troubles in the subsequent etching process. 2 (Please read the notes on the back before filling this page) The paper size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 484209 A7 B7 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs >) In order to solve the above problem that a uniform photoresist layer cannot be formed on the surface of the capacitor structure, the present invention proposes to first form a planarized dielectric layer and then perform lithographic etching to achieve a capacitor structure separation and simultaneously complete Purpose of via hole etching. Among them, the entire etching process is performed in two stages due to the relationship between the etching depth. First, the first etch was based on the separation capacitor structure. The second etching process is coordinated with the fabrication of the spacers to complete the etching process of the entire via hole. The process steps mainly include: first, sequentially forming on a capacitor structure including a substrate, a first dielectric layer, a first nitride layer, a first conductive layer, a capacitor dielectric layer and a second conductive layer; A planarized second dielectric layer and a uniformly covered second silicon nitride layer; and then using a photoresist pattern through the second silicon nitride layer, the second dielectric layer, the second conductive layer, the capacitor dielectric layer, The first conductive layer and the first silicon nitride layer are etched for the first time to separate the capacitor structure. The end of the first two under-etched holes is controlled on the first dielectric layer. After that, a uniformly coated third silicon nitride layer is formed and then etched back to form a spacer structure on both sides of the via hole; finally, a second via hole etch is performed to complete the fabrication of the via hole . In the following, the implementation of the present invention will be described in detail with illustrations and drawing numbers. (I) Illustrated Figure 1 is a cross-sectional structure diagram of a conventional technique, showing the basic structure of a d cylindrical capacitor. Figure 2 is a cross-sectional structure diagram in progress of the present invention, showing the structure of Figure 1, after the second dielectric layer and the second silicon nitride layer are formed ° 3 — This paper is in accordance with Chinese National Standards (CNS) A4 size (210X 297mm) (Please read the precautions on the back before filling this page) ▼ pack.
、1T ΙΦ, 484209 A7 B7 五、發明説明（）） 圖三係爲本發明製作進行中之剖面結構圖，顯示圖二之結 構，再經光阻圖案，進行第一次介層孔蝕刻而分隔電 容器結構後之情形。 圖四係爲本發明製作進行中之剖面結構圖，顯示圖三之結 構，再形成一均勻被覆之第三氮化矽層後的情形。 圖五係爲本發明製作進行中之剖面結構圖，顯示圖四之結 構，經以回蝕刻方式形成間隙壁結構，之後，再進行 第二次介層孔蝕刻，而完成分隔電容器結構與介層孔 蝕刻製程之情形。 20-第一介電層 30-第一氮化矽層 32-第三氮化矽層 41-電容器介電層 (二)圖號說明 10-基板 21-第二介電層 31-第二氮化矽層 40-第一導電層 42-第二導電層 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 本發明是一種分隔電容器結構，並同時完成介電層蝕 刻的方法。其實施方法則如以下圖二至圖五所示。 首先，請參閱圖二，以半導體產業中習知之製程技 藝，於一包含有基板10、第一介電層20、第一氮化矽層 30、第一導電層40、電容器介電層41與第二導電層42之電 容器結構上，依序形成平坦化之第二介電層21與均勻被覆 之第二氮化矽層31。其中，第二氮化矽層31之厚度約在 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 484209 0年/月π條正/更$ . / (第〇八七一〇八〇—八號專利案之專利說明書修正$ 五 ___ 經濟部智慧財產局員工消費合作社印製 發明説明（〆） 200A〜2000A之間，其係以低壓化學氣相沉積法，於約650°C 所形成。 (請先閲讀背面之注意事項再填寫本頁) 接著，請參閱圖三，利用光阻圖案50，經第二氮化矽層 31、第二介電層21、第二導電層42、電容器介電層41、第一 導電層40與第一氮化矽層3G，以電漿蝕刻方式，進行第一次 介層孔的蝕刻，以分隔電容器結構。其中，該第一次介層孔 蝕刻之製程終點，係控制於第一介電層20之上。於電容器結 構分隔後，再蝕刻去除該光阻層50，以進行下一步驟。 :接著，請參閱圖四，於第二介電層21之上與介層孔內側， 形成一均勻被覆之第三氮化矽層32。其中，第三氮化矽層32 之厚度約在200A〜7Q0A之間，其係以低壓化學氣相沉積法， 於約65G°C所形成。 接著，請參閱圖五，以電漿蝕刻方式，回蝕刻第三氮化 矽層32，以在介層孔兩側形成間隙壁結構33。該間隙壁結構 33，不僅在後續的第二介層孔蝕刻製程中，具有蝕刻保護層 之功用，並可作爲後續金屬化製程中隔離電容器之絕緣層。 最後，藉由間隙壁結構33的保護作用，以電漿蝕刻方式， 對第一介電層20進行第二次介層孔之蝕刻，而完成電容器結 構之分隔與介層孔之製作。 以上所述，爲本發明具體實施的情形，旨在說明本發明 的原則和精神，應可瞭解本發明並不局限於該實施情形，因 此，在本發明之原則和範圍底下作細節上的變化，都應視爲 本發明的進一步實施狀況。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）、 1T ΙΦ, 484209 A7 B7 V. Description of the invention ()) Figure 3 is a cross-sectional structure diagram of the invention in progress, showing the structure of Figure 2, and then separated by photoresist pattern for the first via hole etching. The situation behind the capacitor structure. FIG. 4 is a cross-sectional structure diagram of the production process of the present invention, showing the structure of FIG. 3, and the situation after forming a uniformly covered third silicon nitride layer. Figure 5 is a cross-sectional structure diagram of the production process of the present invention, showing the structure of Figure 4. After the spacer structure is formed by etch-back method, a second interlayer hole etching is performed to complete the separation of the capacitor structure and the interlayer. Case of hole etching process. 20-first dielectric layer 30-first silicon nitride layer 32-third silicon nitride layer 41-capacitor dielectric layer (b) figure number description 10-substrate 21-second dielectric layer 31-second nitrogen Siliconized layer 40-First conductive layer 42-Second conductive layer Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) The invention is a separation capacitor structure, and at the same time complete the introduction Electrical layer etching method. The implementation method is shown in Figures 2 to 5 below. First, please refer to FIG. 2. According to the conventional manufacturing process technology in the semiconductor industry, a substrate 10, a first dielectric layer 20, a first silicon nitride layer 30, a first conductive layer 40, a capacitor dielectric layer 41 and On the capacitor structure of the second conductive layer 42, a planarized second dielectric layer 21 and a uniformly covered second silicon nitride layer 31 are sequentially formed. Among them, the thickness of the second silicon nitride layer 31 is about 4 paper sizes, and the Chinese National Standard (CNS) A4 specification (210X 297 mm) is applicable. 484209 0 / month π positive / more $. / (No. 0087 Amendment of Patent Specification of Patent No. 108—8 No. 5 ___ The invention description printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (〆) is between 200A and 2000A, which is a low-pressure chemical vapor deposition method. Formed at 650 ° C. (Please read the precautions on the back before filling this page.) Then, please refer to Figure 3, using the photoresist pattern 50, passing the second silicon nitride layer 31, the second dielectric layer 21, the second The conductive layer 42, the capacitor dielectric layer 41, the first conductive layer 40, and the first silicon nitride layer 3G are etched for the first time through a plasma etching method to separate the capacitor structure to separate the capacitor structure. Among them, the first The end of the process of etching the secondary dielectric hole is controlled on the first dielectric layer 20. After the capacitor structure is separated, the photoresist layer 50 is removed by etching to proceed to the next step .: Then, please refer to FIG. A uniform coating is formed on the second dielectric layer 21 and inside the dielectric hole. The silicon trinitride layer 32. The thickness of the third silicon nitride layer 32 is about 200A to 7Q0A, which is formed by a low pressure chemical vapor deposition method at about 65G ° C. Next, please refer to FIG. 5 By plasma etching, the third silicon nitride layer 32 is etched back to form a spacer structure 33 on both sides of the via hole. The spacer structure 33 is not only used in the subsequent second via hole etching process, The function of etching the protective layer can be used as the insulating layer of the isolation capacitor in the subsequent metallization process. Finally, by the protective effect of the spacer structure 33, the second dielectric layer 20 is etched by plasma etching. The layer holes are etched to complete the separation of the capacitor structure and the production of the interlayer holes. The above is a specific implementation of the present invention, and is intended to explain the principles and spirit of the present invention. It should be understood that the present invention is not limited to this. Implementation situation, therefore, changes in details under the principles and scope of the present invention should be regarded as the further implementation of the present invention. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)