TW484202B - Method for avoiding overetching of side spacer - Google Patents

Abstract

A method for avoiding overetching of a side spacer can obtain a planar device surface and comprises: patterning a conductive layer and an oxide layer; depositing a conformal insulation layer on the abovementioned pattern layer; using an additional isotropic etching to improve the shape of the insulation layer to make it smoother; and performing an anisotropic etching to obtain a side spacer that is more slant.

Description

A7

This case is China's Patent Bulletin No. 346 6 67 (invention name: "Method of Forming a Gap Wall with a Small Slope"). It relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for forming a spacer. Field of the Invention: The present invention relates to a pretreatment method for protecting a conductive layer from unnecessary conduction, especially before forming a side gap wall, to perform an isotropic etching to prevent the side gap wall from being over-etched. This exposure method can also reduce the topographies on the device to provide a flat surface for subsequent processes. The invention of the invention: The method of forming a side gap wall is an important issue because it serves as a cover for a lightly doped drain (LDD). The other purpose of the gap wall is to protect the conductive layer from unnecessary conduction. . At present, the contour control of the gap wall is widely discussed to meet the requirements of advanced components. The traditional method is to form a vertical side gap wall to meet the length of the gap wall. However, the problem of the gap wall being over-etched may also occur, such as in stacking. In subsequent processes of dynamic dynamic random access memory (DRAMs) such as when etching poiy · 2 and Poly-3, a tapered spacer with high stability and reliability is required. For the remaining and difficult to remove polycrystalline silicon, long-term etching may destroy the paper size in MOS transistors. Applicable to China National Standard (CNS) A4 (210 X 297 mm). Read the note on the back? Please fill in this page for the matter, > -------- Order --------- line. Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 ^ 4202 A7 _______ B7 V. Description of the invention (Side wall. (Note: Please add about, to remove the residual felt + polycrystalline silicon left by Wen Wen, for more details, such as how the residue is generated and how to peel J The reason is that.) On the other hand, because of the increase in the degree of integration, the technology of multilevel interconnections (L, 丄 Λ, and 剐) is also widely discussed. The planarization of the intermetal dielectric layer and the conductive layer , Metallization, and deposition methods are some of the important issues in the multi-metal interconnect process. Generally, semiconductor components use contact windows and interlayer windows to connect different conductive layers inside to form circuits, and use internal dielectric layers to isolate them. These contact windows and interlayer windows. The undulations on the surface of the part will increase the difficulty of subsequent layers of thin film deposition. One of the disadvantages caused by the undulations is that the mask pattern will become worse and the focus will not be able to focus. special Poorly deposited films may cause voids, while holes in the conductive layer increase the resistance of the contact window and increase power consumption. On the other hand, holes in the dielectric layer (such as oxide layer) Affects the quality of the subsequent lithography process. When the subsequent process is built on the wrong photoresist pattern, the yield will be seriously reduced. Therefore, a method to avoid the side gap wall from being over-etched is needed, and this method can also eliminate the traditional The problem of high and low fluctuations and over-etching in the method. Purpose and summary of the invention: The main purpose of the present invention is to provide a pre-treatment method to avoid the side gap wall from being over-etched. The paper size is applicable to Chinese National Standard (CNS) A4 specification (21〇 x 297 公 爱) (Please read the notes on the back before filling in this page)

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 484202 A7 B7 V. Description of the invention () Another object of the present invention is to provide a flat component surface for subsequent processes. According to the above purpose, the method disclosed in the present invention uses an additional isotropic etching process to prevent the side gap walls from being over-etched. After a conductive layer and an oxide layer are deposited and patterned on the wafer, a uniform insulating layer (such as an oxide layer or a silicon nitride layer) is deposited on the thin film pattern, and then an additional isotropic etching process is performed. In order to improve the shape of the insulating layer to make it smoother, an anisotropic etching is performed to obtain a thicker and more inclined side gap wall than before. Brief description of the drawings: The preferred embodiment of the present invention will be supplemented by the following. The graphics will be explained in more detail in the following description: The first figure shows a cross-sectional view of a patterned oxide cover layer and a conductive layer on a wafer The second figure shows a cross-sectional view of forming a spacer deposited layer on the wafer of the first figure; the third figure shows a cross-section view of the anisotropic etching of the spacer; the fourth figure shows the anisotropic etching to form Sectional view of the barrier wall on the oxide capping layer and the conductive layer side wall; Figure 5 shows a cross-sectional view of the traditional method of etching a contact window to form a capacitor deposition layer; Figure 6 shows the etching method based on the method disclosed in the present invention. The size of this paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)

A7 B7 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs i. Description of the invention () Window to form a cross-sectional view of the capacitor deposit layer; The seventh figure shows the traditional method of depositing an MOS transistor by depositing an insulating layer on the wafer A cross-sectional view; and an eighth view are cross-sectional views showing an insulating layer deposited on a wafer when a MOS transistor is manufactured by the method of the present invention. Detailed description of the invention: Please refer to the first figure, which shows a cross-sectional view in which a conductive layer and an oxide cover layer 103 are sequentially formed and patterned. According to a preferred embodiment of the present invention, a crystal is provided. Monocrystalline silicon with a direction of < 1 00 > was used as the substrate 1 〇 丨. Generally, the conductive layer 102 is a poly-1 layer. The poly-1 layer is used to form a zigzag line connected to the gate electrode. The oxide cover layer 103 is a cover formed on the conductive layer 102. Traditionally, an oxide layer is formed. Processes such as TEOS, CVD, and PECVD can be used to deposit the oxide capping layer 103. Then, a barrier wall deposition layer 104 is uniformly formed on the substrate 101, and a material forming the barrier wall (such as silicon nitride or silicon dioxide) can be used to form the barrier wall deposition layer 104. The second figure shows the load-bearing surface after the formation of the spacer deposition layer 104 is completed. Next, the spacer deposition layer 104 is isotropically etched, and conventional isotropic etching methods such as Chemical Dry Etching (CDE) and hydrofluoric acid wet etching (HF dip) can be used to etch the The gap wall deposit layer 104 is, in a preferred embodiment, the remaining gas entering the reaction chamber contains CF4, the flow rate is 100 seem to 500 seem, and the flow rate is 50. This paper size is applicable to Chinese national standards (CNS) A4 size (210 X 297 mm) (Please read the precautions on the back before filling this page)

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, M4202 A7 ^ ^ lift / S ¥ Yue Zhengzheng / more charge ----- B7_ —__ V. Description of the invention () seem to 200 sccm; the temperature range of the reaction chamber is 20 degrees Celsius to 50 degrees Celsius; pressure range is 300 to 1,000 milliTorr. Finally, the spacer deposition layer 104 will become smoother after etching. The third figure shows a cross-sectional view of the spacer deposition layer 104 after isotropic etching. The spacer wall is then anisotropically etched with the spacer layer 104 to form the required side spacers formed on the sidewalls of the conductive layer 10 and the oxide cover layer 103 in a preferred embodiment. In other words, the etching gas flowing into the reaction chamber is CF4, the flow rate is 10 seem to 100 seem, CHF3, the flow rate is 10 sccm to 100 seem, the Ar 'flow rate is 200 seem to 2000 seem; the pressure range is 300 to 2 0 0 mi The temperature of the 11 i T 〇rr 'reaction chamber is between Celsius _ 10 and 60; the operating frequency of the power supply is 4 to 13 · 56 million hertz (mHz), and the power of the power supply is 500 to 1 300 watts. The fourth figure depicts the cross-section of the gap wall deposited layer, which becomes a side gap wall after the anisotropy. As mentioned earlier, the side gap wall is thicker than the corresponding side gap wall formed by traditional methods and More inclined. Generally, the side wall is used as a mask when the lightly doped drain (LDD) is used. The LDD layer must be formed before the side wall is etched. In other words, the LDD layer can also avoid the conductive layer 102 and other conductive layers. Form unnecessary connections, such as poly-2 layers. However, when the subsequent p0ly_2 layer and the poly_3 layer are made, the side gap wall may be over-etched, please refer to the fifth figure, which is described in the figure. A cover layer 107 is used to form a cross-section of the contact window 108A. In addition, the gate structure 105A, the capacitor 106A, the source electrode 109A connected to the word line, and the drain electrode 109B connected to the capacitor 106A are shown in the figure. Obviously, the side wall formed by the traditional method may be applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) due to the paper size. -------: --41 ^ equipment ----- --- Order --------- (Please read the notes on the back before filling this page) A7

V. Description of the invention () The money is too long and the conductive layer 102 of the road knife is exposed. Otherwise, the tapered side gap may be itchy because the thickness is too thin to make the conductive layer too thin. 1 0 2 is separated from the p0iy_2 layer in the contact window 108A. Θ ^ ′ y ζ layer, but when the side gap wall is formed by the method disclosed in the present invention, even if excessive etching occurs, The insulation of the side gap wall will also be fully retained. The sixth figure shows that when a contact window 108B is formed in jgjfn ini, howling wind X Japanese yen 101 In the cross-sectional view, please note that the gate structure 105B and the capacitor 106a in the figure are both formed using the method disclosed in the present invention. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In addition, a flat component surface can also be provided using the disclosed method. Please refer to the seventh figure, which shows the traditional method of forming an insulating layer 1 ii on a multi-metal interconnect In the upper cross-sectional view, the detailed structure of the MOS transistor 110A is not shown here for simplicity, and the depth in the seventh figure is calculated from the top to the bottom of the insulating layer 111. The eighth figure shows a cross-sectional view of the side gap wall of the MOS transistor 1 110B formed by this method. Obviously, the depth H2 is shallower than the depth Η1, so a flat element surface can be obtained with this method. Based on the above, the present invention discloses a method of using an additional isotropic etching process to prevent the side gap wall from being excessively etched. The disclosed method can also obtain a flat element surface and protect the conductive layer from unnecessary And the yield of semiconductor devices can be significantly improved. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other paper dimensions that do not depart from the present invention are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297) Gongai) (Please read the notes on the back before filling this page)

Order: ·% 484202 A7 ___B7_ V. Description of the invention () Equivalent changes or modifications made under the spirit should be included in the scope of patent application below. ----- I ------ ^ 装 —— (Please read the precautions on the back before filling this page) ·

Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, Printed Agricultural Co., Ltd. 484202 / AS Guide 7 Corner_ 余 止 // iL, Supplement B8 1 C8 -----— _ ^ __— _ VI. Patent Application Scope 1. A kind of wafer A method for forming a side spacer on the wafer includes: a patterned cover layer formed on the patterned conductive layer, the method including at least the following steps: depositing a spacer deposition layer on the wafer; isotropic etching The spacer wall deposition layer; and anisotropically etching the spacer wall deposition layer to form the side spacer wall. 2. The method according to item 1 of the scope of patent application, wherein the above-mentioned side spacer is located on the sidewall of the above-mentioned patterned cover layer and the above-mentioned patterned conductive layer. 3. The method according to item 1 of the scope of patent application, wherein the above isotropic etching method is a chemical dry etching method (C h e m i c a 1 D r y E t c h i n g; C D E) method. 4. The method according to item 1 of the scope of patent application, wherein the above isotropic etching method is a hydrofluoric acid wet name etching method (H F d i p p r 0 c e s s). 5. The method according to item 1 of the scope of patent application, wherein the above-mentioned side spacers are uniformly formed on the above-mentioned wafer. 6. The method according to item 1 of the scope of patent application, wherein the above wafer is used to make a dynamic random access memory (DRAM). 7. A method for forming a side gap on a wafer, the method includes at least the paper size applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----------- 4 | ^ Clothes -------- Order --------- ^ 9 (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 484202 A8 B8 C8 D8 The scope of the patent application is as follows: depositing a conductive layer on the wafer; depositing a cover layer on the conductive layer; patterning the conductive layer and the cover layer; uniformly (c ο nf omma 11 y) depositing a The side gap wall is on the wafer; the gap wall deposition layer is etched isotropically; and the gap wall deposition layer is etched anisotropically to form the side gap wall. 8. The method according to item 7 of the scope of patent application, wherein the above-mentioned side gap wall is located on the above-mentioned patterned cover layer and the above-mentioned patterned conductive layer on the side wall. 9. The method according to item 7 of the scope of patent application, wherein the isotropic etching method is a Chemical Dry Etching (CDE) method. 10. The method according to item 7 of the scope of patent application, wherein the isotropic method I is the hydrofluoric acid wet method (H F d i p p r oc c s s). Π. The method according to item 7 of the scope of patent application, in which the above-mentioned wafer is used to make a dynamic random access memory (DRAM) 〇1 2.-A kind of side wall is formed on the wafer Method, the method includes at least the following steps: depositing a conductive layer on the wafer; 10 paper sizes are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) ----------. -------- Order --------- ^ 一 ^ (Please read the precautions on the back before filling in this page) 484202 A8 B8 C8 D8 On the conductive layer; patterning the conductive layer and the cover layer; uniformly (c ο nf omma 11 y) depositing one side spacer on the wafer; isotropically etching the spacer deposition layer; and anisotropic The spacer deposition layer is etched to form the side spacers on the conductive layer and the sidewall of the cover layer. 13. The method according to item 12 of the scope of patent application, wherein the above-mentioned isotropic I insect method is a chemical dry I insect method (C h e m i c a 1 D r y E t c h i n g; C D E) method. 14. The method according to item 12 of the scope of patent application, wherein the isotropic residual method is the hydrofluoric acid wet engraving method (H F d i p p r oc c s s). 15. The method according to item 12 of the scope of patent application, wherein the above wafer is used to make a dynamic random access memory (DRAM). (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm)