-5^566 9 a? ___B7____ 五、發明說明（/ ) 技術領域： 本發明係關於一種積體電路的製程技術，特別是關於用 於自行對準接觸窗(self-align contact ; SAC)之多接觸頭 (butted contact)的製程技術。 發明背景： 半導體元件尺寸的縮小及集積化密度的提高已大幅增加 半導體積底上電路密度，此電路密度的增加已明顯改善電性 的動作表現且減少今日電子產品的生產成本。 然而，在半導體工業致力於元件尺寸縮小時，製程問題 及元件電性的限制使得製造改善動作表現的積體電路有其困 難。製程限制之一就是在蝕刻相當厚絕緣層到基板或到薄非 晶矽層或複晶矽層（如<50〇A)的接觸窗時準確及再現性 控制的能力，而接觸窗是現今半導體元件內部連線的一部 份。 此蝕刻控制問題在具有多層複晶矽的積體電路製造過程 中特別嚴重，於是一種能大幅縮小接觸窗面積的自行對準接 觸(SAC)的製程就被開發出來。 請參考圖一，爲一典型習知技藝形成自行對準接觸 (SAC)的製程方法及其限制，分別含有閘氧化層(未標出）、 複晶矽或金屬矽化物層5、雜質攙雜區(未標出)等電性元件 於一個半導體基板1的主動區與隔離區上，再形成氮化矽 (5丨31^4)的覆蓋介電層(^3此1€(；1：14£：)9和側壁子細&06]：)11以作 爲閘極的絕緣之用，然後形成硼磷攙雜玻璃(BPSG)之類的 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297孓t ) (請先閱讀背面之注意事項再填寫本頁) --------訂---------· 經濟部智慧財產局員Η消費合作社印製-5 ^ 566 9 a? ___B7____ V. Description of the Invention (/) Technical Field: The present invention relates to a process technology for integrated circuits, and particularly to the use of self-align contact (SAC) Process technology for butted contact. Background of the Invention: The reduction in the size of semiconductor components and the increase in integrated density have significantly increased the circuit density on semiconductor substrates. This increase in circuit density has significantly improved electrical performance and reduced the production costs of today's electronic products. However, when the semiconductor industry is working to reduce the size of components, process problems and limitations on the electrical properties of the components make it difficult to manufacture integrated circuits that improve performance. One of the process limitations is the ability to accurately and reproducibly control the etching of contact windows with relatively thick insulating layers to substrates or to thin amorphous silicon layers or polycrystalline silicon layers (such as < 50A), which are nowadays Part of the internal wiring of a semiconductor device. This etch control problem is particularly serious in the fabrication of integrated circuits with multiple layers of polycrystalline silicon, so a self-aligned contact (SAC) process that can significantly reduce the contact window area was developed. Please refer to FIG. 1 for a typical conventional technique for forming a self-aligned contact (SAC) process and its limitations, including a gate oxide layer (not shown), a polycrystalline silicon or metal silicide layer 5, and an impurity doped region. (Not shown) Isoelectric components are formed on the active region and the isolation region of a semiconductor substrate 1 to form a silicon nitride (5 丨 31 ^ 4) overlying dielectric layer (^ 3 this 1 € (; 1:14) £:) 9 and side wall fine & 06] :) 11 for insulation of the gate, and then form borophosphoric doped glass (BPSG), etc. 2 This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 孓 t) (Please read the notes on the back before filling out this page)
經濟部智慧財產局員工消費合作社印制衣 五、發明說明（d) 氧化矽層間介電層13於整個半導體基板1表面，再部分蝕刻 的氮化砂層間介電層13，以形成自行對準接觸(SAC)窗。 然而，因爲氮化矽和氧化矽特性上的差異，在進行至複 晶矽閘極接觸窗21的蝕刻時，須要額外蝕刻去掉未被光阻23 覆蓋的氮化矽，如圖二所示，如此一來，就增加了一次光罩 微影和蝕刻的步驟了，進而也增加了製程的複雜程度。 另一方面，爲了在晶粒(die)上有限的空間中放置最多的 元件同時仍能有效地隔離，淺凹溝隔離(shallow trench isolation ; STI)技術就被開發出來以取代傳統的區域氧化隔 離技術(LOCOS)，而在電性元件彼此之間的連接方式，由最 早的金屬連線(interconnect)或閂柱(plug)來連接複晶矽與矽基 板，逐漸轉而利用減少接觸窗面積的多接觸頭或埋窗接觸 (buried contact)等方式(請參閱S.Wo明ί著”Silicon Processing For the VLSI Era - Vloume 2", pp. 160Ί61) ° 請參閱圖三，爲多接觸頭的佈局方式，所謂的多接觸頭 接觸方式是一次在接觸窗24內同時與複晶矽層5和矽基板 的主動區域27相連。請參閱圖四(A)，爲圖三沿著複晶矽層 5和矽基板的主動區域27接面方向AA之剖面圖，在積體電 路尺寸不斷縮小後，造成了對準偏差(misalign)的機率升高 許多。傳統的自行對準接觸(SAC)多接觸頭製程，若是向左 對準偏差的話’在蝕刻未被光阻圖案35所覆蓋的氮化矽覆蓋 層9之時’電漿就會傷害了自行對準接觸(SAC)窗內24a未被 複晶矽閘極而裸露的矽基板31，造成了基板的凹陷32，如圖 四(A)所示。相似的狀況也會發生在向右對準偏差的情形 3 I. ----------- --- -----訂 ---------線 {請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（2〗〇 X 297公笼） 經濟部智慧財產局貝Η消費合作社印製 425669 A7 ____B7__ 五、發明說明（>) 下，如圖四(B)所示，爲沿著圖三BB方向之剖面圖，在電漿 蝕刻的過程中，無可避免地會過度蝕刻而傷害到自行對準接 觸(SAC)窗內24b的淺溝渠隔離區(STI)33，有可能會在淺溝 渠隔離區(STI)33特別薄弱之處(weak spots)37，造成矽基板 的主動區域短路的情形發生，如圖四(B)所示，進而影響到 產品的良率(yield)和品質。 因此，提供一個高品質之自行對準接觸(SAC)多接觸頭 的製造方法，是半導體工業在邁入次微米領域時，一個非常 重要的課題。 發明之概述： 本發明之主要目的爲提供一種自行對準接觸多接觸頭的 新製程技術，可以防止接觸窗內矽基板的主動區域短路的情 形發生。 本發明之次要目的爲提供一種自行對準接觸多接觸頭的 新製程技術，可以防止接觸窗內主動區域的矽基板在蝕刻過 程中受到傷害，有效提升積體電路產品的良率和品質。 本發明之再一目的爲提供一種自行對準接觸多接觸頭的 新製程技術，可以提供一種不必接觸窗延展區域的設計準 則’有效提升積體電路產品的集積密度，進而降低生產成 本。 本發明係利用以下的製程方式，而達成上述之各種目 的：首先，在半導體基板上定義出主動區和形成淺溝渠隔離 G(STI)後’再形成包含有複晶砍閘極、閘極覆蓋層、側壁 子以及源/汲極區域的場效電晶體。接下來的步驟爲本發明 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------ 枚------ -- 訂------線 I <請先閲讀背面之注意事項再填寫本頁) B7 /12 5 6 6 9 五、發明說明（/) 重點所在，塗佈一層有機的底部抗反射層(bottom anti-reflective coating ; BARC) 和光阻於整個半導體基板表面之 後，並利用微影技術，製定出多接觸頭之接觸窗的光阻圖 案，再利用蝕刻技術將所述底部抗反射層(BARC)、閘極覆 蓋層、側壁子蝕刻去掉以形成閘極自行對準接觸多接觸頭， 最後，將剩餘的光阻圖案63以及底部抗反射層(BARC)同時 除去，本發明所述積體電路自行對準接觸窗的多接觸頭製程 於焉完成。 本發明之重點在於所述有機的底部抗反射層(BARC)， 具有比所述閘極覆蓋層爲慢的蝕刻速率，如此一來，底部抗 反射層(BARC)在蝕刻的過程中，就能達成保護基板主動區 或是淺溝渠隔離區(STI)53不會受到傷害的功效。另一方 面’以硫酸(H2S04)和雙氧水(H202)的混合溶液操作之，即 可以輕易地將光阻以及底部抗反射層(BARC)同時除去，使 得本發明不必對現有製程作太大的改變，具有高度的產業實 用性。 圖式簡要說明： 圖一爲習知技藝形成自行對準接觸窗之剖面圖。 圖二爲習知技藝形成閘極自行對準接觸窗之剖面圖。 圖三爲習知技藝多接觸頭的佈局方式示意圖。 圖四(A)爲習知技藝在對準偏差時，沿著圖三複晶矽層 和矽基板的主動區域接面方向AA之剖面圖。 圖四(B)爲習知技藝在對準偏差時，沿著圖三複晶矽層 和矽基板的主動區域接面方向BB之剖面圖。 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 2请先閱讀背面之注意ί項再填寫本頁) 訂---------線 經濟部智慧財產局員工消費合作社印製 4 256 6 9 a? B7 五、發明說明（f) 圖五(A)爲本發明實施例於形成自行對準接觸的多接觸 頭後之沿著圖三AA方向之剖面圖。 圖五(B)爲本發明實施例於形成自行對準接觸的多接觸 頭後之沿著圖三BB方向之剖面圖。 圖號說明： 1-半導體基板 3-氧化層 5-複晶矽閘極 9-閘極覆蓋層 11-側壁子 13-層間介電層 15-自行對準接觸窗 21-複晶矽閘極接觸窗 23-光阻 27-主動區域 31-半導體基板 33-淺溝渠隔離區(STI) 37-弱點處 51-半導體基板 53-淺溝渠隔離區(STI) 55-複晶矽閘極 57-自行對準接觸窗 58-側壁子 59-閘極覆蓋層 61-底部抗反射層(BARC) 63-光阻 發明詳細說明： 以下實施例以靜態隨機存取記憶體(SRAM)爲例說明本 發明，但本發明之方法亦可推廣應用於各種積體電路，如動 態隨機存取記憶體(DRAM)等。 請參閱圖五(A)和圖五(B) ’首先，在半導體基板5丨上定 義出主動區和形成淺溝渠隔離區(STI)53後，於氧化層3上再 形成包含有複晶矽閘極55、閘極覆蓋層59、側壁子58以及源 /汲極區域(未標出)的場效電晶體。接下來的步驟爲本發明重 6 (請先閱讀背面之注意事項再填寫本頁) ---II 訂------ ---線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國豕铋準（CNS)A4規格（210 X 297公釐） -4256 6 9 A7 ______ B7 五、發明說明（/〉 點所在，塗佈一層有機的底部抗反射層(BARC)61和光阻於 整個半導體基板51表面之後，並利用微影技術，製定出多接 觸頭之接觸窗57的光阻圖案63，再利用蝕刻技術將所述底部 抗反射層(BARC)61、閘極覆蓋層59、側壁子58蝕刻去掉以 形成閘極自行對準接觸多接觸頭，最後，將剩餘的光阻圖案 63以及底部抗反射層(BARC)61同時除去，本發明所述積體 電路自行對準接觸窗的多接觸頭製程於焉完成。 所述淺溝渠隔離區(STI)53通常先是使用電漿蝕刻方 法，如：反應式活性離子蝕刻(RIE)、電子迴旋共振電漿蝕 刻(ECR)或磁場增強式反應式活性離子蝕刻(MERIE)，以含 氯氣體爲反應氣體，在基板51之上形成渠溝。接著，基板31 與渠溝的表面以熱氧化法形成一層墊氧化層(pad oxide)。或 者所述淺溝渠隔離區(STI)53亦可使用熱氧化方法，先在基 板51之上形成一層墊氧化層，然後利用微影與蝕刻技術形成 渠溝，再進行一次熱氧化方法，在渠溝的表面形成一層熱氧 化層，該熱氧化層是作爲隔離之用。 所述複晶矽閘極55通常是複晶矽和金屬矽化物如:矽化 鎢(WSi2)的雙層結構，其厚度介於1000到3000埃之間。所 述閘極覆蓋層59、側壁子58必須是相同的材質，通常是利用 電漿輔助化學氣相沈積法(PECVD)所生成的氮化矽(Si3N4)， 其厚度介於500到1500埃之間，但也可以利用其他的介電層 材料，如利用低壓化學氣相沈積法(LPCVD)所形成之四乙氧 基矽烷(LPTE0S)或是利用電漿輔助化學氣相沈積法(PECVD) 7 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） (請先閱讀背面之注意事項再填寫本頁) ------1 訂------- 線 經濟部智慧財產局員工消費合作社印製 425669 A7 B7 五、發明說明（/ ) 所形成之四乙氧基矽烷(PETEOS)，或是其他型態的氧化 砂。 所述有機的底部抗反射層(BARC)61，通常是高分子聚 合物(polymer)如乙基乳酸鹽(ethyl lactate)之類的物質’具有 比所述閘極覆蓋層59、側壁子58爲慢的蝕刻速率，所述閘極 覆蓋層59與所述底部抗反射層(BARC)61的蝕刻速率比最好 是在1.5到3的範圍之內，其厚度係介於200到5000埃之間， 如此一來，底部抗反射層(BARC)61就能在蝕刻的過程中， 達成保護基板51主動區或是淺溝渠隔離區(STI)53不會受到 傷害的功效。而蝕刻所述底部抗反射層(BARC)61、閘極覆 蓋層59、側壁子58的步驟，也是利用前述之電槳蝕刻技術， 以CH4、N2和Ar的混合氣體操作之。 除去所述光阻圖案63以及底部抗反射層(BARC)61的步 驟，通常是以硫酸(H2S04)和雙氧水(H202)的混合溶液操作 之，即可以輕易地將光阻以及底部抗反射層(BARC)同時除 去。 上述說明係以較佳實施例來闡述本發明，而非限制本發 明，並且，熟知半導體技藝之人士皆能明瞭，適當而作些微 的改變及調整，仍將不失本發明之要義所在，亦不脫離本發 明之精神和範圍。 8 (請先閱讀背面之注意事項再填寫本頁) 訂---------線· 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f )Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (d) A silicon oxide interlayer dielectric layer 13 is formed on the entire surface of the semiconductor substrate 1, and then a partially etched nitrided interlayer dielectric layer 13 is formed to form self-alignment. Contact (SAC) window. However, because of the differences in the characteristics of silicon nitride and silicon oxide, when etching to the polycrystalline silicon gate contact window 21, additional etching is required to remove the silicon nitride that is not covered by the photoresist 23, as shown in FIG. In this way, a step of photolithography and etching is added, and the complexity of the process is also increased. On the other hand, in order to place the most components in a limited space on the die while still being effectively isolated, shallow trench isolation (STI) technology has been developed to replace traditional regional oxidation isolation. Technology (LOCOS), and in the way of connecting electrical components to each other, the earliest metal interconnects or plugs connect the polycrystalline silicon and the silicon substrate, and gradually use the Multi-contact head or buried contact (see S. Wo Ming Ming "Silicon Processing For the VLSI Era-Vloume 2 ", pp. 160Ί61) ° Please refer to Figure 3 for the layout of the multi-contact head Method, the so-called multi-contact contact method is to connect with the polycrystalline silicon layer 5 and the active area 27 of the silicon substrate at the same time within the contact window 24. Please refer to FIG. 4 (A), which is shown in FIG. 3 along the polycrystalline silicon layer 5 The cross-sectional view of the AA in the direction of contact with the active area 27 of the silicon substrate. After the size of the integrated circuit is continuously reduced, the probability of misalignment is increased. The traditional self-aligned contact (SAC) multi-contact head Process if left If the misalignment occurs, 'at the time of etching the silicon nitride cover layer 9 not covered by the photoresist pattern 35', the plasma will hurt the self-aligned contact (SAC) window 24a without the polycrystalline silicon gate and is exposed. The silicon substrate 31 caused a recess 32 of the substrate, as shown in Figure 4 (A). A similar situation also occurs in the case of right-alignment deviation 3 I. ------------ ------- Order --------- Line {Please read the notes on the back before filling in this page) This paper size applies to China National Standard (CNS) A4 specifications (2) 〇X 297 Cage) Printed by the Betty Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 425669 A7 ____B7__ 5. The description of the invention (>), as shown in Figure 4 (B), is a cross-sectional view along the BB direction in Figure 3, which is etched in the plasma In the process, inevitably over-etching will damage the shallow trench isolation region (STI) 33 in the self-aligned contact (SAC) window 24b, which may be particularly weak in the shallow trench isolation region (STI) 33. (weak spots) 37, which caused a short circuit in the active area of the silicon substrate, as shown in Figure 4 (B), which further affected the yield and quality of the product. Therefore, provide a The manufacturing method of high quality self-aligned contact (SAC) multi-contact head is a very important subject when the semiconductor industry enters the sub-micron field. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a self-aligned contact multi-contact. The new process technology of the contact head can prevent the active area of the silicon substrate in the contact window from being short-circuited. A secondary object of the present invention is to provide a new process technology for self-aligning contact multi-contacts, which can prevent the silicon substrate in the active area of the contact window from being damaged during the etching process, and effectively improve the yield and quality of integrated circuit products. Yet another object of the present invention is to provide a new process technology for self-aligning contact multi-contacts, which can provide a design rule that does not need to contact the window extension area 'to effectively increase the integrated density of integrated circuit products, thereby reducing production costs. The present invention uses the following process methods to achieve the above-mentioned various objectives: First, after defining an active area on a semiconductor substrate and forming a shallow trench isolation G (STI), the formation of a complex crystal cut gate and gate cover is performed. Layers, sidewall spacers, and field effect transistors in the source / drain regions. The next step is the present invention. 4 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------ Pieces ---------Order- ----- Line I < Please read the notes on the back before filling this page) B7 / 12 5 6 6 9 V. Description of the invention (/) The main point is to coat an organic bottom anti-reflection layer (bottom anti -reflective coating; BARC) and photoresist on the entire surface of the semiconductor substrate, and use lithography technology to develop a photoresist pattern of the contact window of the multi-contact head, and then use etching technology to the bottom anti-reflection layer (BARC), gate The electrode cover layer and the side wall are removed by etching to form a gate self-aligning contact multi-contact. Finally, the remaining photoresist pattern 63 and the bottom anti-reflection layer (BARC) are removed at the same time, and the integrated circuit according to the present invention is self-aligned. The multi-contact process of the contact window is completed in 焉. The main point of the present invention is that the organic bottom anti-reflection layer (BARC) has a slower etching rate than the gate capping layer. In this way, the bottom anti-reflection layer (BARC) can be etched during the etching process. It achieves the effect of protecting the active area of the substrate or the shallow trench isolation area (STI) 53 from being damaged. On the other hand, when operated with a mixed solution of sulfuric acid (H2S04) and hydrogen peroxide (H202), the photoresist and the bottom anti-reflection layer (BARC) can be easily removed at the same time, so that the present invention does not need to make too much change to the existing process. , Has a high degree of industrial applicability. Brief description of the drawings: Figure 1 is a cross-sectional view of a self-aligned contact window formed by conventional techniques. Fig. 2 is a cross-sectional view of a gate formed by a self-aligned contact window formed by a conventional technique. Figure 3 is a schematic diagram of the layout method of the multi-contact head of the conventional technique. Figure 4 (A) is a cross-sectional view along the direction AA of the active area junction of the polycrystalline silicon layer and the silicon substrate in Figure 3 when the alignment technique is misaligned. Figure 4 (B) is a cross-sectional view along the direction BB of the active area junction of the polycrystalline silicon layer and the silicon substrate in Figure 3 when the alignment technique is misaligned. 5 This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 2 Please read the note on the back before filling this page) Order --------- Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee consumer cooperative 4 256 6 9 a? B7 V. Description of the invention (f) Fig. 5 (A) is a cross-sectional view of the embodiment of the present invention after forming a self-aligned contact multi-contact head along the direction of AA in Fig. 3 . Fig. 5 (B) is a cross-sectional view of the embodiment of the present invention, after forming a self-aligned contact multi-contact, along the BB direction of Fig. 3; Drawing number description: 1-Semiconductor substrate 3-Oxide layer 5-Polycrystalline silicon gate 9-Gate cover 11-Side wall 13-Interlayer dielectric 15-Self-aligned contact window 21-Polycrystalline silicon gate contact Window 23-Photoresistor 27-Active area 31-Semiconductor substrate 33-Shallow trench isolation region (STI) 37-Weak point 51-Semiconductor substrate 53-Shallow trench isolation region (STI) 55-Polycrystalline silicon gate 57-Self-alignment Quasi-contact window 58-side wall 59-gate cover 61-bottom anti-reflection layer (BARC) 63-photoresist Detailed description of the invention: The following embodiments use static random access memory (SRAM) as an example to illustrate the invention, but The method of the present invention can also be popularized and applied to various integrated circuits, such as dynamic random access memory (DRAM). Please refer to FIG. 5 (A) and FIG. 5 (B) 'First, after the active region is defined on the semiconductor substrate 5 and a shallow trench isolation region (STI) 53 is formed, a polycrystalline silicon is formed on the oxide layer 3 The gate 55, the gate cover layer 59, the side wall member 58, and the field effect transistor of the source / drain region (not shown). The next steps are the 6th of the present invention (please read the precautions on the back before filling this page) --- II Order -------- --- Printed by the Consumers Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Applicable to China National Bismuth Standard (CNS) A4 (210 X 297 mm) -4256 6 9 A7 ______ B7 5. Description of the invention (/> Where the point is, apply an organic bottom anti-reflection layer (BARC) 61 and photoresist After the entire surface of the semiconductor substrate 51, the photoresist pattern 63 of the contact window 57 of the multi-contact head is developed by using the lithography technology, and then the bottom anti-reflection layer (BARC) 61 and the gate cover layer 59 are etched using an etching technique. The side wall 58 is etched away to form a gate self-aligning contact multi-contact. Finally, the remaining photoresist pattern 63 and the bottom anti-reflection layer (BARC) 61 are removed at the same time, and the integrated circuit according to the present invention is self-aligning and contacting. The multi-contact process of the window is completed in 焉. The shallow trench isolation region (STI) 53 is usually firstly etched by plasma, such as reactive reactive ion etching (RIE), electron cyclotron resonance plasma etching (ECR), or magnetic field. Enhanced reactive ion etching (MERIE) Using a chlorine-containing gas as a reaction gas, a trench is formed on the substrate 51. Then, a surface of the substrate 31 and the trench is formed by a thermal oxidation method to form a pad oxide layer or the shallow trench isolation region (STI) 53 can also use a thermal oxidation method, first forming a pad oxide layer on the substrate 51, and then using photolithography and etching to form a trench, and then performing a thermal oxidation method to form a thermal oxidation layer on the surface of the trench. The thermal oxide layer is used for isolation. The polycrystalline silicon gate 55 is usually a double-layer structure of polycrystalline silicon and metal silicide such as tungsten silicide (WSi2), and its thickness is between 1000 and 3000 angstroms. The gate covering layer 59 and the side wall 58 must be of the same material, usually silicon nitride (Si3N4) produced by plasma-assisted chemical vapor deposition (PECVD), and the thickness is between 500 and 1500 Angstroms. However, other dielectric layer materials can also be used, such as tetraethoxysilane (LPTE0S) formed by low pressure chemical vapor deposition (LPCVD) or plasma-assisted chemical vapor deposition (PECVD). Paper size applies to China National Standard (CNS) A4 (21〇x 297 mm) (Please read the precautions on the back before filling out this page) ------ 1 Order ------------ Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Online Economics 425669 A7 B7 5. Description of the invention (/) Tetraethoxysilane (PETEOS), or other types of oxidized sand. The organic bottom anti-reflection layer (BARC) 61 is usually a polymer. Substances such as ethyl lactate have a slower etch rate than the gate cover layer 59 and the side wall 58, and the gate cover layer 59 and the bottom anti-reflection layer (BARC) The etching rate ratio of 61 is preferably in the range of 1.5 to 3, and its thickness is between 200 and 5000 Angstroms. In this way, the bottom anti-reflection layer (BARC) 61 can be achieved during the etching process. The function of protecting the active area of the substrate 51 or the shallow trench isolation area (STI) 53 from being damaged. The step of etching the bottom anti-reflection layer (BARC) 61, the gate capping layer 59, and the side wall 58 is also performed by using the aforementioned paddle etching technique with a mixed gas of CH4, N2, and Ar. The step of removing the photoresist pattern 63 and the bottom anti-reflection layer (BARC) 61 is usually performed by using a mixed solution of sulfuric acid (H2S04) and hydrogen peroxide (H202), that is, the photoresist and bottom anti-reflection layer ( BARC). The above description is to illustrate the present invention with a preferred embodiment, but not to limit the present invention. Those skilled in the art of semiconductors will understand that appropriate changes and adjustments will still be made without losing the essence of the present invention. Without departing from the spirit and scope of the invention. 8 (Please read the precautions on the reverse side before filling out this page) Order --------- Line · Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 male f)