483135 經濟部智.¾財產局員工消費合作社印製 A7 B7 五、發明說明（1 ) 【發明領域】： 本發明係關於一種覆晶底部填膠（Flip Chip Underfill )方法，尤指一種降低充填膠材產生熱應力 (Thermal Stress )與吸水性之非流動性底部填膠（N〇_fl〇w Underfill )方法。 【發明背景】： 球栅陣列技術（Ball Grid Array, BGA)為一種先進 的半導體封裝技術，其特點在於採用一基板的正面來安置 半導體晶片，並於該基板的背面植接上複數個銲球（s〇lder Balls )，亦即所明之球柵陣列，以藉由此球柵陣列而將整 個封裝單元銲結及電性連接至外部印刷電路板上。 覆晶型球柵陣列技術（Flip-Chip Ball Grid Array FCBGA)則為一種改良型之BGA封裝技術，其特點係於 晶片電路表面之鐸墊上形成銲塊底部金屬層（UBM，undeT bump metal)，再於該等UBM上施加錫鉛共熔合金的銲料 (以形成以下所稱之錫銲凸塊）並藉高溫回銲（Refl〇w ) 方式將該等鍚銲凸塊（Solder bumps )銲結至一具有多數 銲接銲墊（Solder Pads，一般係銅或鎳銅合金材質）之基 板表面以形成一導電接合結構。由於FCBGA封裝結構中 不需使用較佔空間之輝線（Bonding Wire )來提供晶片電 性連結至基板，因此可使封裝件之整體尺寸製作得更為輕 薄短小。 然而晶片安置於基板銲接銲墊上之後，受到該等錫 銲凸塊分隔而使該半導體晶片與基板間存在有一間隙（以 (請先閱讀背面之注意事項再填寫本頁) Φ ill 訂 * I 1 ---.----線 < 1 ώ V £ *1 C / 〇 τ 1 卞 & Ϊ 63 483135 A7 ___B7___ 五、發明說明（2 ) 下稱為’’覆晶底部間隙”）。若未將此覆晶底部間隙填以絕 緣性膠劑，往往因晶片與基板二者具有不同的熱膨脹係數 (Coefficient of Thermal Expansion，CTE)(—般半導體 晶片之CTE約為3.5 ppm/°C，基板之CTE則介於16-26 ppm/ C之間）而於後績製程之溫-度播_環（Temperature Cycle )中產生過高熱應力，迫使該導電接合結構（即「晶 片銲墊-錫銲凸塊-基板銲接銲墊」所形成之覆晶結構）產 >生疲乏性破裂及電性失能。因此FCBGA封裝結構進行封 裝製程之一必要步驟即為覆晶底部填膠（Flip Chip Underfill)作業，即藉一如環氧樹脂（Ep0XyResin)之 絕緣性膠劑填入覆晶底部間隙，使膠劑完整包覆該等錫銲 凸塊而提供一物理性保護，藉以降低半導體晶片、錫銲凸 塊以及基板間不同熱應力之影響。 經 濟 部 智 •v^u、 財 產 局 消 費 合 社 印 製 (請先閱讀背面之注意事項再填寫本頁) 晶片、錫銲凸塊及基板間熱應力得藉該絕緣膠劑提 供緩衝，乃係因膠劑内含有多量固態填料（S〇iid Filler ) ►(如矽化物、石英或其他微粒物質）致使該膠劑具有近似 錫銲凸塊之熱膨脹係數。然該固態填料之添加將顯著提昇 膠劑黏滯度（Viscosity )，造成充填及固化時間延長而使 產品產率下降。 另一方面，為使錫銲凸塊與基板銲接銲墊間銲熔 (Solder Melting )順利，一般會在回銲作業中使用助銲 劑（Flux )幫助金屬表面清潔，惟當晶片與基板完成固接 後，停留在錫銲凸塊表面之雜質與殘餘助銲劑會阻礙後續 底部填膠作業實施遂需予以清除。但一般清除該殘存助銲 紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱) ------ 2 16311 483135 經 濟 部 智 慧 財 產 局 消 費 合 ft 社 印 η 3 A7 五、發明說明（3 ) 劑時須使用特定清洗設傷造成成本增加，且清洗戶斤用溶劑 多為強腐蝕性或致癌性溶液，往往形成二次污染頗不符合 環保考量。 基於上述缺失，美國專利第6，121，689號 案 Semiconductor flip-chip package and method for tin fabrication thereof”揭露一種將晶片導電接合作業及底部 填膠技術（Undefill )製程合一之非流動性底部填膠技術 (No-flow Under-fill )。該項技術特點係於晶片尚未安置 到基板前，在基板上該等銲接銲墊分布區域預先塗佈一層 特定非流動性膠材，該膠材為一不含固態填料且混有助多 劑之熱塑性或熱固性膠劑，待攜有複數個錫銲凸塊之半专 體晶片對應壓接於該基板適當位置後，利用紅外線回銲（工〗 Reflow)方法進行覆晶接合，助銲劑混入膠劑内可使錫姿 凸塊與基板銲接銲墊順利銲結，復透過回銲之熱循驾 (ThermalCycle)俾使膠材完全填封於覆晶底部間隙·内， 助鲜劑便伴隨勝材永存於封裝結構中無須清除（N〇_ciea Flux)。非流動性膠材雖具有簡化製程及免除助銲劑清隙 的優點，但因膠材内不含有固態填料顆粒，導致整體膠材 的熱膨脹係數（接近70ppm/t：)遠超過半導體晶片及基 板，而使封裝件在後續作業之溫度循環（Temperatm Cycle )下承受過高熱應力引發銲結結構破裂（ hcklng)(如第！圖所示）；此外，是種膠材具有較強吸 水性，因而封裝結構於高溫環境中當 么兄τ㊉因膠材内水氣急速蒸 發引發爆裂（Popcorn )，產品不良率大為提昇 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 16311 -----------------1 ^ ---! !!^ AW (請先閱讀背面之注意事項再填寫本頁) 483135483135 Wisdom of Ministry of Economic Affairs. ¾ Printed by A7 B7 of Consumer Cooperatives of the Property Bureau V. Description of Invention (1) [Field of Invention]: The present invention relates to a method of Flip Chip Underfill, especially a method of reducing the filling filler The material generates thermal stress (Thermal Stress) and water-absorbing non-flowing underfill (N0_fl0w Underfill) method. [Background of the Invention]: Ball Grid Array (BGA) is an advanced semiconductor packaging technology, which is characterized in that a semiconductor wafer is placed on the front side of a substrate, and a plurality of solder balls are implanted on the back side of the substrate. Solder Balls, also known as ball grid arrays, are used to bond and electrically connect the entire package unit to an external printed circuit board through the ball grid array. Flip-Chip Ball Grid Array FCBGA is an improved BGA packaging technology, which is characterized by the formation of a UBM (undeT bump metal) on the pads on the surface of the chip circuit. Then, a solder of a tin-lead eutectic alloy is formed on these UBMs (to form the solder bumps referred to below) and the solder bumps are soldered by means of high temperature reflow (Refl0w). A conductive bonding structure is formed on the surface of a substrate having most solder pads (generally copper or nickel-copper alloy material). Because the FCBGA package structure does not need to use a relatively large space of bonding wire (Bonding Wire) to provide the chip electrical connection to the substrate, the overall size of the package can be made thinner and shorter. However, after the wafer is placed on the substrate soldering pad, it is separated by the solder bumps so that there is a gap between the semiconductor wafer and the substrate (to (please read the precautions on the back before filling this page) Φ ill Order * I 1 ---.---- line < 1 FREE V £ * 1 C / 〇τ 1 卞 & Ϊ 63 483135 A7 ___B7___ V. Description of the invention (2) is called "Flip-Chip Bottom Gap"). If the bottom gap of this flip-chip is not filled with an insulating adhesive, it is often because the wafer and the substrate have different coefficients of thermal expansion (CTE) (normally, the CTE of a semiconductor wafer is about 3.5 ppm / ° C, and the substrate The CTE is between 16-26 ppm / C), and excessive thermal stress is generated in the Temperature Cycle of the subsequent performance process, forcing the conductive bonding structure ("wafer pad-soldering" "Flip-chip structure formed by" bump-substrate soldering pad ") > fatigue fatigue and electrical disability. Therefore, one of the necessary steps for the FCBGA packaging structure to carry out the packaging process is the flip chip underfill operation. That is, an insulating adhesive such as epoxy (Ep0XyResin) is used to fill the bottom gap of the flip chip to make the adhesive. The solder bumps are completely covered to provide a physical protection, thereby reducing the influence of different thermal stresses between the semiconductor wafer, solder bumps and the substrate. Printed by the Ministry of Economic Affairs • v ^ u, printed by the Consumer Cooperative of the Property Bureau (please read the precautions on the back before filling this page). The thermal stress between the wafer, solder bumps and the substrate can be buffered by the insulating adhesive. Because the glue contains a large amount of solid fillers (such as silicide, quartz, or other particulate matter), the glue has a coefficient of thermal expansion similar to that of solder bumps. However, the addition of this solid filler will significantly improve the viscosity of the adhesive (Viscosity), which will cause prolonged filling and curing time and reduce product yield. On the other hand, in order to make soldering between the solder bumps and the substrate pads smooth (Solder Melting), Flux is generally used in the reflow operation to help clean the metal surface. After that, impurities and residual flux remaining on the surface of the solder bumps will hinder the subsequent underfill operation and need to be removed. However, the standard for clearing the residual soldering paper is generally applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) ------ 2 16311 483135 Consumption by the Intellectual Property Bureau of the Ministry of Economic Affairs ft Social Printing η 3 A7 V. Invention Note (3) The use of specific cleaning equipment to increase the cost of the agent, and the solvents used to clean households are mostly strongly corrosive or carcinogenic solutions, and secondary pollution often forms quite inconsistent with environmental protection considerations. Based on the above-mentioned shortcomings, US Patent No. 6,121,689 (Semiconductor flip-chip package and method for tin fabrication thereof) discloses a non-fluid underfill that combines the conductive bonding operation of a wafer and the underfill technology (Undefill) process. No-flow under-fill technology. This technology is characterized in that before the wafer is placed on the substrate, a layer of specific non-flowing glue is pre-coated on the distribution area of the solder pads on the substrate. Thermoplastic or thermosetting adhesives that do not contain solid fillers and are mixed with multiple agents. After the semi-specialized wafers carrying a plurality of solder bumps are correspondingly crimped to appropriate positions on the substrate, infrared reflow is used. (Reflow) The method is to perform flip-chip bonding. The flux is mixed into the glue to make the solder bumps on the substrate and the soldering pads of the substrate smoothly welded. The thermal material of the reflow soldering is used to completely fill the gap in the bottom of the flip-chip. · Inside, the freshener will accompany the permanent material in the packaging structure and does not need to be cleared (N0_ciea Flux). Although the non-flowing adhesive has the advantages of simplifying the process and eliminating the flux clearance, but because The material does not contain solid filler particles, which causes the thermal expansion coefficient (close to 70 ppm / t :) of the overall rubber material to far exceed that of semiconductor wafers and substrates, so that the package is subjected to excessive thermal stress under subsequent temperature cycle (Temperatm Cycle) to cause soldering. The junction structure is cracked (hcklng) (as shown in the figure!); In addition, the glue material has strong water absorption, so the package structure is exposed to high temperature. ), The product defect rate is greatly improved. This paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) 16311 ----------------- 1 ^ --- ! !! ^ AW (Please read the notes on the back before filling out this page) 483135
I I I 訂 請 先 閱 讀 背 面 意 事 項 再 填 寫 本 頁 k 483135 A7 B7 五、發明說明（5 ) 晶底部間隙得被該膠材完全填滿；最後施以回銲作業，利 用膠材内該等鋼粒子引導鋼質輝墊表面的鋼份與錫銲凸塊 之錫鉛共熔合金進行交換，俾使錫銲凸塊與基板鋼質銲墊 間形成強固銲結，即完成本發明之覆晶底部填膠方法。 本發明之特點係提供一種非流動性底部充填膠材， 其包含有一助銲劑，約2〇%重量百分比之鋼粒子以及一 絕緣性膠材基質共同混合而成。充填膠材内添加鋼粒子（熱 膨脹係數約為18 ppm/t：)得使膠材具有與該錫銲凸塊近 似之熱膨脹係數，降低半導體晶片、錫銲凸塊以及基板於 後續製程溫度循環中不同之熱應力差，並提供銅作為濕潤 步驟（Wetting)之引導物質（Wetting pr〇m〇t〇r)俾利回 銲作業之實施；此外，由於銅粒子具備良好的傳熱特性， 故可解決樹腊膠材傳熱不良造成散熱效率不彰的問題，同 時經由鋼粒子的添加調降膠材基質之使用比例更能改善傳 統非流動性底部充填（No — fiow Underfill)膠材吸水性較 高之缺失。 【圖式簡單說明】： 以下茲以較佳具體例配合所附圖式進一步詳細說明 本發明之特點及功效·· 第1圖係為習知之非流動性底部填膠技術於回銲溫 度循環下受熱應力導致銲結結構破裂之剖面示意圖，· 第2圖係為應用本發明覆晶底部填膠技術之半導體 封裝件之剖面示意圖； 第3A至3D圖係為尚未實施回銲作業前，本發明覆 16311 483135 A7 經 濟 部 智 慧 財 產 局 消 費 合 社 印 製 發明說明（6) 底部填膠技術之製作流程； 第4A至4C圖係為實施回銲作業當時，本發明覆蓋 底部填膠技術中’充填膠材與銲結環境間作用機制之假想 示意圖； 第5圖係.备-應甩本發明.覆晶底—部填膠技術之半争體 封裝件於高溫環境下膨脹結構之剖面示意圖；以及， 第6圖係為應用本發明覆晶底部填膠技術之半導體 >封裝件於冷卻環境下收縮結構之剖面示意圖。 【發明詳細說明】： 以下即配合所附圖式第2圖，第3六至3〇圖以及負 4A至4C圖詳細揭露本發明覆晶底部填踢方法之實施例。 第2、圖係顯示採用本發明覆晶底部填膠技術充填圭 二成之半導體封裝件其剖面示意圖。如圖所示，該封屬 口構1係包含-正^⑽上黏置有多數銲接銲墊n之羞 ㈣，一"體晶片12，複數個連接該晶#12且與該等 銲接鲜塾11對㈣接之料凸塊13，多數個#球15 ’以 =用^整包㈣㈣銲凸塊13並填封晶片12與基板 B ^隙16之底部充填膠材14。本發明之特徵係於回 .程進行時，藉—特定底部充填膠材14達成上述目的， 因：現分別就回銲作業實施之前（第3Ai 3D圖）以及 回銲作業實施當時（第4A至4CR、 » 跋古、土制 1弟A至4C ® )，本發明覆晶底部填 ^方法之製程步驟進行描述。 :參閱第3A圖’首先預置一半導體晶片12，該晶片 ―八 作二表面12Qa Μ有多數電子電路及電子元 B曰 (請先閱讀背面之注意事項再填寫本頁) ㈣ ^ 規格（21Q x 297 公爱 6 16311 A7 ___ B7 五、發明說明（7 件之表面）及一相對之非作用表面121，於該作用表面 上形成有複數個晶片銲墊122並在無銲墊分布之作用表面 120上塗佈一絕緣保護層（passivati〇n Layer)(未圖式）。 接著於該等s曰片銲墊122表面形成一銲塊底部金屬化 —(Under Bump Metallizati〇n，UBM)結構層（未圖式）， 復施以銲料俾形成穩固接合於該晶片銲墊122上之複數個 錫鲜凸塊13。該等錫銲凸塊13之主要成分為錫錯共溶合 金（Eutecdc Alley)，如 Sn63/pb37 等，另加入銀、鉍、 銦等少量成分。 另製備一基板10,如第3B圖所示，該基板具有一正 面100及一相對之背面101，於該基板10正面1〇〇上形 成有複數個銲接銲墊u，俾供該等錫銲凸塊（未圖式） 對應接置以提供該半導體晶片（未圖式）電性連接至基板 10。薛接鋅墊n材質之選擇與基板1〇材料有關，該基板 1〇如為陶竟材料，其銲接銲墊u多為鎳銅合金，如使用 有機材質（如BT樹腊或聚亞酿胺樹脂等）基板1〇，其適 用之銲接銲墊11多為純銅所製。 接著’如第3C圖所示’本發明之特徵係提供一種特 定底部充填膠材14’該膠材14用以實施一非流動性底部 充填作業（No-flow Underfill)，即在半導體晶片η安置 於基板ίο前預先以膠材14塗佈於晶片12作用表面12〇 =及基板1G之該等銲接㈣n分布區域上，使得相鄰錫 銲凸塊13或基板1〇表面的銲接銲墊u間之間隙完全被 ，膠材14填充阻絕。此種特定底部充填膠材14呈一流動性 本纸張尺度適用中國國家標準（CNS)A4規格（210x297公髮) 16311 f 訂 線 經 濟 部 智 慧 財 產 局 消 費 合 作 社 印 製 7 8 483135 A7 ___— R7__ 五、發明說明（8 ) 膠液狀態或以黏著性貼片（Adhesive Tape )形式來作用， 且不具有固態填料顆粒（未圖式）而係以聚亞醯胺 (Polynmde)或環氧樹脂（Ep〇xy)樹脂等絕緣性膠材基 質混合助銲劑（Flux )與約20 %重量百分比之銅粒子 (Copper Particles >所構成（此係封裝—結梅巨觀备示圖， 並未標示該膠材基質、料劑以及銅粒+，其;洋細標號請 參酌第4A圖）。 常溫下，將塗佈有該充填膠材14之錫銲凸塊13對 準基板上該等銲接料„位置傾斜壓接，如第3D圖 所示。傾斜壓接之目的在於避免晶片12作用表面12〇上 膠劑14與基板10正面1〇〇上之膠劑14接觸融合時夹捲 空氣，遂能減低充填膠# 14 β氣泡之產1。待該錫鲜凸 塊13對正壓接於該等銲接銲墊Π正上方處，半導體晶片 12與基板Η)間之覆晶底部間隙16亦完全為該充填膠材ρ 所在填’此時該封裝結構」即移入治具⑷（未圖式） 内進行回銲作業。 第4Α至4C圖係表示回銲作業實施時錫銲凸塊與充 填膠材及銲接銲塾三者間作用機制之假想示意圖。如第、4八 圖所=，該充填膠材14係由一絕緣性膠材基質ΐ4〇、約Μ %重里百刀比之銅粒子141以及—反應活性可受作業溫度 ㈣之助辉劑142混合構成。待半導體晶片ΐ2係對正架 ，於想1G該銲接料η正上方時，該錫銲凸塊13與 銲接銲塾11之間俱為該特定充填谬材所充塞。因而， 該充填膠I14内之銅粒子14卜助銲劑142以及懸浮於 G氏張尺度適用中國g^f(CNS)A4規格（21〇 χ撕公以 16311 -----------! I-------------------^ (請先閱讀背面之注意事項再填寫本頁) 州135 A7 經濟部智慧財產局員工消費合作社印製 -----—---- -B7_______五、發明說明（9 ) 膠材基齊！ 140巾的微細氣泡143得以均勻充佈於該錫鋒凸 塊13及鮮接鲜塾I〗之間。 然隨著治具（未圖式）逐漸升溫施壓，會啟動濕潤 (Wettlng)作用機制：首先，如第4B圖所示，高溫活化 助鲜劑142 (活化型助銲劑142，如圖中雙三角標號所示） 以清潔錫銲凸塊13及銲接料n的氧化錢污金屬表面 130,110並為疋成清潔之金屬面提供保護，俾令待銲表 面13〇，110具有優良的銲結接合性（Solder Joint);而後， 覆曰曰底4間隙南| Η受壓減小（如圖中h所示）致使質 軟錫銲凸塊13產生潰縮（c〇Uapse)，鋼粒子141與微細氣泡143受到錫銲凸塊13與銲接銲墊n夾擠而停留於二 者界面17上。 裱境持續升溫，如第4C圖所示，錫銲凸塊13 (如 Sn63/Pb37其熔點183它）呈現熔融狀態瞬間，被迫停留 於錫#凸塊13與銲接銲塾11二者界面間之銅粒子ίο與 微細乳泡143犬遭釋放，微細氣泡143漂浮於熔融錫銲溶 液13 (此即錫銲凸塊13熔融狀態，故標號與錫銲凸塊13 相同）上層，惟銅粒子141比重8 84較熔融錫銲溶液13 (Sn63/Pb37 )比重8·38為大，因此銅粒子141會沉聚於 #接#塾11表面11〇，此時，銅粒子141引導銲接鮮塾η 表面110的銅份擴散至熔融錫銲溶液13而與錫鉛共熔合 金進行交換並迅速形成一「界面合金共化物（Inter_metallic Compound，IMC)」接合層18俾供該錫銲凸塊13與銲接 銲墊11間進行強固鍵結。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 9 16311 ------------丨餐—— (請先閱讀背面之注意事項再填寫本頁) 訂—III Please read the notice on the back before filling in this page k 483135 A7 B7 V. Description of the invention (5) The gap at the bottom of the crystal must be completely filled by the glue; Finally, a reflow operation is performed to use the steel particles in the glue The steel component on the surface of the steel glow pad is guided to exchange with the tin-lead eutectic alloy of the solder bump, so that a strong solder joint is formed between the solder bump and the steel solder pad of the substrate, thereby completing the flip-chip underfill of the present invention. Glue method. A feature of the present invention is to provide a non-flowing underfill material, which comprises a flux, approximately 20% by weight of steel particles and an insulating adhesive material matrix. The addition of steel particles (the coefficient of thermal expansion is about 18 ppm / t :) in the filling material allows the material to have a coefficient of thermal expansion similar to that of the solder bump, reducing the semiconductor wafer, solder bump and substrate during the subsequent process temperature cycle. Different thermal stress differences, and provide copper as a wetting step (Wetting pr0m〇t〇r) of the wetting step (Wetting) to facilitate the implementation of reflow operations; In addition, because copper particles have good heat transfer characteristics, it can be Solve the problem of poor heat dissipation caused by poor heat transfer of the wax material. At the same time, the use of steel particles can reduce the use ratio of the rubber matrix to improve the traditional non-flow underfill (No — fiow Underfill). Gao is missing. [Brief description of the drawings]: The following is a detailed description of the features and effects of the present invention with better specific examples and the attached drawings. Figure 1 shows the conventional non-flowing underfill technology under the reflow temperature cycle. Sectional schematic diagram of the cracked solder joint structure caused by thermal stress. Figure 2 is a schematic sectional view of a semiconductor package using the flip-chip underfill technology of the present invention. Figures 3A to 3D are schematic diagrams of the present invention before reflow operations have been performed. Cover 16311 483135 A7 Printed invention description printed by the Consumers' Association of the Intellectual Property Bureau of the Ministry of Economic Affairs (6) Production process of underfill technology; Figures 4A to 4C are for the implementation of reflow operations. Figure 5 is an imaginary schematic diagram of the interaction mechanism between the rubber material and the welding environment; Figure 5 is a cross-sectional schematic diagram of the expansion structure of the semi-contested package of the underfill-part filling technology in a high temperature environment; FIG. 6 is a schematic cross-sectional view of a shrinkage structure of a semiconductor > package using a flip chip underfill technology of the present invention under a cooling environment. [Detailed description of the invention]: The following is a detailed description of an embodiment of the flip-chip bottom-filling method of the present invention in conjunction with the second drawing, the 36th to 30th drawings, and the negative 4A to 4C drawings. Figure 2 is a schematic cross-sectional view of a semiconductor package filled with 20% of the semiconductor package using the flip-chip underfill technology of the present invention. As shown in the figure, the sealing structure 1 includes-a solder chip with a large number of solder pads n adhered to it, a "body chip 12, a plurality of wafers connected to the crystal # 12 and connected with the solder The 11 bumps 13 are connected to the bumps 13, and most of the balls # 15 are filled with the bumps 13 and the wafer 12 and the bottom of the substrate B gap 16 are filled with an adhesive material 14. The feature of the present invention is that the above-mentioned purpose is achieved by using a specific underfill material 14 during the backhaul process, because: before the reflow operation is performed (Figure 3Ai 3D) and when the reflow operation is performed (Sections 4A to 4A to 3D). 4CR, »Post ancient, 1st A to 4C ®), the process steps of the method for filling the bottom of the flip chip of the present invention will be described. : Please refer to Figure 3A ', a semiconductor wafer 12 is preset first. The wafer—the eight surfaces and two surfaces 12Qa Μ has most electronic circuits and electronic elements B (please read the precautions on the back before filling this page). ^ Specifications (21Q x 297 Public love 6 16311 A7 ___ B7 V. Description of the invention (surface of 7 pieces) and an opposite non-active surface 121, a plurality of wafer pads 122 are formed on the active surface and the active surfaces are distributed on the pad-less surface An insulating protective layer (passivated layer) (not shown) is coated on 120. Then, an under-bump metallization (UBM) structure layer is formed on the surface of the pads 122. (Not shown), further applying solder tin to form a plurality of tin bumps 13 firmly bonded to the wafer pad 122. The main component of the solder bumps 13 is a tin eutectic alloy (Eutecdc Alley) , Such as Sn63 / pb37, and also add a small amount of silver, bismuth, indium, etc. Another substrate 10 is prepared. As shown in FIG. 3B, the substrate has a front surface 100 and an opposite back surface 101, and the front surface 1 of the substrate 10 〇〇 formed a plurality of welding pads u, for Solder bumps (not shown) are connected to provide the semiconductor wafer (not shown) to be electrically connected to the substrate 10. The choice of the material of the x-connection zinc pad n is related to the material of the substrate 10, such as the substrate 10 For ceramic materials, the welding pads u are mostly nickel-copper alloys. For example, if an organic material (such as BT wax or polyurethane resin) is used as the substrate 10, the applicable welding pads 11 are mostly made of pure copper. 'As shown in FIG. 3C', a feature of the present invention is to provide a specific underfill material 14 'which is used to perform a no-flow underfill operation, that is, a semiconductor wafer η is placed on The substrate 14 is coated with the adhesive material 14 on the active surface 12 of the wafer 12 and the welding area n of the substrate 1G in advance, so that the adjacent solder bumps 13 or the solder pads u on the surface of the substrate 10 The gap is completely blocked by the filling material 14. This specific underfill material 14 is fluid. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x297). 16311 f. Printed by the cooperative 7 8 483 135 A7 ___— R7__ 5. Description of the invention (8) The glue state works in the form of adhesive tape (Adhesive Tape), and does not have solid filler particles (not shown). Instead, it is polynmde or Epoxy resin (Epoxy) resin and other insulating adhesive material matrix mixed flux (Flux) and about 20% by weight of Copper Particles (Copper Particles >) (this package-Jiemei giant view, The matrix, materials, and copper particles + of the glue material are not marked, and their foreign symbols are shown in Figure 4A). At normal temperature, the solder bumps 13 coated with the filling material 14 are aligned with the solder on the substrate. The position is crimped, as shown in Figure 3D. The purpose of the crimped crimp is to avoid the active surface of the wafer 12 The 12 sizing agent 14 and the glue 14 on the front surface 100 of the substrate 10 are brought into contact and entangled air, which can reduce the production of the filling glue # 14 β bubble 1. When the tin fresh bump 13 is positively crimped to the Directly above the solder pads Π, the bottom gap 16 between the semiconductor wafer 12 and the substrate Η) is also completely filled with the filling material ρ. 'The packaging structure at this time' is moved into the fixture ⑷ (not shown) ) For reflow operations. Figures 4A to 4C are imaginary schematic diagrams showing the action mechanism between the solder bumps, the filler material, and the solder joint when the reflow operation is performed. As shown in Figures 4 and 4, the filling material 14 is made of an insulating rubber material substrate 40, copper particles 141 with a weight ratio of about 100% by weight, and a brightener 142 whose reaction activity can be affected by the operating temperature. Mixed composition. When the semiconductor wafer ΐ 2 is aligned, when the solder η is thought to be above 1G, the solder bump 13 and the welding 塾 11 are filled with the specific filling material. Therefore, the copper particles 14 in the filler I14, the flux 142, and the suspension in the G-scale scale are applicable to China's g ^ f (CNS) A4 specification (21〇χTrip to 16311 ---------- -! I ------------------- ^ (Please read the notes on the back before filling out this page) State 135 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs- ----—---- -B7 _______ V. Description of the invention (9) The glue base is uniform! The fine bubbles 143 of 140 towels can be evenly filled between the tin front bump 13 and the freshly-sealed fresh bread I〗 However, as the fixture (not shown) gradually heats up and applies pressure, the Wettlng mechanism is activated: First, as shown in Figure 4B, the high-temperature activation freshener 142 (activated flux 142, as shown in the figure) (Indicated by double triangles) Clean the oxidized and stained metal surfaces 130,110 of the solder bumps 13 and the solder n and provide protection for the clean metal surfaces, so that the surfaces to be soldered 13,110 have excellent solder joints. (Solder Joint); Then, the gap 4 at the end of the cover | | The pressure reduction (shown as h in the figure) causes the soft solder bump 13 to collapse (c〇Uapse), the steel particles 141 and Micro bubbles 143 The solder bump 13 and the solder pad n are squeezed and stay at the interface 17. The mounting environment continues to heat up. As shown in Figure 4C, the solder bump 13 (such as Sn63 / Pb37 and its melting point 183) appears. The molten state was forced to stay at the interface between the tin #bump 13 and the solder joint 11 and the copper particles ίο were released, and the fine emulsion bubbles 143 were released, and the fine bubbles 143 floated in the molten solder solution 13 (this is soldering) The bump 13 is in a molten state, so the label is the same as that of the solder bump 13) The upper layer, but the specific gravity 8 84 of copper particles 141 is greater than that of molten solder solution 13 (Sn63 / Pb37) 8.38, so the copper particles 141 will settle At # 接 # 塾 11 surface 11〇, at this time, the copper particles 141 guide the copper content on the surface 110 of the fresh solder to diffuse to the molten solder solution 13 to exchange with the tin-lead eutectic alloy and quickly form an "interface alloy Intermetallic compound (IMC) "bonding layer 18" is used for strong bonding between the solder bump 13 and the solder pad 11. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 9 16311 ------------ 丨 Meal-(Please read the notes on the back before filling in this ) Set -
-£fl «t I 線 483135 經 濟 部 智 慧 財 產 局 消 費 合 社 印 製 Α7 _— ___ Β7 __五、發明說明（10) 第5圖（高溫膨脹）及第6圖（冷卻收縮）係分別 地顯不應用本發明覆晶底部填膠技術之半導體封裝結構於 高溫膨脹以及冷卻收縮之結構型態。如圖所示，回銲作業 之溫度循環中半導體晶片12,錫銲凸塊13以及基板1〇 三者產生不同程度之熱應力棒番魯挤夺封裝膠材体填入 而提供緩衝，鋼粒子（未圖式）之熱膨脹係數約為18 ppm〆 C，因此加入粒徑（Particle Size)約3至1〇微米的銅粒 .子（未圖式）至非流動性底部充填膠材（未圖式，其熱膨 脹係數約70 ppmrC )内得使整體膠材14之熱膨脹係數 明顯降低而於熱循環中產生趨近於錫銲凸塊丨3之熱應 力，以維護導電接合結構的銲接信賴性。另外，該絕緣性 膠材基質（未圖式）内僅添加約2〇%重量百分比之鋼昶 子（未圖式）並不會造成金屬團聚集，故無須顧慮鋼聚稍 引發不當電性導接；此外，銅粒子具備良好的傳熱特性， 遂能解決樹脂膠材傳熱性差造成散熱效率不彰的問題，同 丨時經由鋼粒子的添加調降膠材基質之使用比例更能改善傳 統非流動性底部充填（No-flow Underfill)膠材吸水性較 南之缺失。 以上所述僅為本發明之較佳實施例而已，並非用以 限制本發明之實質技術内容範圍。本發明之實質技術内容 範圍係廣義地定義於下述之申請專利範圍中，任何他人完 成的技術實體或方法，若與下述之申請專利範圍所定義者 係為完全相同或為一種等效之變更，均將被視為涵蓋於下 述之專利範圍之中 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ·——----------裝 (請先閱讀背面之注意事項再填寫本頁) • n n ϋ n n · 訂- -線· 483135 A7 B7 五、發明說明（11 ) 【符號標號說明】： 經濟部智慧財產局員工消費合作社印製 1 半導體封裝結構 10 基板 100 基板正面 101 基板背面 11 銲接銲墊 110，130待銲表面 12 半導體晶片 120 作用表面 121 非作用表面 122 晶片銲墊 13 錫銲凸塊(熔融錫銲溶液） 14 底部充填膠材 140 絕緣性膠材基質 141 銅粒子 142 助銲劑 1425 活化型助銲劑 143 微細氣泡 15 鋒球 16 覆晶底部間隙 17 錫銲凸塊與銲接銲墊界面 18 界面合金共化物 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 11 16311-£ fl «t I line 483135 Printed by the Consumers' Association of Intellectual Property Bureau of the Ministry of Economy Α7 _ — ___ Β7 __ 5. Description of the invention (10) Figure 5 (high temperature expansion) and Figure 6 (cooling contraction) are separately It is obvious that the semiconductor package structure to which the flip-chip underfill technology of the present invention is applied has a structural form of high temperature expansion and cooling shrinkage. As shown in the figure, during the temperature cycle of the reflow operation, the semiconductor wafer 12, the solder bump 13 and the substrate 10 generate different degrees of thermal stress. The extrusion glue is filled to provide cushioning, and the steel particles are filled. The thermal expansion coefficient (not shown) is about 18 ppm〆C, so copper particles with a particle size of about 3 to 10 microns are added. (Not shown) to the non-flowing underfill material (not shown) In order to maintain the welding reliability of the conductive bonding structure, the thermal expansion coefficient of the entire rubber material 14 is significantly reduced and the thermal stress close to the solder bumps 3 is generated in the thermal cycle. In addition, the addition of only about 20% by weight of steel ladle (not shown) in the insulating rubber matrix (not shown) will not cause metal clusters to aggregate, so there is no need to worry that the steel gathering may cause improper electrical conductivity. In addition, copper particles have good heat transfer characteristics, which can solve the problem of poor heat dissipation caused by poor heat transfer properties of resin glues. At the same time, the use of steel particles can reduce the proportion of the glue matrix to improve the traditional The non-flow underfill (No-flow Underfill) glue lacks water absorption compared to the south. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of the essential technical content of the present invention. The substantial technical content scope of the present invention is broadly defined in the scope of patent application described below. Any technical entity or method completed by others is completely the same as or equivalent to the scope of the patent application scope defined below. Changes will be deemed to be covered by the following patent scope. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Please read the notes on the back before filling in this page) • nn ϋ nn · Order--line · 483135 A7 B7 V. Description of Invention (11) [Symbol Description]: Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 1 Semiconductor Package structure 10 Substrate 100 Substrate front 101 Substrate back 11 Welding pads 110, 130 Surfaces to be welded 12 Semiconductor wafers 120 Active surfaces 121 Non-active surfaces 122 Wafer pads 13 Solder bumps (melt solder solution) 14 Underfill material 140 Insulating adhesive matrix 141 Copper particles 142 Flux 1425 Activated flux 143 Micro-bubbles 15 Front ball 16 Gap bottom gap 17 Interface between solder bumps and pads 1 8 Interfacial Alloy Condensate (Please read the notes on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) 11 16311