TW480819B - Modularized single transition counter - Google Patents

Abstract

The present invention provides a single transition counter, used for only transiting one bit in a time interval. The transition counter includes at least one counter module having an input terminal for inputting the clock signals and an output terminal for outputting the control signals. The counter module includes an invisible bit line which will change its logic value when receiving a clock signal, and at least one data bit line, wherein when the data bit line receives the clock signal, and the logic value of the invisible bit line and the logic value of a data bit line having an order lower than the data bit line in the counter module conform to a predefined first computation rule, the logic value of the data bit line is changed. When the logic value of the invisible bit line and the logic value of each non-highest order data bit line in the at least one data bit line conforms to a predefined second computation rule, the counter module will output a control signal at its output terminal.

Description

480819 V. Description of the invention (1) The present invention provides a single-bit conversion counter, especially a high-speed, low-power and modular single-bit conversion counter. In a logic circuit of a computer system, a single bit transition counter (single transition counter) includes a plurality of digital data bit lines representing different levels. When the counter receives a clock signal, only one of the plurality of data bit lines There is a data bit line that generates a logical value conversion, so it is called a "single bit" conversion counter. Please refer to FIGS. 1 to 5. FIG. 1 is a logic circuit diagram of a conventional single-bit conversion counter 10 for generating a logical value conversion of the first data bit line a, and FIG. 2 is a single-bit conversion counter 1 for generating a logical value. The logic circuit diagram of the logic value conversion of the second data bit line & FIG. 3A and FIG. 3B are the logic circuit diagrams of the single bit conversion counter 10 used to generate the logic value conversion of the third data bit line A. Four is a logic circuit diagram of the single-bit conversion counter 10 used to generate the logical value conversion of the one hundredth data bit line ^, and FIG. 5 is a table of the logical values of the data bit lines of the single-bit conversion counter 10. The single bit conversion counter 10 includes a clock pulse input 11, a hidden bit line, and a plurality of data bit lines. . And a plurality of AND gates' (AND gat e t t) 2 1, whenever the clock pulse input 1 1 receives a clock signal, the logic value of the hidden bit line% will change (from 0 to 1, or (From 1 to 0), and the logical value conversion system of the data bit line

480819 V. Description of the invention (2) Generated according to a predetermined operation rule. As shown in Figures 1 and 5, when the gate group 2 1 receives a clock signal from the clock pulse input 11 and the hidden bit line is at 0, the logic value of the data bit line will change. As shown in Figures 2 and 5, when the gate group 2 1 receives a clock signal from the clock pulse input 1 1 and the hidden bit line butterfly j input is 1 and the data bit line A input is 0, the data The logic value of bit line A changes. As shown in Figure 3A and Figure 5, when the gate group 2 1 receives a clock signal from the clock pulse input 1 1 and hides the bit line% and the input of the data bit line A is 1, the data bit line is clever. When the input is 0, the logical value of the data bit line $ will change. As shown in Figures 4 and 5, when the gate group 2 1 receives a clock signal from the clock pulse input 1 1 and hides the bit line 〃. When the input of data bit lines A to ^ is 1, and the input of data bit line ~ is 0, data bit line θ1 (). The logical value will change. That is, when the gate group 2 1 receives a clock signal from the clock pulse input 1 1 and the input of the hidden bit line% and the data bit line to 1 is 1, and the input of the data bit line l is 0. As a result, the logical value of the data bit line ~ changes, where X is a positive integer at least equal to 3. Please refer to FIG. 3A and FIG. 3B. FIG. 3A is a simplified logic circuit diagram of FIG. 3B. As can be seen from FIG. 3A and FIG. It can be seen from the same reason that the sum gate group 21 in Fig. 4 is composed of 100 sum gates 24. As shown in Figures 1 to 4, whenever a data bit line is added to the counter 10, a sum gate must be added to the counter 10, and all bit lines and clock pulses of lower order than the data bit line are added. The wave input 11 is connected to the input of the sum brake group. As can be seen from Figure 4, when a higher-order data bit line is added

V. Invention Description 57: Many? The calculation function can be achieved in a short time. The calculation accuracy, the two reds, and the scottish dolls are very complicated, and it will slow down the power of the counter 10, which is the high-speed operation of the technical policy f. Therefore, the counter 10 cannot meet the current differences. Requirements for reducing power consumption. And minus: the main purpose of Ϊridge ΐ fming is to provide a kind of modular counters that can operate the high-speed line, ί ί. Complete the counting operation with a large number of data bits. The modular counter can save power consumption and quickly refer to Figure 6. Figure 6 is a single-bit conversion counter of the present invention (stars 1, 2 and lransitiori counter) 50 Part of the circuit diagram. :::: 2 The counter 50 will only convert a single bit in a time, and its ^ # 从 '、、 呀 Pulse 5 1 is used to generate a system pulse to control the counter of 0 50 and multiple counting modes. Groups 5, 2, 5, 8, 60 and 62 are connected in a cascade manner. Each counting module 52, 58, 60, 62 t 2 + Di 2 2 terminal 54 is used to input the clock signal, and an output terminal 5 6 is =, the counting module "and 52, 58, 60, 62 &; Contains -Hidden = Une), which will change its logical value (from 0 to 1, and four data bit lines) after counting modules 52, 58, and one-day pulse signals. 7 =, for number f, and 52, it contains a hidden bit line Q; and data bits ^ t '42, AQ, 3, & for the second counting module 58, it contains hidden Zigzag line Q4, and data bit line & Qe, I; with (n + 1) th

Page 7 480819 V. Description of the invention (4) The counting module 6 0 includes a hidden bit line Q 4n 'and a data bit line Q4n + 1, Q4n + 2, Q4n + 3, and Q4n + 4; Taking the (Π + 2) th counting module 60, it includes a reduced bit line Q 4ιί + 4 and a data bit line Q 4n + 5, Q 4η + 6, 〇4η + 7, Q 4n + The change of the logic value of the 80 bit line can be explained as follows, taking the (n + 1) th counting module 60 as an example: when the counting module 60 receives a clock signal at its input terminal 5 4 and hides the bit When the logic value of the line Q 4n 'is 0, the logic value of the data bit line Q 4nH changes. When the counting module 60 receives a clock signal and the logic value of the hidden bit line Q 4n 'is 1, and the logic value of the data bit line Q 4n + 1 is 0, the data bit line Q 4n + 妁 logic value will change. When the counting module 60 receives a clock signal and the logic value of the hidden bit line Q 4n 'and the data bit line Q 4n + 1 is 1, and the data bit line Q 4n + has a logic value of 0, the data bit The line Q 4n + fishing logic value will change. When the counting module 60 receives a clock signal and hides the bit line Q 4n 'and the data bit lines Q 4nH, Q 4n + logical logic value 1, the logical value of the data bit line Q 4n + 3 is 0 The data bit line Q 4n + fishing logic value will change. The generation of the control signal can be explained as follows, taking the (n + 1) th counting module 60 as an example: when the counting module 60 receives a clock signal from its input terminal 5 4 and hides the bit line Q4n 'and the data bit When the Q4n + 1, Q4n + 2, Q4n + fishing logic values of the element lines are 1, the counting module 60 will generate a control signal at its output terminal 5 6, and the control signal will be related to the system pulse generated by the system clock 51. The wave is input together with the gate 64 to generate the clock signal of the input counting module 62. When the counting module 6 2 receives the clock signal, the logic value of the hidden bit line Q 4n + 4 'will change. Then count

480819 V. Description of the invention (5) The logical value of the data bit line in the number module 6 2 will be based on the logical value of the hidden bit line Q 4n + 4 'and the ratio of the data bit line in the counting module 6 2 to the data bit line. The logic value of the lower-order data bit line is changed. Please refer to Figure 7. Figure 7 is the timing diagram of the single-bit conversion counter 50. As shown in Fig. 7, after the counting module 5 2 receives the system pulse generated by the system clock 51, the logic value of the hidden bit line Q 0 'will change. When the counting module 5 2 receives the system pulse and the logic value of the hidden bit line Q G 'is 0, the logic value of the data bit line Q changes. When the counting module 5 2 receives the system pulse and the logic value of the hidden bit line Q 0 ′ is 1, and the logic value of the data bit line Q fishing is 0, the logic value of the data bit line Q fishing will change. When the counting module 5 2 receives the system pulse wave and the logical value of the hidden bit line Q 0 ′ and the data bit line Q i is 1, and the logical value of the data bit line Q fishing is 0, the data bit line Q 妁The logic value will change. When the counting module 5 2 receives the system pulse wave and hides the bit line Q 〇 ′ and the data bit line Q!, Q logical value is 1, and the data bit line Q 妁 logic value is 0, the data bit line The logical value of Q will change. When the counting module 5 2 receives the system pulse wave and hides the bit line Q 〇 ′ and the data bit line Q r Q 2 and Q logic logic values are 1, the counting module 5 2 will output 5 6 A control signal is output, and the control signal is input together with the system pulse and the gate 6 6 causes it to generate a clock signal to the input terminal 5 4 of the counting module 5 8. When the counting module 5 8 receives the clock signal at its input terminal 5 4, the logic value of the hidden bit line Q 4 ′ will change. When the counting module 5 8 receives the clock signal and the logic value of the hidden bit line Q 4 ’is 0, the logic of the data bit line Q

480819 V. Description of the invention (6) The value will change. When the counting module 58 receives the clock signal and the logic value of the hidden bit line Q 4 ′ is 1, and the logic value of the data bit line Q is 0, the logic value of the data bit line Q will change. When the counting module 5 8 receives the clock signal and the logic value of the hidden bit line Q 4 'and the data bit line Q 妁 is 1, and the logic value of the data bit line Q 6 is 0, the data bit line Q fishing The logic value will change. When the counting module 5 8 receives the clock signal and hides the bit line Q 4 'and the data bit line Q 5 and Q, the logical value is about 1 and the data bit line Q 妁 logic value is 0. The data bit line The Q approx logic value will change. It can be seen that the calculation rules of the counting module 58 and the counting module 56 are exactly the same. The data bit line in the counting module 58 can rely on the hidden bit line Q 4 'and all of the counting module 58 only. The logic value of the data bit line lower than the level of the data bit line is used to determine whether to change the logic value of the data bit line without reference to the logic value of the hidden bit line of the lowest order in the counter 50 and all The logic value of the data bit line lower than the rank of the data bit line determines whether to change the logic value of the data bit line. As for the data bit lines in the counting module 58, it is not necessary to refer to the logic values of the hidden bit lines of the lowest order in the counter 50 and the logic values of all data bit lines lower than the rank of the data bit line. The reason for changing the logical value of the data bit line can be further explained by taking the data bit line Q as an example: when the counting module 5 8 receives the clock signal and hides the bit line Q 4 'and the data bit line Q When the fishing logic value is 1, and the data bit line Q hook logic value is 0, the data bit line Q fishing logic value will change. That is, when the logic value of the data bit line Q 7 is changed, the logic value of the hidden bit line Q 4 ′ must be 1, and according to the calculation rule used in this embodiment, the logic of the bit line Q 4 ′ is hidden. value

Page 10 480819 V. Description of the invention (7) When changed, the hidden bit line Q 0 ′ and the data bit line Q Γ Q 2 and Q 妁 in the counting module 5 2 must be 1, and the hidden bit is visible. When the logic value of the line Q 4 ′ is changed to 1, the logic value of the hidden bit line Q G ′ and the data bit lines Q 1, Q 2, Q in the counting module 5 2 must be 1. In addition, as shown in FIG. 7, the data bit line Q and the hidden bit line Q 4 ′ have the same waveform. It can be seen that when the logic value of the hidden bit line Q 4 ′ is 1, the data bit line Q fishing logic value is also Is 1. It can be seen that the data bit line Q does not need to refer to the logic value of the hidden bit line of the lowest order in the counter 50 and the logic value of all data bit lines lower than the data bit line QA to determine whether to change the data bit. Element line Q 妁 logic value. Because when the hidden bit line Q 4 'is 1, the data bit line Q corresponding to the hidden bit line Q 4' in the counter 50 and all data bit lines and the lowest order lower than the data bit line Q The hidden bit lines have a logic value of 1. Therefore, when judging the logical value of the data bit line Q 妁, it is only necessary to know the logical values of the hidden bit line Q 4 'and the data bit lines Q 5, Q. The number of data bit lines of each counting module 5 2, 5 8, 60, 62 of the single bit conversion counter 50 of the present invention can be determined by the circuit designer. Different counting modules cascaded together May contain a different number of data bit lines. In addition, since the gray code has only a single bit conversion at the time of conversion, the gray code counter can also use the modular concept of the single bit conversion counter 50. Different types of counters will cooperate with different As long as the operation rules of the method are used to form a single-bit conversion counter in the form of a cascade counting module, it is within the scope of the present invention.

Page 11 480819 V. Description of the invention (8) Compared with the conventional technology, the single-bit conversion counter 50 of the present invention includes a plurality of modular counting modules 5 2, 5 8, 6 0, 62, When the user wants to increase the data bit line, he only needs to cascade more counting modules after the existing counting module, instead of pulling each successive data bit line to generate subsequent data bits. Line and gate group. Because the number of AND gates in each counting module is very limited, the circuit is very simple. When the counter 50 has many data bit lines, increasing the counting modulus will not significantly increase the power consumption. In this way, the counter 50 can not only save The power consumption can also be quickly calculated. Therefore, the single-bit conversion counter 50 can meet the requirements of today's high-speed operations while reducing power consumption. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

Page 12 480819 Brief description of the diagram Brief description of the diagram Figure 1 is a logic circuit diagram of a conventional single-bit conversion counter used to generate the logical value conversion of the first data bit line. FIG. 2 is a logic circuit diagram of the single-bit conversion counter used to generate the logical value conversion of the second data bit line in FIG. Figures 3A and 3B are logic circuit diagrams of the single-bit conversion counter used to generate the logical value conversion of the third data bit line in FIG. FIG. 4 is a logic circuit diagram of the single-bit conversion counter used in FIG. 1 to generate the logical value conversion of the one hundredth data bit line. Figure 5 is a logic value table of the data bit lines of a single bit conversion counter in Figure 1. FIG. 6 is a partial circuit diagram of the single-bit conversion counter of the present invention. FIG. 7 is a timing diagram of the single-bit conversion counter of FIG. Explanation of symbols in the figure 5 0 Single bit conversion counter 51 System clock 52, 58, 60, 62 Counting module 6 4, 6 6 and gate

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Claims (1)

480819 6. Scope of patent application 1-a single transition counter, which is used to convert only a single bit within the time, which includes • at least one counting module, which includes an input Terminal for inputting the clock signal y and an output terminal for outputting the control signal. The counting module includes • a barrier 1 hidden bit line () invisible bit line, which is received by the counting module when it is received. The pulse signal will change its logic value; and at least the data bit line, wherein when the data bit line receives the clock signal and the logic value of the hidden bit line and the internal ratio of the counting module When the logical value of the data bit line with a lower rank of the material bit line matches a predetermined first operation rule, the logical value of the data bit line is changed. 9 When the logic of the barrier \ Tibetan bit line Value and each non-most significant element in the data bit line Logic value of a bit line and the second predetermined operation rule of the J group can count its analog output terminal of a phase control signal identifier. 2. As mentioned in the patent application, the single-bit conversion counter in item 1 of the patent, which includes a plurality of analog-to-digital modules, is connected in a cascade (c a s c a d e) manner. 3. For example, please request a single bit conversion counter for item 2 of the target range / Γ. Among the two connected counting modules, the control signal output by the previous counting module is used to generate the lower counting module. Clock signal. Page 14 480819 6. Scope of patent application 4. The single-bit conversion counter of item 1 of the patent application scope also includes a system clock, which is used to generate system pulses to control the sequence operation of the counter. 5. If the single-bit conversion counter in item 1 of the patent application scope is a gray code counter. ’ Page 15