469593 A7 〜----------B7 五、發明説明（/)—" -- 技術領域： 本發明係有關於半導體元件之製程，特別地是有關於一 種用以在閘極結構之間形成—自行對準接觸窗結構，以暴露 出半導體基板中之導電區的方法。 發明背景： 經濟部智慧財產局員工消費合作社印製 目前藉由縮減半導體最小線寬尺寸，以增加裝置性能的 半導體產業之目的早已進展中，然而，相較於使用較大尺寸 所製造之組件，其將產生較小的導電區域，而具有降低的寄 生接面電容值’以及較低的性能劣化電阻電容（RC)值。藉 由若干半導體製造範疇（諸如光學微影及乾式蝕刻）的進展， 此已被完成。更複雜之曝光照相機的使用以及更敏感之光阻 層的使用已經允許次四分之二微米特徵被形成於光阻層中。 此外，更先進的乾式餘刻設備及製程的開發已經允許光阻層 中的次四分之一微采特徵被轉置於半導體裝置製造中所使用 的其他材料。然而，除了製造範疇的進展外，結構上的創新 亦已允許次四分之一微求特徵的達成被實現。例如自行對準 接觸（開口與結構被形成於金屬氧化半導體場效電晶體 (MOSFET)裝置的閘極結構之間）已經允許閘極結構之間 的間隔被縮減。該自行對準接觸窗開口完全允許所安置的接 觸窗結構’而被形成於該自行對準接觸窗開口中，而與閘極 結構之間的底層導電性區域（位於該間隔中，寬度較自行對 準接觸開口的直徑小）接觸。而在未形成自行對準接觸窗開 口之情況下，則必須使用較大的導電區域於閘;1¾結構之間， ______ 本紙張尺度適用中固國家棣準< CNS M4规格（210X297公釐} 469593 經濟部智慧財產局員工消費合作社印製 A7 一 " -—^— --------B7 五、發明説明（>) — ----— =確保能完全置備其上層結構。該自行對準接_開口的完 係㈣形成—解電_ (諸如應FET _極/汲極區） ;閘極1構的^_中，接著形成自行^_準接觸窗開口（較 ^極結構之間的間隔為幻，而暴露位於閘減構之間的導電 區出後續的自行對準接觸窗結構（形成於自行對準接觸窗 開口中）接著觀全設置於該底層導紐㈣上。如此新穎 的方法無需較大的輯，以確縣完全安置結構的接觸孔開 口。然而’為了使自行解_峨念能触功，無針孔現 象的絕緣體間隙壁必須被形成於該閘極結構的邊緣，以避免 該自行對準接觸結構（位於自行對準接觸開口中）與閘極結 構之間的漏電流與短路現象。 為此’本發明將說明一種用於形成複合間隙壁於該閘極 結構邊緣的新穎製程，其中該複合間隙壁之底層組件中，可 能的缺陷或針孔現象係以非導電性之該複合間隙壁之下層組 件覆蓋，因而避免基板（自行對準接觸窗結構下的導電區域） 發生自行對準接觸窗結構所引起閘極短路（自行對準接觸窗 結構所引起）的風險。諸如美國專利第6，〇33，962號（Jeng 等人）之習知技藝說明一種形成一絕緣體間隙壁於閘極結構 邊緣上之用於自行對準接觸結構的方法，然而該習知技藝並 未說明本發明中所述之用於形成複合間隙壁的製程，該複合 間隙壁的特徵在於自行對準接觸結構所使用之非導電性的上 層間隙壁組件。‘ 本紙張尺度遥用中國國家橾车（CHS ) Μ規格（210X297公釐） (請先閲讀背面之注意事項^:填寫本頁) •裝.469593 A7 ~ ---------- B7 V. Description of the Invention (/)-"-Technical Field: The present invention relates to the manufacturing process of semiconductor devices, and in particular, to a method for controlling a gate electrode. Formation between structures-A method of self-aligning a contact window structure to expose conductive regions in a semiconductor substrate. Background of the Invention: The printing of consumer cooperatives by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs is currently progressing by reducing the minimum line width of semiconductors to increase the performance of the semiconductor industry. However, compared to components manufactured using larger sizes, It will result in a smaller conductive area with reduced parasitic junction capacitance value 'and lower performance degradation resistance capacitance (RC) value. This has been accomplished through advances in several semiconductor manufacturing areas such as optical lithography and dry etching. The use of more sophisticated exposure cameras and the use of more sensitive photoresist layers has allowed features in the second-quarter micron feature to be formed in the photoresist layer. In addition, the development of more advanced dry-etching equipment and processes has allowed second-quarter micro-picked features in photoresist layers to be transferred to other materials used in semiconductor device manufacturing. However, in addition to progress in manufacturing, structural innovations have also allowed the realization of sub-quarter microfinding features. For example, self-aligned contacts (openings and structures formed between the gate structures of a metal oxide semiconductor field effect transistor (MOSFET) device) have allowed the gap between gate structures to be reduced. The self-aligned contact window opening completely allows the disposed contact window structure to be formed in the self-aligned contact window opening, and the bottom conductive region (located in the gap, which is more Align the contact opening with a small diameter) contact. In the case where the self-aligned contact window opening is not formed, a larger conductive area must be used between the gates; 1¾ between the structures, ______ This paper size applies to the China Solid State Standards < CNS M4 specifications (210X297 mm) 469593 A7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs "--^--------- B7 V. Description of the invention (>)--------- = ensure that its upper structure can be fully prepared The complete alignment of the self-aligned _ opening is formed-de-energized (such as the FET _ pole / drain region); in the gate structure, the self-aligned quasi-contact window opening (more ^ The spacing between the pole structures is magical, and the conductive area between the gate reduction structures is exposed to the subsequent self-aligning contact window structure (formed in the self-aligning contact window opening). This novel method does not require a large compilation to ensure that the contact hole openings of the structure are fully installed in the county. However, 'in order to solve the problem _ Anian can work, an insulator gap wall without pinholes must be formed in the gate Edge of the pole structure to avoid this self-aligning contact structure (located Self-align the leakage current and short-circuit phenomenon between the contact opening) and the gate structure. To this end, the present invention will describe a novel process for forming a composite gap wall on the edge of the gate structure. In the underlying component, possible defects or pinholes are covered by the non-conductive component below the composite gap wall, thus avoiding the substrate (self-aligning the conductive area under the contact window structure) caused by self-aligning the contact window structure. The risk of a gate short circuit (caused by self-alignment of the contact window structure). Known techniques such as US Pat. No. 6,033,962 (Jeng et al.) Describe the formation of an insulator gap on the edge of the gate structure. A method for self-aligning a contact structure, however, the conventional technique does not explain the process for forming a composite spacer wall described in the present invention, which is characterized by the non-conductive used for self-aligning the contact structure The upper partition wall component. 'This paper size is used in China's national car (CHS) M specifications (210X297 mm) (Please read the notes on the back first (Item ^: Fill out this page)
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A7 B7 469 593 五、發明説明（j) 發明概要： 本發明之主要目的在於提出一種於半導體基板上形成 自行對準接觸窗結構的方法，關於使M0SFET裝置能被使用 於動態隨機存取記憶體（DRAM)以及靜態隨機存取記憶體 (SRAM)單元。 本發明之另一個目的在於提出一種於半導體基板上形 成自行對準接觸窗結構的方法，特別係在於形成複合間隙壁 於該MOSFET裝置之閘極結構邊緣上。 本發明之又一個目的為提出一種於半導體基板上形成 自行對準接觸窗結構的方法，係在於所形成的複合間隙壁包 含有一底層氮彳匕石夕以及一上層未摻雜或非晶相的矽化合物所 組成。 本發明之再一個目的為提出一種於半導體基板上形成 自行對準接觸窗賴的方法’係在於形成-導紐自行對準 接觸結構於位在閘極結構之間的自行對準接觸窗開口中，其 中該自行對準接觸結構與該複合間隙壁的未摻雜或非晶石夕間 隙壁化合物連接《 經 濟 部 智： 慧 財 產 局 員 工 m 費 合 作 社 印 製 為達上述之目的，本發0⑽、提供—齡半導縣板上形成自 行對準接«結構的方法，尤其是—細彡成自行對準接觸窗 開口以及位於MOSFET裝置之閘極結構之_自行對準接 觸結構的綠。其特徵在於複合間随位於關極結構邊 緣’並包含一未摻雜或非晶石夕上層嶋壁化合物。於半導體 基板上形雜#雜_版赌紅後，麟碱減化吩所 覆蓋的閘極結構。在-氮⑽層以及_上層未雜或非晶石夕 本紙張从14财關家轉（⑽ 經濟部智慧財產局員工消费合作社印製 6 9 5 9 3 A7 —_______ B7 五、發明説明（/ ) 層沈積後’以非等向性乾式银刻製程，形成複合間隙壁於該 被氮化矽覆蓋的閘極結構邊緣上。特徵在於該上層未摻雜或 非晶石夕間隙壁化合物’將填入底層氣化物間隙壁化合物中的 缺陷或針孔現象。接著在未為被氮化矽覆蓋之閘極結構，或 未於被亂化梦覆蓋之閘極結構上的複合間隙壁所覆蓋之半導 體基板的區域，形成重摻雜源極/汲極區域之後，沈積氧化 矽》接著形成一個自行對準接觸窗開口於氧化矽層中，其中 該自行對準接觸窗開口將暴露出之寬度係位於被氮化矽覆蓋 之閘極結構間的重摻雜源極/汲極區域，以及暴露出位於被氬 化矽覆蓋之閘極結構邊緣上的複合間隙壁。接著沈積導電材 料’如摻雜複晶矽、鎢，並進行化學機械研磨(CMp)，因而 形成自行對準接觸結構，或導電性自行對準接觸插塞於自行 對準接觸窗口中。其中該自行對準接觸結構將完全置於底層 之重摻雜源極/汲極區域上’並與位於被氮化矽覆蓋之閘極結 構邊緣上的複合間隙壁連接。 圖式之簡要說明： 本發明之目的及其他優點將參考附圖而於較佳實施例 中作最佳的說明，含有： 圖1〜5係為本發明之主要目的在於提出一種於半導體 基板上形成自行對準接觸窗結構的方法之較佳實施示意圖， 說明形成自行對準接觸結構於位在閘極結構間之自行對準接 觸窗開口中的主要製程，其中該閘極結構包含有複合間隙 壁’其特徵在於一上唐未掺雜或非晶;5夕間隙壁。 ----------參-------1T-----1^ . ί ^ (请先閱讀背面之注意事乎4填寫本頁) 本紙張朝 Hi家料^ CNS ) ( 2iG>^297公釐)^' 469593 A7 --――------B7 五、發明説明（y ) ~ --- 圖號說明： 1- P型半導體基板 2- 閘極氧化層 3- 複晶石夕層或金屬碎化物層 4- 氮化矽層 5_閘極結構 6a-氮化矽層 6b-氮化矽間隙壁 7a-未摻雜複晶矽或非晶矽層 7b-未摻雜複晶矽或非晶矽間隙壁 8- 重摻雜源極/汲極區域 9- 氧化矽層 10- 自行對準接觸窗口 · 11- 自行對準接觸結構 20-隔離區 30-重摻雜區 發明之詳細步驟： 經濟部智慧財產局員工消費合作社印製 本發明主要係為在閘極結構間之自行對準接觸窗開口 中’形成一自行對準接觸結構的方法。其中該閘極結構包含 有複合間隙壁’特徵在於上層間隙壁由未摻雜或非晶石夕所組 成。本發明係以NCHANNEL之MOSFET元件說明，但亦可 被應用於PCHANNEL MOSFET元件。本發明中所說明的複 合間隙壁可被應用於所有的MOSFET元件，諸如DRAM、 本紙張尺度適用中菌國家榇準（CNS ) A4規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 469593 A7 .. _ B7 五、發明説明（t ) SRAM或其他類型之邏輯或記憶單元的mqsfet裝置。 圖一為一 P型半導體基板1，該P形半導體基板丨由具 有<100〉結晶方向之單晶矽所組成，首先形成以絕緣物填充 隔離區20 ’如淺溝渠隔離（STI)或熱成長場氧化層（F〇x)， 在氧乳氣氛中熱成長形成一閘氧化層2，其厚度在5〇至1〇〇 埃之間。接著形成一氮化矽覆蓋之閘極結構5於該閘氧化層 2上。此步驟藉著低廢化學氣相沈積（LPCVD) —複晶矽層 或金屬矽化物層3，如矽化鎢，其厚度在1〇〇〇至3〇〇〇埃之 間。然如果是金屬矽化物層3可由下層複晶矽與上層金屬矽 化層所組成；而複晶矽層3可藉由添加砷或磷至矽烷氣氛 中’而於沈積期間動態地摻雜’或者複晶矽層3可本質地沈 積，並接著藉由砷或磷離子的植入摻雜。在複晶矽層或金屬 矽化物層3沈積後，藉由低麈化學氣相沈積或電漿辅助化學 氣相沈積(PECVD)沈積一氮化矽層4，其厚度在300至15〇〇 埃之間。 接著以一光阻（圖中未式）為蝕刻罩幕，藉由非等向性 活性離子银刻（RIE)製程形成被氮化矽覆蓋的閘極結構5， 其中該非等向性活性離子蝕刻係使用CF4或CHF3作為氤化 矽層4的蝕刻劑，而使用C12或SR作為複晶矽層或金屬矽化 物層3的蝕刻劑。該被氮化矽覆蓋之閘極結構5的寬度在〇j5 至〇.2〇微米之間’其將造成在源極/没極區域形成後，被氮化 矽覆蓋之閘極結構5下方的通道長度低於〇1〇微米。藉由電 聚氧氣灰化及濕式清洗移除用於定義被氮化矽覆蓋之閘極結 構5的光阻’而藉由濕式清洗製程的缓衝氬氟酸循環，將未 ---------Ί裝------訂------線 ί ( (請先閲讀背面之注意事填寫本頁) 469593 A7 ___B7 五、發明説明（，） " " - 為被ii化⑦覆蓋之閑極結構5所覆蓋的二氧化^^極絕緣層 2。1^刀移除。接著形成輕摻雜的源極/汲極區域邓（用於諸如 SRAM之特定單元巾的元件）在未為被氮化树蓋層 閘極結 構5所覆蓋的半導體基板i區域中，其係藉由能量約3〇至 70 KeV間之砷或磷的植入，植入劑量在ιΕι3至1拉4 atoms/cm2 之間。 經濟部智慧財產局員工消費合作社印製 接著說明形成間隙壁於被氮化矽覆蓋之閘極結構5邊 緣上。因為一自行對準接觸窗口於後續選擇性地形成於一氧 化矽層中，以將位於閘極結構之間的導電性源極^及極區域暴 露出，該間隙壁必須自氧化石夕以外的材料形成，以確保該自 行對準接觸窗口製程的選擇性。如前所述，習知技藝係使用 氮化矽作為間隙壁材料，以允許一自行對準接觸窗口形成於 氮化矽覆蓋之閘極結構間的氧化石夕層中，其特徵在於閘極結 構邊緣上的氮化矽間隙壁。然而，諸如針孔等在氮化矽間隙 壁中的缺陷將允許位於自行對準接觸窗口中的後續導電性自 行對準接觸結構與閘極結構接觸，而造成不希望之閘極至基 板的漏電流或短路。因此，本發明的特徵在於一種複合間隙 壁，其係由一個底層氮化矽層以及一非導電性之未摻雜複晶 矽或非晶矽上層間隙壁所組成。因此，若針孔現象確實存在 於底層氮化矽間隙壁組件中，則上層間隙壁的未摻雜矽將以 一非導電性材料將該缺陷或針孔填充，因而降低之閘極至基 板的漏電流或短路的風險。因此，一個氮化矽層齟首先藉由 低壓化學氣相沈積或電漿輔助化學氣相沈積製程而被沈積達 約50至500埃之間的厚度，接著藉由低壓化學氣相沈積製程 本紙張適用巾( CNS ) A4j^ ( 21。】297公着j * - 469593 A7 _________B7 五、發明説) 沈積一個未摻雜複晶矽或非晶質矽層7a達約50至200埃之 間的厚度，如圖2所示。 、接著進行非等向性活性離子蝕刻，其係使用Cl2或Sf6 作為未掺雜複晶石夕或非晶石夕層7a的姓刻，而使用CF4或 作為氮化矽層6a的蝕刻劑，而產生位於氮化矽覆蓋層之閘極 結構5邊緣的複合間隙壁，該複合間隙壁係由上層的未換雜 複晶石夕或非晶石夕間隙壁7b以及底層的氮化石夕間隙壁隙壁奶 所組成。此係示意地表示於第3圖中。重摻雜源極/没極區域 8接著形成於未為被氮化石夕覆蓋之閘極結構5，或未為置於被 氮化矽覆蓋之閘極結構5上的複合間隙壁所覆蓋之半導體基 板1的區域中。重摻雜源極/汲極區域8係藉由植入神或鱗離 子而被形成，其能量在約40至80 KeV之間，劑量在約1E14 至1E15 atoms/cm2之間’楂入角度在約0至7〇度之間。該低 植入角度為重要的，以限制離子不會損傷未摻雜複晶矽或非 晶矽間隙壁7b的本身。 經濟部智慧財產局員工消費合作社印製 接著以低壓化學氣相沈積或電漿辅助化學氣相沈積一 氧化石夕層9 ’其厚度達約3000至12000埃之間，其係使用四 乙烷矽甲烷（TEOS)作為來源。接著進行化學機械研磨 (CMP)’而產生平坦表面的氧化矽層9 ^ 一作為蝕刻罩幕之 光阻（未示於圖式中），以使用CHF3作為氮化矽的蝕刻劑， 而選擇性地形成自行對準接觸窗口 1〇於氧化矽層9 ^相對 於未摻雜複晶矽或氮化矽的較低蝕刻速率，氧化麥的較高姓 刻速率將使自行對準接觸窗口 10選擇性地形成。在被氮化梦 覆蓋層之閘極結構5 (包含有複合間隙壁）之間的間隔約在 本紙&尺度逋用中國國家標率「CNS } A4規格（210二297公釐〉 469593 經濟部智慧財產局員工消贫合作社印製 A7 B7 五、發明説明（，） 001至〇.10微米之間，而自行對準接觸窗口 10係以約0.01 至0.1微来之間的直徑被形成。被使用以形成自行對準接觸 窗口 10之罩幕的光阻接著使用氧氣灰化以及的濕式清洗而 被移除，如圖4所示。 第5圖中所示意表示之自行對準接觸結構u接著被形 成於自行對準接觸窗口 10中。一個諸如鎮、石夕化鶴或摻雜複 晶石夕的導電層’藉由低壓化學氣相沈積製程而被沈積達約 1000至5000埃之間的厚度，而將自行對準接觸窗口 10完全 填充°部分的導電層接著藉由化學機械研磨，或藉由選擇性 活性離子钱刻製程（使用Cl2或SF6作為該導電層的蝕刻 劑）’而由氧化矽層9的頂端表面被移除，因而形成自行對準 接觸結構11於自行對準接觸窗口 10中。自行對準接觸結構 11完全置於重摻雜源極/沒極區域8上，並與未接雜複晶矽或 非晶質碎間隙壁組件7b連接。以未摻雜複晶碎或非晶石夕將氮 化石夕間隙壁組件6b中的缺陷或針孔填充或密封的能力將消 除導電性自行對準接觸結構11連接至被氮化矽覆蓋層之閘 極結構5的導電區域的風險，因而避免閘極至基板的短路或 漏電流》 以上係針對本發明之較佳實例作詳細敘述，而非限制本 發明的範圍，而且對熟知此技術領域人士而言，當可在不脫 離本發明要義的情況下，作適當而細微的改變與調整，惟此 等皆應視為本發明之進一步實施狀況 本紙張尺度適用中國國家標牟（CNS) M規格（21〇χ297公釐） - II 裝 訂 i A . , / Μ <請先閲讀背面之注意事項再填寫各莨), TT line. A7 B7 469 593 V. Description of the invention (j) Summary of the invention: The main purpose of the present invention is to propose a method for forming a self-aligned contact window structure on a semiconductor substrate. With regard to enabling MOSFET devices to be used in dynamic random Access Memory (DRAM) and Static Random Access Memory (SRAM) cells. Another object of the present invention is to provide a method for forming a self-aligned contact window structure on a semiconductor substrate, in particular to form a composite gap wall on an edge of a gate structure of the MOSFET device. Yet another object of the present invention is to provide a method for forming a self-aligned contact window structure on a semiconductor substrate. The formed composite spacer wall includes a bottom layer of nitrogen dagger and an upper layer of undoped or amorphous phase. Composed of silicon compounds. Another object of the present invention is to propose a method for forming a self-aligned contact window on a semiconductor substrate. The method is to form a self-aligned contact structure of a guide in a self-aligned contact window opening located between gate structures. , Where the self-aligned contact structure is connected with the undoped or amorphous stone spacer compound of the composite spacer. "Ministry of Economics: Intellectual Property Bureau employee m. Fei Cooperative printed to achieve the above purpose, this issue 0⑽, Provides a method for forming self-aligned contact structures on the old semi-conducting board, in particular, the self-aligned contact window opening and the green of the self-aligned contact structure located in the gate structure of the MOSFET device. It is characterized in that the recombination space is located at the edge of the gate structure 'and contains an undoped or amorphous stone upper wall compound. After the shape of the impurity on the semiconductor substrate was changed, the base structure covered by phenanthrene was reduced. In the -nitrogen layer and _ upper layer of unmixed or amorphous stone paper, transferred from 14 Choi Kwan House (⑽ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6 9 5 9 3 A7 —_______ B7 V. Description of the invention (/ ) After the layer is deposited, a non-isotropic dry silver engraving process is used to form a composite spacer on the edge of the gate structure covered by silicon nitride. The feature is that the upper layer of undoped or amorphous stone spacer compound will Defects or pinholes in the bottom gaseous spacer compound are filled in. Then the composite spacers on the gate structure not covered by silicon nitride or on the gate structure covered by chaotic dreams After the heavily doped source / drain region is formed on the semiconductor substrate, a silicon oxide is deposited. A self-aligned contact window opening is then formed in the silicon oxide layer, wherein the width of the self-aligned contact window opening will be exposed. The heavily doped source / drain regions between the gate structures covered by silicon nitride, and the composite spacers on the edges of the gate structures covered by silicon argon are exposed. Then a conductive material such as doped is deposited Compound , Tungsten, and chemical mechanical polishing (CMp), thereby forming a self-aligning contact structure, or a conductive self-aligning contact plug in a self-aligning contact window. The self-aligning contact structure will be completely placed on the bottom layer. It is heavily doped on the source / drain region and is connected to a composite spacer on the edge of the gate structure covered by silicon nitride. Brief description of the drawings: The purpose and other advantages of the present invention will be described with reference to the drawings. The best description in the preferred embodiment includes: Figures 1 to 5 are schematic diagrams of the main purpose of the present invention to propose a method for forming a self-aligned contact window structure on a semiconductor substrate, illustrating the formation of a self-aligned pair. The main process of the quasi-contact structure in the self-aligned contact window openings located between the gate structures, wherein the gate structure includes a composite spacer wall, which is characterized by an undoped or amorphous upper wall; ---------- Refer to ------- 1T ----- 1 ^. Ί ^ (Please read the note on the back first and fill out this page) This paper faces Hi ^ CNS) (2iG > ^ 297mm) ^ '469593 A7 ------------ B7 V. Description (y) ~ --- Drawing number description: 1- P type semiconductor substrate 2- gate oxide layer 3- polycrystalline stone layer or metal fragment layer 4- silicon nitride layer 5_ gate structure 6a- Silicon nitride layer 6b-silicon nitride spacer 7a- undoped polycrystalline or amorphous silicon layer 7b- undoped polycrystalline or amorphous silicon spacer 8- heavily doped source / drain region 9 -Silicon oxide layer 10- Self-aligning contact window · 11- Self-aligning contact structure 20- Isolation zone 30- Heavily doped zone Detailed steps of invention: Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economics A method of forming a self-aligning contact structure in a self-aligning contact window opening between gate structures. The gate structure includes a composite barrier wall ', which is characterized in that the upper barrier wall is composed of undoped or amorphous stone. The present invention has been described using NCHANNEL MOSFET elements, but it can also be applied to PCHANNEL MOSFET elements. The composite spacer described in the present invention can be applied to all MOSFET components, such as DRAM, this paper size is applicable to the Chinese National Standard for Microorganisms (CNS) A4 specification (210X297 mm) printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 469593 A7 .. _ B7 V. Description of the invention (t) mqsfet device of SRAM or other types of logic or memory unit. FIG. 1 is a P-type semiconductor substrate 1. The P-shaped semiconductor substrate 丨 is composed of single crystal silicon with a crystal orientation of <100>. First, an isolation region 20 'is filled with an insulator, such as shallow trench isolation (STI) or thermal insulation. The growth field oxide layer (Fox) is thermally grown in an oxygen emulsion atmosphere to form a gate oxide layer 2 having a thickness between 50 and 100 angstroms. A gate structure 5 covered with silicon nitride is then formed on the gate oxide layer 2. This step is performed by low waste chemical vapor deposition (LPCVD)-a polycrystalline silicon layer or a metal silicide layer 3, such as tungsten silicide, with a thickness between 1000 and 3000 angstroms. However, if it is a metal silicide layer 3, it can be composed of a lower polycrystalline silicon layer and an upper metal silicide layer; and the polycrystalline silicon layer 3 can be dynamically doped during deposition or added by adding arsenic or phosphorus to the silane atmosphere. The crystalline silicon layer 3 may be deposited substantially and then doped by implantation of arsenic or phosphorus ions. After the polycrystalline silicon layer or the metal silicide layer 3 is deposited, a silicon nitride layer 4 is deposited by low hafnium chemical vapor deposition or plasma-assisted chemical vapor deposition (PECVD) to a thickness of 300 to 1 500 Angstroms. between. Next, a photoresist (not shown in the figure) is used as an etching mask, and a gate structure 5 covered with silicon nitride is formed by an anisotropic active ion silver etching (RIE) process, wherein the anisotropic active ion etching CF4 or CHF3 is used as an etchant for the silicided silicon layer 4, and C12 or SR is used as an etchant for the polycrystalline silicon layer or the metal silicide layer 3. The width of the gate structure 5 covered by silicon nitride is between 0 μ5 and 0.20 μm. This will cause the gate structure 5 under the gate structure 5 covered by silicon nitride to form after the source / dead region is formed. The channel length is below 010 microns. By using polyoxygen ashing and wet cleaning to remove the photoresist used to define the gate structure 5 covered by silicon nitride, and through the buffered argon-fluoric acid cycle of the wet cleaning process, the --- ------ Outfit ------ Order ------ Line ί ((Please read the notes on the back and fill out this page first) 469593 A7 ___B7 V. Description of the Invention (,) " " -Dioxide ^ electrode insulation layer 2 covered by the free electrode structure 5 covered by fluorene, and then removed by a knife. Then lightly doped source / drain regions are formed (for specific applications such as SRAM) Element of the unit towel) In the area of the semiconductor substrate i which is not covered by the nitrided tree capping gate structure 5, it is implanted by implantation of arsenic or phosphorus with an energy of about 30 to 70 KeV. Between ιΕι and 1 to 4 atoms / cm2. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and then explain the formation of a gap wall on the edge of the gate structure 5 covered by silicon nitride. Because a self-aligned contact window will follow It is selectively formed in the silicon oxide layer to expose the conductive source electrode and the electrode region between the gate structures. Materials other than fossils are formed to ensure the selectivity of the self-aligned contact window process. As mentioned earlier, the conventional technique uses silicon nitride as the spacer material to allow a self-aligned contact window to be formed on the nitride. The silicon oxide oxide layer between the gate structures covered by silicon is characterized by a silicon nitride spacer on the edge of the gate structure. However, defects such as pinholes in the silicon nitride spacer will allow self-alignment Subsequent conductivity in the contact window is self-aligned and the contact structure contacts the gate structure, resulting in an undesired gate-to-substrate leakage current or short circuit. Therefore, the present invention is characterized by a composite gap wall, which is composed of a bottom layer It is composed of a silicon nitride layer and a non-conductive undoped polycrystalline silicon or amorphous silicon upper spacer. Therefore, if the pinhole phenomenon does exist in the bottom silicon nitride spacer, the upper spacer Doped silicon will fill the defect or pinhole with a non-conductive material, thereby reducing the risk of gate leakage to the substrate or the risk of short circuit. Therefore, a silicon nitride layer Low pressure chemical vapor deposition or plasma-assisted chemical vapor deposition processes are deposited to a thickness of about 50 to 500 angstroms, and then the paper is suitable for paper towels (CNS) A4j ^ (21.) by low pressure chemical vapor deposition processes. 297 J *-469593 A7 _________B7 V. Invention) Deposition of an undoped polycrystalline silicon or amorphous silicon layer 7a to a thickness of about 50 to 200 Angstroms, as shown in Figure 2. Isotropic reactive ion etching uses Cl2 or Sf6 as the last name of the undoped polycrystalline or amorphous stone layer 7a, and uses CF4 or as an etchant for the silicon nitride layer 6a, resulting in nitrogen Compound gap on the edge of the gate structure 5 of the silicon cover layer. The compound gap is composed of the unsubstituted doped polycrystalline or amorphous stone gap 7b in the upper layer and the nitrided stone gap wall milk in the bottom layer. composition. This is shown schematically in Figure 3. The heavily doped source / dead region 8 is then formed on a semiconductor structure 5 that is not covered by a nitride stone, or a semiconductor that is not covered by a composite spacer placed on the gate structure 5 that is covered by silicon nitride. In the region of the substrate 1. The heavily doped source / drain region 8 is formed by implanting god or squamous ions. Its energy is between about 40 and 80 KeV, and the dose is between about 1E14 and 1E15 atoms / cm2. About 0 to 70 degrees. This low implantation angle is important so that the ions do not damage the undoped polycrystalline silicon or the amorphous silicon spacer 7b itself. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, followed by low-pressure chemical vapor deposition or plasma-assisted chemical vapor deposition of the oxide layer 9 'with a thickness of about 3000 to 12000 Angstroms, which uses tetraethane silicon Methane (TEOS) as a source. Then chemical mechanical polishing (CMP) 'is performed to produce a flat silicon oxide layer 9 ^ a photoresist (not shown in the figure) as an etching mask, using CHF3 as an etchant for silicon nitride, and selective Ground self-aligning contact window 10 on silicon oxide layer 9 ^ Compared to undoped polycrystalline silicon or silicon nitride, the lower the etch rate, the higher the etch rate of the oxide will make the self-aligning contact window 10 select Sexually formed. The gap between the gate structure 5 (including the composite spacer wall) covered by the nitrided dream is about the paper & scale, using the Chinese national standard "CNS} A4 specification (210-2297mm> 469593 Ministry of Economic Affairs Printed by A7 B7 of the Intellectual Property Bureau's Anti-Poverty Cooperative V. Invention Description (,) 001 to 0.10 micron, and the self-aligned contact window 10 is formed with a diameter of about 0.01 to 0.1 micron. The photoresist used to form the mask of the self-aligning contact window 10 is then removed using oxygen ashing and wet cleaning, as shown in Fig. 4. The self-aligning contact structure u shown schematically in Fig. 5 It is then formed in the self-aligning contact window 10. A conductive layer such as a town, a safflower crane or a doped polyspar slab 'is deposited between about 1000 and 5000 angstroms by a low pressure chemical vapor deposition process. And the self-aligned contact window 10 is completely filled with a part of the conductive layer, and then is subjected to chemical mechanical polishing, or through a selective active ion etching process (using Cl2 or SF6 as an etchant for the conductive layer) ' Top of silicon oxide layer 9 The surface is removed, thereby forming a self-aligned contact structure 11 in the self-aligned contact window 10. The self-aligned contact structure 11 is completely placed on the heavily doped source / dead region 8 and is un-doped with a polycrystalline Silicon or amorphous broken spacer components 7b are connected. The ability to fill or seal defects or pinholes in the nitride spacer components 6b with undoped polycrystalline fragments or amorphous stones will eliminate conductivity self-alignment The risk that the contact structure 11 is connected to the conductive region of the gate structure 5 covered by silicon nitride, thus avoiding a short circuit or leakage current from the gate to the substrate. The above is a detailed description of the preferred embodiment of the present invention, but not a limitation. The scope of the present invention, and for those skilled in the art, appropriate and subtle changes and adjustments can be made without departing from the gist of the present invention, but these should be considered as further implementation status of the present invention. Paper size applies to China National Standards (CNS) M specification (21〇297mm)-II Binding i A., / Μ < Please read the notes on the back before filling in each note)