TW441101B - Method of forming dynamic random access memory with capacitor over bit line - Google Patents

Abstract

This invention is about the method that uses self-aligned contact window manner to fabricate dynamic random access memory (DRAM) with capacitor over bit line. In this invention, a self-aligned contact (SAC) window is opened in between bit lines to punch through silicon oxide layer. In particularly, the silicon oxide spacer is formed at the sidewall of bit line structure and the formation of spacer is performed after the opening of SAC window. The punching through in between bit lines for self-aligned contact window can make the integration density of DRAM increase. The spacer of bit line structure is formed after the SAC window is opened such that the spacer can use silicon oxide as the material. Therefore, smaller coupling capacitance can be obtained as compared with that of DRAM device, which uses silicon nitride as the spacer.

Description

4 41 10 1 A7 _._ B7 V. Description of the Invention (I) Field of the Invention: The present invention relates to a method for forming a semiconductor element, and more particularly to a method for forming a dynamic random access memory with a bit line capacitor on a semiconductor substrate Memory, cell method. ......... Stomach background: .............................. ..... In order to obtain the maximum density of dynamic random access memory (Dynamic Random Access Memory)

Random Access Memory (DRAM), a capacitor over bitline (COB) designed for high-density density chip chips has been widely used in the industry. The traditional method of forming a COB structure is to first open a bit line structure, and then form a dielectric spacer on the side wall of the bit line structure. Subsequently, a self-aligned contact (SAC) window is opened on the first dielectric layer, and the window is opened to penetrate the first dielectric layer between the bit lines to expose the conductive plug of the lower layer. Plug (Conductive Plug). This conductive plug is located above the source / drain region and is used to connect the semiconductor substrate and the capacitor structure above it. However, before the SAC window is opened on the silicon oxide layer after the sidewall spacers of the bit line structure are formed, silicon nitride (Silicon Nitride) must be selected as the material of the above spacers. Silicon nitride and silicon oxide ( Silicon Oxide) high etching selectivity ratio to perform the dry etching step of SAC. However, the dielectric constant of nitrided cleavage (Dielectric_Constant) is much higher than that of silicon oxide, and the formation of the barrier wall will increase the mold value. Because of the low surface, mia recalls the abdomen and mouth quality. .... This invention describes a SAC window used on a DRAM to connect source / drain regions. The window is opened between bit lines and penetrates through two sheets of paper. The dimensions are applicable to the Chinese National Standard CCNS) A4 specification (210 X 297 mm) (Please read the precautions for --t- .. and then fill out this page) Installation -------- Order ----- ----- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 41 10 1 A7 __ _B7__ V. Description of the Invention (>) Electrical layer, however, it is different from the know-how Yes, the process of opening the SAC window of the present invention is before the formation of the dielectric spacer on the sidewall of the bit line structure. Therefore, in the present invention, silicon oxide can be selected as the material of the gap wall of the bit line structure, so that the coupling capacitance between the bit line and the capacitor can be greatly reduced than that of the silicon nitride gap wall. Furthermore, because the spacer is formed after the SAC window is opened, any damage to the spacer that may be caused by the etching process when the SAC window is opened will not occur. In this way, a thinner partition wall can be used, and a narrower SAC window can also be designed in the layout, which can further increase the density of the accumulation. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for forming a dynamic random access memory with a capacitor structure on a bit line. The secondary purpose of the present invention is to form a window in the silicon oxide layer that automatically aligns with the contact window. The window is opened between the bit lines and penetrates the silicon oxide layer. The opening process of the SAC window is in the formation position. Before the dielectric spacers on the side wall of the element structure. Another object of the present invention is to provide a method for forming a silicon oxide spacer on a sidewall of a bit line structure, and the formation of the spacer is after opening the SAC window. The invention describes a method for forming a bit line on a DRAM structure. In the capacitor method, a window for automatically aligning a contact window is opened between bit lines and penetrates the silicon oxide layer, and then a dielectric gap wall is formed on a sidewall of the bit line structure. The first polycrystalline silicon plug structure is formed on the source / drain region, and is used to connect and conduct the source / drain region on the semiconductor substrate. Bit 3 This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the notes on your mouth before filling in this page) Loading -------- Order --------; Λ / 1-Staff of the Intellectual Property Bureau of the Ministry of Economic Affairs Consumption Cooperation Du Yin-44-1101 A7 ________B7_ V. Description of the Invention ()) Between the word line structures covered by silicon nitride, and it is automatically aligned. A bit line structure with a silicon nitride cap is then formed, the direction of which is perpendicular to the underlying character line structure, and a silicon oxide layer is subsequently deposited. Next, an auto-alignment contact window is opened on the oxide layer and penetrates between the bit lines, exposing the top of the first polycrystalline silicon plug structure. A silicon oxide spacer is then formed on the sidewalls of the bit line structure, and a second polycrystalline plug structure is then formed between the bit line structures. Finally, a capacitor is formed on the second polycrystalline silicon plug structure. Brief Description of the Drawings: FIG. 1A is a top view after the character line structure is completed in the present invention. FIG. 1B is a schematic cross-sectional view of the direction A-A in FIG. 1A. FIG. 1C is a schematic cross-sectional view of FIG. 1A in the direction of B-B. FIG. 2A is a top view of the silicon oxide structure in the present invention. FIG. 2B is a schematic cross-sectional view in the direction C-C of FIG. 2A. FIG. 2C is a schematic cross-sectional view in the direction D-D of FIG. 2A. FIG. 3A is a top view of the first polycrystalline silicon plug structure in the present invention. FIG. 3B is a schematic cross-sectional view in the direction E-E of FIG. 3A. FIG. 3C is a schematic sectional view of FIG. 3A in the direction of F-F. FIG. 4A is a top view of the bit line structure in the present invention. FIG. 4B is a schematic cross-sectional view in the direction G-G of FIG. 3A. FIG. 5 is a schematic cross-sectional view after the window of the contact window is automatically aligned in the present invention. 4 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (please read the precautions on the arm surface before filling out this page) Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (f) Figure 6 is a schematic back view of the cross section after the completion of the silicon oxide spacer in the present invention. FIG. 7 is a schematic cross-sectional view of the second polycrystalline silicon plug structure in the present invention. FIG. 8 is a schematic sectional view after the embodiment of the present invention is completed. Description of drawing number: 1- semiconductor substrate 2-shallow trench isolation region 3-gate dielectric layer 4-polycrystalline silicon layer 5-silicon nitride cap 6_ source / drain region 7-dielectric gap 8 ~ 11-word line structure 12-silicon oxide structure 12A-silicon removed area 13-first polycrystalline silicon plug structure 14-conductive layer 15-nitride sand layer 16-bit line structure 17-silicon oxide Layer 18-Automatically aligned window for contact window 19-Silicon oxide spacer 20-Second polycrystalline silicon plug structure 21-Capacitor structure 22-Polycrystalline silicon storage electrode structure 23-Capacitor dielectric layer 24-Polycrystalline silicon Electrode structure 30-oxide sand layer Detailed description of the invention: The present invention provides a method for forming a memory cell of a dynamic random access memory with a capacitor on a bit line on a semiconductor substrate. One of the characteristics of this method is that the formed auto-alignment contact window is in the bit line structure. The paper size is applicable to the Chinese National Standard (CNS) A4 specification < 210 X 297.) (Please read Note for refilling this page) Binding ---------. Consumption cooperation of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 441 10 1 Δ7 ___ Β7__ V. Interpretation of invention (meaning) Interpenetration; another of this method The silicon oxide spacer wall, which is characterized by a bit line structure, is formed after the auto-alignment contact window is opened. FIG. 1A is a top view of a COB MIMO element after forming a word line structure 8-11. Figure 1A also shows the area of the semiconductor substrate 1 and the Shallow Trench Isolation. Figures 1B and 1C show schematic cross-sectional views of the character line structures 8-11 in the A-A and B-B directions, respectively. The semi-conductor substrate 1 is a P-doped wafer, and its lattice direction is < 100>. The shallow trench isolation region 2 is formed by using a conventional lithography and anisotropic reactive ion etching (Reactive Ion Etching; RIE) on a semiconductor substrate 1 to form a shallow trench. The etching system uses chlorine gas (Cl0 as a reaction gas. After removing the photoresist used to define shallow trenches by Plasma 0xygen Ash and wet dephotoresist method, the low-pressure chemistry is used to remove the photoresist. A vapor deposition method (Low Pressure Chemical Vapor Deposition; LPCVD) or a plasma enhanced vapor deposition method (Plasma Enhanced Chemical Vapor Deposition; PECVD) is used to deposit a silicon oxide layer to fill the shallow trench. Then, a chemical mechanical polishing method is used. (Chemical Mechanical Polishing; CMP) or Selective Reactive Ion Etching (Selective RIE) to remove the silicon oxide layer located on the surface of the semiconductor substrate 1 to form a shallow trench isolation region 2 as shown in FIGS. 1B and 1C As shown in Figures 1B and 1C, a Gate Insulator Layer 3 is formed by a conventional thermal oxidation method with a thickness of 20 to 80 people. Next, a low-pressure chemical vapor phase is used. sink LPCVD to form a polycrystalline silicon layer 4 with a thickness between 8Q0 and 400GA. The polycrystalline silicon layer 4 6 I ------!-^ ≫ pack-! 1 --- -Order · •-(Please read the precautions on the arm surface before filling out this page) This paper size applies to the Chinese National Standard < CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 4110 1 A7 _; ___B7__ 5. Description of the Invention (b) There are two methods for doping, one of which is to mix arsenic or phosphorus into the reaction gas Silane, so that arsenic or phosphorus is simultaneously deposited with silicon; One method is to deposit an intrinsic polycrystalline silicon layer, and then dope arsenic or phosphorus into the polycrystalline silicon layer by ion implantation. Subsequently, a silicon nitride layer is deposited by LPCVD or PECVD technology to a thickness of 500 to 3G00A. Using conventional lithography and anisotropic reactive ion etching techniques, CF4 is used as a reactive gas to etch the silicon nitride layer, and Cl2 is used as a reactive gas to etch the polycrystalline silicon layer 4 to form a silicon layer as shown in Figure 1B. Word line structure 8-11. The photoresist used to define the character lines is then stripped off using an oxygen plasma ashing method and a wet de-resistance method. The gate dielectric layer 3 not covered by the word lines 8-11 is removed during the wet photoresist removal process described above. In addition, if a word line structure 8-11 with lower resistance is desired, a silicided metal layer can also be deposited on the polycrystalline silicon layer. Next, please continue to refer to FIG. 1B and FIG. 1C. A lightly doped source / drain region (LDD) 6 is formed on the semiconductor substrate 1 in a region not covered by the word line structure 8-11. . The LDD region 6 is formed by ion implantation with arsenic or phosphorus ions having an energy between 20 and other KeV, and its doping concentration is between 1E12 and 5E13 atoms / cm 2. Next, a dielectric spacer 7 is formed on the sidewall of the word line structure 8-11. The manufacturing process of the dielectric spacer 7 is to first form a silicon nitride layer with a thickness of 100 to 1 GGGA by using LPCVD or PECVD, and then use CF4 as a reaction gas by anisotropic reactive ion etching. Etching back. As shown in FIG. 1B, at this time, the word line structures 8-11 have been completely covered by silicon nitride, including the silicon nitride top cover 5 and the dielectric spacer 7 on the side wall. Then use LPCVD or PECVD technology to deposit a silicon oxide layer with a thickness of 7 (please read the precautions on the front side and then fill out this page). The size of this paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) 4110 B7 Duo Printing by Employees' Intellectual Property Bureau, Ministry of Economic Affairs

5. Description of the invention (;?) Between 2000 and 8Q00A. Then, a planarization process is performed by CMP technology, and the top of the silicon oxide layer is polished. The conventional lithography process is used to perform anisotropic reactive ion etching with CHF3 as the reactive gas, and the silicon oxide at 12A is removed to define a silicon oxide structure directly above the shallow trench isolation area 2. ) 12. Fig. 2A shows a top view of the oxidized sand structure 12, and Fig. 2C shows a schematic 7K side view of the silicon oxide structure 12 in the D-D direction. FIG. 2B is a schematic side cross-sectional view in the direction C-C of FIG. 2A, showing that the silicon oxide structure 12 covers the word line structure 8-11. Oxygen plasma ashing and wet photoresist stripping are used to remove the photoresist used to define the silicon oxide structure 12. Next, a polycrystalline silicon layer is formed by LPCVD with a thickness between 2QG0 and 6000 people. There are two methods for doping the polycrystalline silicon layer, one of which is doping arsenic or phosphorus into the reactive gas silane to deposit arsenic or phosphorus and silicon simultaneously; the other method is to deposit an essential polycrystalline silicon layer first Then, arsenic or phosphorus is doped into the polycrystalline silicon layer by an ion implantation technique. Then, the CMP technology is used to perform a planarization process, and the polycrystalline silicon layer on the word line structure 8-11 above the nitride cutting cap 5 and the silicon oxide structure 12 is polished away to form a first polycrystalline silicon plug. Structure (First Polysilicon Plug Structure) 13. As shown in FIG. 3B, the first polycrystalline silicon plug structure 13 is located between the word line structures 8-11 covered by silicon nitride, and is located above the lightly doped source / drain region 6 For connection conduction. The CMP process also forms a first polycrystalline silicon plug structure 13 as shown in FIG. 3C. The first polycrystalline silicon plug structure 13 is also located in the word line structure 8- Between 11, it is located above the lightly doped source / drain region 6 for connection conduction. Figure III A shows S ------------ install --- (please read the precautions on the mouth first and then fill in this page) I n VK n order ---- ν. This paper size applies China National Standard (CNS) A4 specification (210 X 297 mm) 4 41 10 1 A7 _____B7______ V. Description of the invention () shows the top view of the first polycrystalline silicon plug structure 13 which is located between the character line structures, It is also located between the oxidized chopping structures 12. In the subsequent system, a silicon oxide layer 30 is formed first, and then a bit line structure 16 is formed. FIG. 4A shows a top view thereof, and FIG. 4B shows a schematic cross-sectional view in the G-G direction. The bit line structure 16 includes a conductive layer composed of a doped polycrystalline silicon layer, a tungsten metal layer, a tungsten silicide layer, or a polycrystalline metal silicide layer (covered by a layer of metal silicide on a polycrystalline silicon layer). Layer 14. Each of the above conductive layers can be formed by LPCVD, and its thickness is between 500 and 4000A. There are two methods for doping the polycrystalline silicon layer, one of which is doping arsenic or phosphorus with a reactive gas to cut arsenic to simultaneously deposit arsenic or phosphorus with silicon; the other method is to first deposit an essential polycrystalline silicon layer Then, arsenic or phosphorus is doped into the polycrystalline silicon layer by an ion implantation technique. Subsequently, a silicon nitride layer 15 is formed on the conductive layer U by LPCVD or PECVD, and the thickness is between 500 and 3,000. Using conventional lithography and anisotropic reactive ion etching techniques, CF4 is used as a reactive gas to etch the silicon nitride layer 15 and Ch is used as a reactive gas to etch the conductive layer 14 to form the sites shown in FIG. 4A. Element line structure 16. As shown in FIG. 4A, the bit line structure 16 is perpendicular to the word line structure 8-11, and as shown in FIG. 4B, the bit line structure 16 is located above the silicon oxide structure 12. The photoresist used to define the bit line structure 16 is stripped by an oxygen plasma ashing method and a wet photoresist removal method. Subsequently, a silicon oxide layer 17 is formed by LPCVD or PECVD with a thickness between 2000 and 8000 A, and the gaps between the bit line structures 16 are filled. Then, a CMP step is performed to smooth the surface of the silicon oxide layer 17. Then, as shown in Figure 5, the automatic alignment contact is turned on the flattened silicon oxide layer _____ 9 _ This paper size is applicable to the National Standard of China (CNS) A4 (210 X 297 mm) (Please read first Note on the front page, please fill out this page) -------- Order ----- 11 '' Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 4 41 10 1 A7 B7 V. Description of Invention (j) (Please read the precautions for the arm surface before filling out this page) Window 18 of the window. In the lithography process of forming the window 18 of the auto-aligned contact window, the width of the photoresist openings must be greater than the pitch of the bit line structure 16, and the width of the photoresist openings must be greater than the word line structure 8-11. Pitch. Using anisotropic reactive ion etching technology, using chf3 as a reactive gas to etch the oxide cleave layer, penetrate the oxide cleave layer Π 'between the two bit line structures 16 to expose the first polycrystalline silicon plug structure 13 Top surface. By virtue of the high etch selection ratio (about 25 to 1) between the silicon oxide layer 17 and the exposed silicon nitride layer 15 and the high etch selection ratio (about 25 to 1) between the silicon oxide and the first polycrystalline silicon plug structure 13 It is 20 to 1), and the window 18 of the automatic alignment contact window is formed, as shown in FIG. 5B. It is also shown in FIG. 5 that the window 18 of the self-aligned contact window is between the word line structures 8-11, and the surface of the first polycrystalline silicon plug structure 13 is exposed. Oxygen plasma ashing and wet photoresist stripping are used to remove the photoresist of window 18, which defines the automatic alignment of the contact window. It is particularly important that the window 18 of the self-aligning contact window is completed before the insulation gap on the side wall of the bit line structure is formed. Therefore, it is possible to avoid the conventional technique of forming the window 18 of the self-aligning contact window. Damage caused by insulating spacers on the sidewalls of the bit line structure during the RIE process. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to Figure 6, and then the dielectric gap wall of the bit line structure sidewall will be formed. First, a silicon oxide layer is formed by LPCVD or PECVD, and the thickness is between 300 and 2000 people. Then, using CHF3 as a reaction gas, and performing etchback using RIE technology, a silicon oxide spacer (Si 1 icon Oxide Spacer) 19 can be obtained. As shown in FIG. 6, the silicon oxide spacer 19 is located on the sidewall of the silicon nitride top cover in the bit line structure 16, and the silicon oxide spacer 19 is also located on the silicon oxide structure 17 (located in the word line 8-11 Top) of the sidewall. If 10 papers are printed in Chinese National Standard (CNS) A4 (210 X 297), ~ 4110 1 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 5. The invention description (π) is also required The silicon oxide spacer 19 is made into a silicon oxide-silicon nitride double-layer structure. However, it needs to be emphasized that compared with the simple use of silicon nitride, the use of silicon oxide as the material of the spacer can make the coupling capacitance between the bit line structure and the capacitor formed later smaller. In the present invention, the window for automatically aligning the contact window is opened before the gap wall is formed, which makes it possible to use silicon oxide as the material of the gap wall. However, if the spacer is formed first according to the process steps of the conventional technology, and then the window for automatically aligning the contact window is opened, the silicon nitride must be used as the material of the spacer in order to use the high etching between the silicon nitride and the silicon oxide layer Select ratio for etch back. Referring to FIG. 7, a second polycrystalline silicon plug structure 20 will be formed on the window 18 of the auto-alignment contact window. First, a polycrystalline silicon layer is formed by LPCVD, with a thickness between 1000 and 3G00A, in order to fill the window 18 of the auto-alignment contact window. The doping system of the polycrystalline silicon layer is obtained by synchronous doping, adding arsenic or phosphorus in a silane environment while depositing the polycrystalline silicon. Next, the polycrystalline silicon layer on the surface of the silicon oxide layer 17 is polished by using CMP technology, and a second polycrystalline silicon plug structure 20 is formed in the window 18 of the automatic alignment contact window. The second polycrystalline silicon plug structure 20 is located above the first polycrystalline silicon plug structure 13 and is connected to the first polycrystalline silicon plug structure 13. Next, as shown in FIG. 8, a capacitor structure 21 is formed above the second polycrystalline silicon plug structure 20, so that the capacitor structure 21 can be conducted to the source through the connection of the second polycrystalline silicon plug structure 20. Pole / drain region 6. The capacitor structure 21 includes a Polysilicon Storage Node Structure 22, a Capacitor Dielectric Layer 23 such as Ta205 or ONO, and an electrode structure on polycrystalline silicon. This paper is applicable to this paper. China National Standard (CNS) A4 Specification (210 x 297 mm) ----------- 3 Packing -------- Order -----------.. ··-:, (Please read the precautions on your mouth before filling in this page "'4 41 10 1 ΚΙ _Β7_ V. Description of the Invention (丨 丨) (Polysilicon upper Electrode Structure) 24 〇 Therefore, the structure of the bit line capacitor Completed in detail. The present invention is described in detail, but not to limit the scope of the invention, and those skilled in the art will also understand that making appropriate changes and adjustments will still not lose the essence of the invention or depart from it. The spirit and scope of the invention should be regarded as the further implementation of the present invention. (Please read the notes on the front side before filling out this page.) The paper printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese national standard ( CNS) A4 size (210 X 297 mm)

Claims (1)

4 41 10 1 g D8, patent application scope 1. A method of forming dynamic random access memory with capacitors on bit lines (please read the precautions on the back before filling this page), the steps include: (a) in An isolation region is formed on a semiconductor substrate in a first region; (b) a gate dielectric layer is formed in a second region on the semiconductor substrate and not occupied by the isolation region; (c) Forming a word line structure, which is located above part of the isolation region and also above part of the gate dielectric layer; (d) on the Mou conductor substrate and is The word line structure and the area occupied by the isolation region to form a source / drain region; (e) forming a dielectric structure in the isolation region; (0 forming a low-level complex crystalline plug structure, the The low-level polycrystalline sand plug structure is located between the dielectric structure and between the word line structures; the low-level polycrystalline silicon plug structure is located above the source / drain region, And directly contact the source / drain region; economic Printed by the Intellectual Property Bureau employee consumer cooperative (g) forming a silicon oxide layer; (h) forming a bit line structure above the silicon oxide layer; (i) forming a planarized dielectric layer to completely fill all The space between the bit lines, the dielectric layer is formed on the bit line structure, and also on the low-level polycrystalline silicon plug structure; (j) on the planarized An automatic alignment contact is formed on the dielectric layer. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs? Christine s_D8 _._ The window of the window, wherein the window of the automatic alignment contact window penetrates the dielectric layer between the bit line structures to expose the sidewall of the bit line structure, and exposes the low-level polycrystalline silicon plug structure. Top; (k) forming a dielectric gap wall in the window of the auto-alignment contact window, the dielectric gap wall is located on the side wall of the planarized dielectric layer, and is also located on the bit The side walls of the line structure; (l) in the self-aligning contact window A high-level compound silicon plug structure is formed in the mouth, and the high-layer compound silicon plug structure is located above the low-layer compound silicon plug structure and directly contacts the low-layer compound silicon plug structure; and (m ) A capacitor structure is formed above the high-level polycrystalline silicon plug structure, and the capacitor structure directly contacts the high-level polycrystalline silicon plug structure. 2. The formation position as described in item 1 of the scope of patent application A method of dynamic random access memory for capacitors on an element line, wherein the isolation region is a shallow trench region filled with silicon oxide, and the method for forming the isolation region is firstly formed on the semiconductor substrate by an etching technique. In the shallow trench area, a silicon oxide layer is formed by LPCVD or PECVD to fill the shallow trench area, and then the unnecessary silicon oxide layer is removed by chemical mechanical polishing. 3. The method for forming a dynamic random access memory with a capacitor on a bit line as described in item 1 of the scope of the patent application, wherein the gate dielectric layer is composed of silicon oxide, and the silicon oxide is formed by It is formed by thermal oxidation method, and its thickness is between 20 and 80A. (Please read the note on the back? Matters before filling out this page) tr --------- Λ% This paper applies the national standard (CNS) A4 size (210 x 297 mm) of the Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Cooperatives 4 4110 1 ____ §_ VI. Scope of Patent Application 4 · The method for forming a dynamic random access memory with a bit online capacitor as described in item 1 of the scope of patent application, the word The element line structure is composed of polycrystalline silicon. First, a layer of polycrystalline silicon is formed by LPCVD technology with a thickness between 8G0 and 400GA. There are two methods for doping the polycrystalline silicon layer. One of them is The reactive gas silane is doped with arsenic or phosphorus to deposit arsenic or phosphorus and silicon simultaneously; another method is to deposit an intrinsic polycrystalline silicon layer first, and then dope arsenic or phosphorus into the polycrystalline silicon by ion implantation technology. Floor. 5. The method for forming a dynamic random access memory with a capacitor on a bit line as described in item 1 of the scope of the patent application, the dielectric structure is a silicon oxide structure, and the method for forming the silicon oxide structure is LPCVD or PECVD technology forms a silicon oxide layer with a thickness between 2000 and 8000 A. The silicon oxide structure is defined by anisotropic reactive ion etching. The reaction gas used is CHF3. 6. According to the method for forming a dynamic random access memory with a capacitor on a bit line as described in item 1 of the scope of the patent application, the low-level polycrystalline silicon plug structure is firstly formed with a polycrystalline silicon layer by LPCVD technology. The thickness is between 2000 and 6000 A. The doping of the polycrystalline silicon layer is doped with arsenic or phosphorus into the reactive gas silane, so that arsenic or ortho and silicon are deposited simultaneously, and then a low-level complex crystal is defined by chemical mechanical polishing. Silicon plug structure. 7. The method for forming a dynamic random access memory with a capacitor on a bit line as described in item 1 of the scope of the patent application. The bit line structure is composed of polycrystalline silicon. First, a layer of polycrystalline silicon is formed by LPCVD technology. The silicon layer has a thickness between 500 and 4G0QA. There are two methods for doping the polycrystalline silicon layer. One of them is doping arsenic with arsenic or lin to react with arsenic (please read the Note: Please fill in this page again.): 5 paper sizes are applicable to Chinese National Standard (CNS) A4 (210 X 297 mm> 4 4110 1 A8 BS C8 D8. 6. Scope of patent application or simultaneous deposition of phosphorus and silicon; Another method is to deposit an intrinsic polycrystalline silicon layer first, and then dope the arsenic or scale into the polycrystalline silicon layer by using ion implantation technology. 8. Form the bit line on the basis of the first patent application In a method of dynamic random access memory for a capacitor, the bit line structure may be composed of a tungsten metal layer, a silicided crane layer, or a polycrystalline silicon silicide layer (for example, a tungsten silicide layer is covered on a polycrystalline silicon layer). Formation, each of the above conductive layers can be formed by LPCVD Its thickness is between 500 and 4000 A. 9. The method for forming a dynamic random access memory with a capacitor on a bit line as described in item 1 of the patent application range, wherein the planarized dielectric layer is formed by It is composed of silicon oxide, which is formed by LPCVD or PECVD, and has a thickness between 2000 and 800 UA, and then is planarized by a chemical mechanical polishing method. 10. As described in item 1 of the scope of patent application A method for forming a dynamic random access memory with a capacitor on a bit line, wherein the window of the auto-aligned contact window is formed on the planarized dielectric layer, and anisotropic reactive ion etching is used. Technology, using CHF3 as a reactive gas to etch the silicon oxide layer 'by virtue of a high etching selectivity ratio of about 25 to 1 between silicon oxide and the exposed silicon nitride layer 15, and the plug structure of silicon oxide and the first polycrystalline silicon A high etching selection ratio of about 25 to 1 is used for etching. 11. The method for forming a dynamic random access memory with a capacitor on a bit line as described in item 1 of the scope of patent application, said dielectric gap Method of wall formation First, a silicon oxide layer is formed by LPCVD or PECVD technology. Its thickness is between 300 and 2Q00A, and then anisotropic reactive ion etching is performed. The reaction gas used is CHF3. The paper size is applicable to Chinese national standards ( CNS) A4 size (210 X 297 mm) (Please read the precautions on the back before filling out this page) Pack --- ^ ------- Order --------- Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperatives Printed by the Ministry of Economy ’s Intellectual Property Bureau ’s Consumer Cooperatives 4 411 CH Blue C8 D8 VI. Patent Application Scope 12. Dynamic Random Access to Form Bit Online Capacitors as described in Item 1 of the Patent Scope Memory method, the high-level polycrystalline silicon plug structure is first formed by a LPCVD technology with a polycrystalline silicon layer having a thickness between 1000 and 30 G0A, and the doping of the polycrystalline silicon layer is arsenic or disk The reactive gas silane is doped, so that arsenic or phosphorus is simultaneously deposited with silicon, and then a chemical-mechanical polishing method is used to define the high-level compound crystal plug structure. 13. A method for forming a capacitor on a bit line on a semiconductor substrate, the capacitor on the bit line is used for dynamic random access memory, and the method is characterized in that the formed window of the automatic alignment contact window is formed by a bit Penetration between the element line structures, another feature of the present invention is that the dielectric gap wall of the side wall of the bit line structure is formed after opening the window of the auto-alignment contact window, the steps include: (a) in the Forming an isolation region filled with silicon oxide on a semiconductor substrate; (b) forming a gate dielectric layer composed of silicon oxide on the semiconductor substrate and not occupied by the isolation region; ( c) forming a word line structure covered by silicon nitride in a direction perpendicular to the isolation region, the word line structure is located above a part of the isolation region and also on a part of the gate electrode Over the dielectric layer; (d) forming a source / drain region on the semiconductor substrate and not occupied by the word line structure and the isolation region; (e) on the isolation Area and not by the character line Area occupied by the organization 17 This paper size is in accordance with China National Standard (CNS) A4 (210 x 297 mm) (Please read the precautions on the back before filling out this page) Install t & j Employees ’Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Print g __— 6. Form a dielectric structure within the scope of the patent application; (0 form a first polycrystalline silicon layer; (g) perform the first chemical mechanical polishing process to remove the first silicon oxide structure above the silicon oxide structure. A polycrystalline silicon layer to form a low-level polycrystalline silicon plug structure, the low-level polycrystalline silicon plug structure is located between the dielectric structure and also between the word line structures; the low layer The polycrystalline silicon plug structure is located above the source / drain region and contacts the source / drain region; α) forming a silicon oxide layer; (i) forming a bit above the silicon oxide layer Element line structure, the bit line structure including a top cover formed of silicon nitride; (j) forming a silicon oxide layer to completely fill the space between the bit line structures; (k) performing a second Sub-chemical mechanical polishing process to convert the silicon oxide (1) forming a window for automatically aligning a contact window on the silicon oxide layer, the window of the automatically aligning contact window penetrating the silicon oxide layer between the bit line structures and exposing A sidewall of the bit line structure, and the top of the low-level polycrystalline silicon plug structure is exposed; (in) a dielectric gap wall is formed on the sidewall of the bit line structure, and the bit line structure is exposed on Inside the window of the self-aligned contact window; (η) forming a second polycrystalline silicon layer to completely fill the window of the self-aligned contact window; This paper size applies to the Chinese National Standard (CNS) A4 specification (210 χ 297 mm) (Please read the precautions on the back before filling out this page) Install IIIII ί I. U1 1 Ο 8 Α8 '_ _D8 VI. Apply for a patent scope (0) Perform the third chemical mechanical polishing process to remove the A second polycrystalline silicon layer above the silicon oxide layer to form a high-level polycrystalline silicon plug structure 'said high-level polycrystalline silicon plug structure is located above the low-level polycrystalline silicon plug structure and directly contacts The low-level polycrystalline silicon plug structure And Cp) forming a capacitor structure over the top of polysilicon plug structure, the capacitor structure and directly contacts the top of polysilicon plug structure. 14. The method for forming a capacitor on a bit line as described in item 13 of the scope of the patent application, wherein the silicon oxide gate dielectric layer is formed by a thermal oxidation method and has a thickness of 20 to Between 80A. 15. The method for forming a capacitor on a bit line as described in item 13 of the scope of the patent application, wherein the word line structure covered by silicon nitride is composed of a polycrystalline silicon layer and nitrogen above it. It is made of silicon. First, a crystalline silicon layer is formed by LPCVD technology. The thickness is between 800 and 4000A. The reactive gas silane is mixed with arsenic or scale, and arsenic or phosphorus and silicon are deposited simultaneously. Then use LPCVD or PECVD technology to form a silicon nitride layer with a thickness between 500 and 3000A; 16. The method for forming a capacitor on a bit line on a semiconductor substrate as described in item 13 of the scope of patent application, said nitrogen The word line structure covered by siliconized silicon is made of a silicidated metal layer and silicon nitride above it. First, a layer of silicidated metal is formed by LPCVD technology, with a thickness between 800 and 40 G0A. Or phosphorus is connected to the reactive gas silane, and arsenic or phosphorus and silicon are deposited simultaneously, and then formed by LPCVD or PECVD technology (please read the precautions on the back before filling this page) -----:-order- --- Qi, an employee of the Intellectual Property Bureau of the Ministry of Economic Affairs The paper size printed by Fei Cooperative is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) OQ8859 WBCD Sixth, the scope of patent application-a silicon nitride layer with a thickness between 500 and 30Q0A; the silicided metal layer It may be a tungsten silicide layer. 17. The method for forming a capacitor on a bit line as described in item 13 of the scope of the patent application, wherein the word line structure covered by silicon nitride includes silicon nitride located on a sidewall of the word line structure. The method for forming the silicon nitride spacer wall by forming a silicon nitride spacer wall using PECVD or LPCVD technology, and then performing back-etching using anisotropic reactive ion etching, and using CF4 as a reactive gas. 18. The method for forming a capacitor on a bit line as described in item 13 of the scope of patent application, said method for forming a silicon oxide structure is to first form a silicon oxide layer by LPCVD or PECVD technology, and the thickness is between 2000 and 2000. To 80GGA. 19. The method for forming a capacitor on a bit line as described in item 13 of the scope of the patent application, wherein the bit line structure is made of a polycrystalline silicon structure and a silicon nitride structure thereon, The polycrystalline silicon structure is made of a polycrystalline silicon layer. The method for forming the polycrystalline silicon layer is to use LPCVD technology to mix arsenic or phosphorus with a reactive gas silane to deposit arsenic or phosphorus and silicon simultaneously. The thickness is between 5QQ and 400GA. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). 20. As described in item 13 of the scope of patent application, a method for forming a capacitor on a bit line on a semiconductor substrate is used. The bit line structure is made of a silicide crane structure and a silicon nitride structure above it. The tungsten silicide structure is made of a tungsten silicide layer. The method for forming the tungsten silicide layer is deposited using LPCVD technology. And its thickness is between 5QG and 4GQ0A. 21. Form 20 bits on the semiconductor substrate as described in item 13 of the scope of patent application. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 4 4110 1 B8 C8 D8 Employees of Intellectual Property Bureau, Ministry of Economic Affairs Consumer Cooperatives Printed 6. Method of Capacitors on Patent Lines where the auto-aligned contact window is formed on the oxide layer, using anisotropic reactive ion etching technology, with CHF3 as the reaction Gas to etch the silicon oxide layer, with a high etch selection ratio of about 25 to 1 between silicon oxide and silicon nitride layer 15 and a high etch selection ratio of about 25 to 1 between silicon oxide and polycrystalline silicon, For etching. 22. According to the method for forming a capacitor on a bit line on a semiconductor substrate as described in item 13 of the scope of the patent application, the dielectric spacer wall on the side wall of the bit line structure is a silicon oxide spacer to form the silicon oxide spacer The method is to first form a silicon oxide layer by LPCVD or PECVD technology, and then perform anisotropic reactive ion etching. The reaction gas used is CHF3. I 23. A bit-line capacitor formed on a semiconductor substrate, said bit-line capacitor being used for dynamic random access memory, comprising: (a) a shallow trench region filled with a dielectric , Located on a semiconductor substrate; (b) a gate dielectric layer, located on the semiconductor substrate and not occupied by the isolation region; (c) a word line structure covered with silicon nitride, located at In a direction perpendicular to the isolation region, the word line structure covered by silicon nitride is located above part of the isolation region and also above part of the gate dielectric layer; (d) The source / drain region is located on the semiconductor substrate and is not covered by the word line structure covered by the silicon nitride and the isolation. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------- ^-— 11 — Λ1 / ^ * 1 ---- ^ --- Order ---- 1! '-Λ (Please read the notes on the back before filling in this Page) 4 41 10 1 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs VI. Area occupied by patent application area (e) a dielectric structure located above the shallow trench area filled with the dielectric; (0 low-level polycrystalline silicon plug structure located between the dielectric structures and also located Between the word line structures; the low-level polycrystalline silicon plug structure is located above the source / drain region and directly contacts the source / drain region; (g) a silicon oxide layer, the The silicon oxide layer has a contact window; Ch) a bit line structure with a silicon nitride top cover above the oxide sand layer; (i) a window on a flat silicon oxide layer, the window exposing the nitrided layer The sidewall of the bit line structure of the silicon top cap also exposes the top of the low-level polycrystalline silicon plug structure; (j) a dielectric gap wall is located in the bit line structure of the silicon nitride cap. A side wall; a 00 high-level polycrystalline silicon plug structure, located in a window on the flat silicon oxide layer, and above the low-level polycrystalline silicon plug structure, directly contacting the low-level polycrystalline silicon plug structure; and (1) a capacitor structure located above the high-level polycrystalline silicon plug structure, Directly contacting the top of polysilicon plug structure. 24. The bit line capacitor according to item 23 of the scope of the patent application, wherein the isolation region filled with the dielectric is an isolation region filled with silicon oxide. 25. The bit online capacitor as described in item 23 of the scope of patent application, in which the paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) (Please close the precautions on the back before filling in this Page) Binding ·-Λ 41 1 Ο 1 Α8 D8 6. The word line structure covered by silicon nitride as described in the scope of the patent application includes a silicon nitride structure with a thickness of 500 to 3 DGGA, and is located in the nitride. The lower layer of the silicon structure is a polycrystalline silicon structure with a thickness between 800 and 4G00A, and includes a silicon nitride spacer on the sidewall of the word line structure. 26. The bit-line capacitor according to item 23 of the scope of patent application, wherein the word line structure covered by silicon nitride comprises a silicon nitride structure having a thickness of 500 to 3Q00A, and A polycrystalline silicon structure, a tungsten structure, or a tungsten silicide structure with a thickness lower than 500 to 4G00A. 27. The bit line capacitor according to item 23 of the scope of the patent application, wherein the window opened in the flat silicon oxide layer is a window that is automatically aligned with the contact window and is located between the bit line structures. The sidewall of the bit line structure is exposed in the window of the auto-aligned contact window. 28. The bit-line capacitor according to item 23 of the scope of the patent application, wherein the dielectric spacer on the sidewall of the bit-line structure is made of silicon oxide and has a thickness between 300 and 2QG0A. --- · --- ^ ---- I --- ^ ------- Order --------- ^ # (Please read the notes on the back before filling this page) Ministry of Economy Printed by the Intellectual Property Bureau Staff Consumer Cooperatives 23 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)