TW424302B - Manufacturing method for interconnect structure on the semiconductor substrate - Google Patents

Abstract

The present invention provides a manufacturing method for interconnect structure to make the via to contact underneath one side of the via plug structure in which the via plug structure can connect the bit lines with the device active area on the semiconductor substrate. The process especially discloses using a simple photolithography pattern, such as strip-like opening, to expose a group of gate structures and a group of spacers between the gate structures; then, these structures can be used to produce the via plugs. The steps are greatly different from the conventional processes that in the conventional process, it needs a more difficult photolithography step to produce a smaller and individual opening in the space between the gate structures. Furthermore, the invention discloses a self-aligned opening which only exposes on side of the via plug structure; therefore, the above interconnect structure can contact the via plug structure exposed only one side for further reducing the difficulties of photolithography technique in the conventional process for creating a non-self-aligned opening on the via plug.

Description

02 ^ 02 ^ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (/) Background of the Invention: Field of the Invention: The present invention relates to a method for manufacturing semiconductor components, especially a method for manufacturing bit lines (above ) And contact window plug (underneath). Prior art; as described: The purpose of the semiconductor is to continuously reduce the area of the dynamic random access memory (DRAM) or static random access memory (SRAM) on the guard body (1C). Whether such a goal can be achieved depends on the implementation of special semi-conductive brooding techniques to observe the ability to modify the fiber which is difficult to use as a tool, and thereby achieve the goal of reducing the characteristic length of the component to less than 0.25 microns. Thanks to advances in lithography tools, short wavelengths can be achieved using KrF (248 nm) or ArF (193 nm). However, if you want to reduce the feature length of the device to 0.1 micron or even smaller, you need a special semiconductor unit, such as a conductive interconnect structure, to achieve it. In order to make these units in a smaller size, in addition to the lithographic technology, there must be some progress, and related process matching is also required to achieve it. The present invention will describe a new step that can lead to structural innovations to achieve the sub-quarter (micron) feature length target. This method will not increase the burden on lithography technology, such as increasing the resolution of exposure or requiring more sensitive lithography alignment capabilities and critical image control capabilities. A feature of the present invention is that three contact window plugs are generated in a self-aligned manner around the scent pole structure, and the three contact window plugs are combined together by using a single long contact window opening. 2 This paper size is suitable for S 0 home standards (CNShYl specifications (2HJ X 297 male. ¾) J -----------! Installed -------- order. (Please read the back first Please pay attention to this page and fill in this page) Consumption cooperation with employees of the Intellectual Property Bureau of the Ministry of Economic Affairs 77 Β7 5. The invention description (>) can simplify the difficulties encountered in patterning in the traditional process. In the manufacturing process, individual contact windows are formed in individual contact window plug structures. In addition, the present invention also refers to a bit line structure in a self-aligned manner in the inactive area of the component The side wall connected to the contact window plug structure. This simplifies the patterning step in the traditional process; because in the traditional process, the opening on the contact window plug is made in the active area of the component. Past technology, such as Mr. Witek et al., US Patent No. 5,396,681, and Mr. Woo In U.S. Patent No. 54S1543, et al. Once described the method of making a contact window. However, these past technologies do not mention a solution for combining brain and face plugs, or making contact line plugs with bit line structures in In the non-active area of the device. Brief description of the invention: The main purpose of the present invention is to use a simplified patterning technique to produce ultra-small interconnect structures in semiconductor devices. Another object of the present invention is A merged contact window pattern is generated in the silicon layer. This invention can simultaneously expose a series of areas between the gate structures, which will be used to form the contact window plug structure. This can reduce the complexity of the traditional patterning step. Because in the traditional patterning step, individual regions between the pole structures are individually opened. Another object of the present invention is to make a one-bit wire opening in a sand dioxide layer. The opening can self-align. To the adjacent gate structure and the adjacent contact window plug structure, and allow subsequent bit line fibers to contact the contact window plug structure. Applicable Chinese Standard (CNS) Al Regulations (21 Hearts S) ——, ————: Install -------- Order. (Please read the precautions on the back before filling this page) Economy Printed by the Consumer Cooperative of the Ministry of Intellectual Property Bureau Λ 0 2, A7 _____ B7 V. Description of the Invention (i) The present invention is to propose a method using a simplified lithographic pattern to form a self-aligned interconnect structure. This structure is in contact with one side of the contact plug underneath it. After forming a series of polysilicon capped (polycide gate structure) with a silicon nitride cap, a polysilicon gate structure is formed. A source / drain region is formed therebetween and a sidewall spacer made of silicon nitride is formed. This leaves a thin layer of silicon nitride on top of the source / drain region. After depositing the first silicon dioxide layer, a simple strip-shaped opening can be used to make a series of openings in the area between the polysilicon metal gate structures. These openings are still covered by silicon nitride. After removing the thin nitrided sand layers between the polysilicon metal gate structures, a conductive layer is deposited into the openings between the polysilicon metal gate structures. Then, the conductive layer is ground by chemical mechanical polishing (CMP), so that a contact window plug structure can be formed between the polysilicon metal gate structures and above the source / drain regions. After the second silicon dioxide layer is deposited, a bit line opening is formed that is self-aligned to the polysilicon gate structure adjacent to the silicon nitride cap, and the contact window between the polysilicon gate structure is inserted. One side of the plug structure can be exposed. A conductive layer is deposited and patterned over the second-deposited dioxide layer and in the bit line openings, so that a bit map connected to one side of the contact plug structure can be generated. Brief description: The purpose of the present invention and other advantages of the present invention can be combined with the accompanying drawings and detailed description of the invention to obtain the most complete. Figures 1B, 2, 3B, 4, 5B, 6B, 6C are displayed in a cross-section manner. ------------------------ Order Read the notes on the reverse side and fill out this page.) This paper size is in use ® Θ Family Standard (CNS) A 1 Specification (2〗 0 X 1; 97 issued) Printed by the Intellectual Property Office of the Ministry of Economic Affairs and Consumer Cooperatives 424302 '/ A, _B7__ 5. Description of the Invention (^) shows the key steps in the manufacturing process. The leg step is used to create a self-aligned interconnect structure connected to one side of the contact window plug structure. Figure IA, M'SA, 6A Betty shows the key steps in the process in a top view. These steps are used to create an interconnect structure that is self-aligned and connected to one side of the contact plug structure. Brief description of drawing number: 1 semiconductor substrate 2 shallow trench isolation area 3 inside the gate oxide layer of sand dioxide 4 polycrystalline silicon layer 5 metal silicide layer silicon nitride layer 13-15 polycrystalline silicon with silicon nitride cap Boot gate structure 11a Nitrided surface lib Thin nitrided surface 11c Nitrided sand gap wall 12 Sandy oxide layer 13-15 Self-shed quasi-contact window opening 16 Sandy oxide layer 17-bit line contact window opening 19, 20-bit line Structure 21 element active area 22 photoresistor 23 contact surface plug structure 5 I -------------! Equipment --- I ---- order, (Please read the precautions on the back before filling (This page) This paper standard is applicable to China® House Standard Rate (CNS) A 丨 Regulations (21〇X 297g t) 0 21 Five B5 Printed Description of Invention (jr) Details of Invention Explanation: This section will explain in detail how to connect an interconnect structure to one side of the contact window plug structure below it in a self-aligning manner. The invention will be described using an N-type field effect transistor (NFET). It must be noted, however, that the present invention can also be applied to P-type field effect transistors (PFETs). FIG. 1B shows a P-type semiconductor substrate 1 in a cross-sectional manner, which is composed of single crystal silicon with a lattice direction of < 100 >. FIG. 1A is a top view to show that Shallow Trench Isolation (STI) 2 is used for isolation and to define the active area 21 of the component. The shallow trench isolation area 2 is used The traditional lithography technique, coupled with an anisotropic reactive ion etching (RIE) step using Cl2 as an etchant, generates a f @ depth between 2000 and 4000 Angstroms (Angstroms) in the semiconductor substrate 1. Shallow trench. The photoresist used to define the location of the shallow trench was then washed away using the plasma oxygen ashing and careful cleansing steps. Then, low pressure chemical vapor deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD) was used to fill the aforementioned shallow trenches completely with silicon dioxide. As for the silicon dioxide that is not needed outside the shallow trench, it is removed by chemical mechanical polishing (CMP) or a selective reactive ion (RIE) step using CHF3 as an agent. This can form a shallow trench isolation region 2 filled with insulators as shown in FIG. 1B. Next, in an oxygen vapor environment, a thickness of 30 to 80 angstroms is formed by thermal growth, and is used as a second dioxide layer of the gate insulating layer 3. No. 6 nn-«1-1 1 I ί-I nm ^ i ^ lOJ n (Please read the precautions on the back before filling in this page) The paper size is in accordance with Chinese national standards (CNSM1 regulations (210 X 297) (Centi) 4243 Λ7 B7 5. After the description of the invention (t), a series of deposition steps are performed. The first is to use LPCVD to grow a multi-trace layer 4 with a thickness of 500 to 1500 angstroms. The multi-layer 4 can be itself. It is doped with impurities, that is, in the process of deposition, impurities such as arsenic or phosphorous are added to the environment filled with silane. The polycrystalline silicon layer 4 may also be originally free of impurities. Afterwards, arsenic or phosphorus ions are implanted into the polycrystalline silicon layer by ion implantation. After that, a metal silicide layer, such as tungsten (tungsten), is deposited with a thickness of 500 to 1500 angstroms by LPCVD. Silicide. Then use LPCVD or PECVD to deposit a nitrided sand layer with a thickness of 1500 to 3000 angstroms. Then use conventional lithography technology with reverse etch (RIE) step and use CF4 as the nitrided sand layer. XI contact etchant, Cl2 as metal sand 5 and polycrystalline silicon layer 4 of uranium [f, resulting in the cross-sectional view of FIG. 1B and the top view of FIG. 1A, with a nitrided sand cap and polycide (metal sand Crystal sand) gate structure 7-10 〇 After using oxygen electrolysis ashing method and careful wet cleaning steps, the photoresist used to define the polycrystalline silicide metal gate structure is washed away, and removed Crystal-sanded metal gate structure covering the insulating layer of the electrode. The Intellectual Property Bureau of the Ministry of Economic Affairs, the consumer cooperation, printed clothes ---------------- 1 ^ clothing --------- -Order (谙 Please read the notes on the back before filling in this page) Then, the micro-doped N-type source / drain region (not shown in the picture), using ion implantation, with an energy of 20 To 40KeV, the doping dose ranges from 1017 to 1019 atoms / cm2, and the semiconductor substrate region is not covered by the polysilicon metal gate structure. In FIG. 1B, there is a layer of nitride to earn Ua, which is used LPCVD or PECVD deposition, the thickness is between 300 and 600 angstroms. Then use an anisotropic reactive ion etching (RIE) step to CF, _ 7 This scale is suitable for Chinese κϋquasi (CNS) Al specifications C210 X 297 mm) 4243P at _ B? 5. Description of the invention (γ) / CHF3 is used as a thinning agent for thin nitride bumps. The ground is a silicon nitride layer 11a to produce a thin nitrided sand layer lib having a thickness reduced to 100 to 300 angstroms. The region of the thin nitrided sand layer 11b is located above the nitrided sand layer 6 above the semiconductor substrate 1 and between the polycrystalline silicon silicide gate structure. At the same time, nitrided silicon spacers 11 are formed on the sides of the polysilicon metal gate structure. These structures are illustrated in FIG. 2. Next, using the ion implantation method, a high N-type source / drain region (not shown in the picture) with an energy of 50 to 150 KeV and a doping amount of 1019 to 1021 atoms / cm2

To the extent that the implantation is not obscured by the polysilicon gate structure, or is not affected by the silicon nitride spacer 11c, the semiconductor substrate region 1. A silicon dioxide layer 12 having a thickness between 5000 and 10,000 angstroms is then deposited using TEOS (tetraethy orthosilicate) as a raw material by LPCVD or PECVD. In order to make the sand dioxide layer 12 have a flat surface, it is smoothed by a CMP step. The final result is shown in Figure 2. Figures 3A (top view) and 3B (cross-section) show the results after exposing a group of areas. These areas will be used to accommodate contact window plug structures made later, which can self-align to a polysilicon metal gate structure with a silicon nitride cap. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs * '1 clothing I .------------ i equipment -------- order · (Please read the precautions on the back before filling in this Page) The above results are first defined by the photoresist layer 22 to define the active region 21 of the device. The photoresist layer has a strip-shaped opening with the same size and position as the previous photoresist layer. The photoresist layer can be used as a photomask in the process. The selective reactive ion etching (RIE) step using C4FS as an etchant is used to wash away the dioxide layer 12 in the exposed area. The selection of 酵 J is about 10 oz. Of nitrogen dioxide. This allows this reactive ion etching (RIE) step to be etched to a thin thickness of 8 paper. This paper applies the Chinese National Standard (CNS). 297 mm) 02 A7 ________W_ V. Description of the Invention (F) When the nitrided sand layer is 1 lb, the uranium etching rate will be slowed down. Next, remove the thin nitrided sand layer lib with CH3F / 02 as the etchant. The female produced the Self-Aligned Contact (SAC) openings 13, 14 and 15 as shown in Figures 3A (top view) and Figure 3B (cross-sectional view). Here, the selectivity of etching using CH3F / 02 as a uranium etchant is about 5 to 1 for nitrided sand and dioxide for sand. The purpose of making a long opening in the photoresist layer 22 is to avoid encountering the alignment and critical image that would be encountered when traditionally making individual self-aligned contact window (SAC) openings. )The problem. Because in the traditional process, the tendency to reduce the width of polysilicon silicides will make it difficult to make a self-aligned contact window (SAC) opening even with a narrow photoresist pattern. In traditional processes, the openings of the self-aligned contact window (SAC) must be stacked on top of the polysilicon gate structure. However, in the present invention, a set of self-aligned contact window (SAC) openings can be combined together by using the strip-shaped openings on the photoresist, so that the traditional individual self-aligned contact window (SAC) openings can be reduced when making a traditional , Difficulty in lithography technology. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, I Consumer Cooperatives (Please read the precautions on the back before filling this page) After using the oxygen deashing method and careful wet cleaning steps to wash the light 22, wash it out and make self-alignment contact. In the window (SAC) openings 13-15, a contact window plug structure 24 is grown, which is a polycrystalline silicon silicide gate structure self-aligned to a nitrided sand top cover. The composition of the contact plug 24 may be polycrystalline silicon silicide or tungsten. Next, LPCVD is used to deposit contact window plugs with a thickness of 3000 to 6000 Angstroms, and the self-aligned contact windows (SAQ openings 13-15 are full. If polycrystalline silicon is used, the doping step is in the deposition process). , Add arsenic or phosphorus to the environment of silicon methane to achieve, and then use the CMP method to remove unwanted polycrystalline silicon (or remove, and at the same time remove the oxide cut layer 12, _ 9 This paper is applicable in China @ 国 揲 准(CJSS) 8 1 蚬 柊 (21〇J < 297 mm) 4243 02 A7 ___B7__ V. Description of the invention (5) Until the silicon nitride appears as ih 〇 So in the self-aligned contact window (SAC) opening 13-15 A conductive plug structure 24 is formed in the middle as shown in Fig. 4. A sand dioxide layer 16 having a thickness between 1000 and 2000 Angstroms is then deposited by LPCVD or PECVD. The raw material used here is still TEOS. A photoresist layer is placed as a photomask to form a bit line contact window opening 17 in the sand dioxide layer 16 using a reactive ion contact etching (RIE) method using CHF3 as an etchant. When the bit g contacts The window opening reaches the bottom, which is when the nitrided sand layer lib appears. The steps will stop. The opening Π may be down to the bottom, or it may be shallowly etched through the sand dioxide layer 12 at about 1500 to 3500 angstroms; the depth of its engraving to contact the side window contact plug structure 24 Principle. The etch rate of females using C4F8 / CO as the agent is about 10 to 1 whether it is silicon dioxide to silicon nitride or silicon dioxide to polycrystalline silicon. These steps will cause contact window plugs_ One side of 24 will be exposed. The results are shown in the top view of Figure 5A and the cross-sectional view of Figure 5B. In order to allow one side of 51 «» contact plug structure 24 to be exposed, the meter is deliberately removed. The line contact window opening 17 is superposed on the contact window plug structure 24. In this way, a part of the upper surface of the contact surface plug fiber 24 can be exposed in the rice line contact window opening 17. Figure 5A shows the bit line Contact window is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Port 17 is a polycrystalline silicon metal gate structure with self-alignment to the nitrided top cover. ° In the use of oxygen ash removal and careful wet cleaning steps, After the photoresist defining the bit line contact window opening 17 is washed away, a bit line interconnect structure 19'20 can be formed. The bit line contact window can be a polycrystalline sanded metal structure, including the following N-type (with impurities doped inside) polycrystalline ______ 10 This paper size applies the Chinese National Standard (CNS) Al regulations (210x297 gong) 4243 D2 V. Description of the invention () Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (Please read the precautions on the back before filling out this page) silicon layer, and a tungsten silicide layer on top. The connection structure of the bit line contact window may also be composed of cranes. The tungsten layer is located on an adhesive-barrier layer composed of titanium-nitride. Polycrystalline silicide metal with a thickness of 1500 to 2500 Angstroms is then deposited by LPCVD to completely fill the bit line contact window openings 17. As for the bit line interconnect layer composed of tungsten and having a thickness between 1000 and 2000 Angstroms, the bit line contact window opening 17 is completely filled again by using the LPCVD method or the RF sputtering method. To obtain. Next, using conventional lithography technology, combined with anisotropic and selective reactive ion engraving (RIE enamel) using Cl2 or SF6 / C12 (used by ugly) as the measuring agent, the bit line interconnect structure 19 and 20 were produced. The results of these steps are shown in Figure 6A (top view), Figure 6B and Figure 6C (cross-sectional view). Figure 6 also shows the wiring structure 20 and the contact window in the bit line. Between the plug structures 24, the contact window that we want to make is mainly Hi that appears with the mechanical contact structure 24. This female component is above the non-moving area and is in the bit line that is in contact with one side of the contact window plug structure. _ Structure * can reduce the area of the active area of the component, right > The design of making a one-bit line contact window directly on the contact window plug structure will require a larger active area of the element to accommodate the event The problem of mis-alignment. Figure 6C shows a cross-sectional view of an active area of a component that has neither a bit line contact window opening nor a bit line interconnect structure. As for defining a bit line The photoresist of the interconnect structure is oxidized to ash again When other inventions are particularly shown and mentioned about the content of the present invention, 'for those who are familiar with this technology, you should know that there are various designs. 11 This paper standard is applicable to S countries Standard (CNS) Al specification (7mm of LM0 X) Λ7 424302 _B7_ V. Changes in the description of the invention (i /) will not depart from the spirit of the invention and the scope of patent application. (Please read the note on the back first (Fill in this page again)

1 PI In — ^ 1- "-0'HI. ^ 1 n. ^ 1 I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 11 This paper size applies to Yin Guoyuan Home Standard (CNS) A 丨 specifications (210 X 297 malea)

Claims (1)

Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs C8 D8 6. Scope of Patent Application 1. A method for making interconnect structures on a semiconductor substrate, which includes the following steps: Provide silicon nitride on top of a gate insulation layer The gate structure enclosed by the gate structure, the first part of the gate structure surrounded by silicon nitride is located in the active area of the element on the semiconductor substrate, and the second part of the gate lion surrounded by nitrided sand is Isolation area, touch source / drain area; above the device moving area, the active area of the device is not covered by the first part of the gate structure surrounded by silicon nitride: A thin nitrided sand substrate is created between the enclosed gate structures. In the semiconductor substrate, a first opening is formed in the first insulating layer, the thin nitrided sand layer, and the aforementioned active area of the element to expose A group of first gate points of the gate structure surrounded by nitrided sand is exposed, and a source / drain region between the first part of the gate structure surrounded by the nitrided gate is exposed; / Draw A contact window plug structure is formed over the area to reveal the aforementioned first group of gate structures surrounded by silicon nitride, and the contact window plug structure is self-aligned to the first group by the nitride group Surrounded gate structure: A second opening is created in the second insulating layer and the first insulating layer to reveal a thin portion of the nitrided sand layer, and to expose the thin layer overlapping the insulating isolation area. Silicon dioxide layer area, and the second opening 13 (Please read the precautions on the back before filling this page)-Install -------- Order Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) A8 B8 C8 D8 4243 0 6. The scope of patent application is self-aligned and located in the second part of the gate structure surrounded by the aforementioned nitrided sand And; forming the aforementioned interconnect structure on the upper surface of the second insulation layer, the interconnect structure will fill the aforementioned second opening and be connected to one side of the aforementioned contact window fiber. 2. The method according to item 1 of the scope of the patent application, wherein the gate structure surrounded by the nitrided sand is a polycrystalline silicided metal structure, and the composition includes a silicidized crane layer with a thickness of 500 to 1500 angstroms and a A layer of polycrystalline sand with a thickness of 500 to 1500 angstroms under fi®, and includes a 1500 to 3,000 angstroms produced using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). A cap-like nitrided sand layer, and a nitrided spacer with a thickness of 50 to 800 angstroms. 3. The method according to item 1 of the scope of the patent application, wherein the thin nitrided sand layer is formed by using a low pressure chemical vapor deposition method (LPCVD is an enhanced chemical vapor phase ^^^ (PECVD) ^-the layer thickness is between 1500 to A 3000 angstrom nitrided sand layer was subsequently etched using an anisotropic reactive ionization method using CF4 / CHF3 as an etchant to reduce the thickness to between 100 and 300 angstroms. 4. As described in item 1 of the scope of patent application Method, wherein the first insulating layer is a silicon dioxide layer, and is manufactured by using a low pressure chemical surface deposition method (LPCVD) and a donkey plasma enhanced chemical vapor deposition method (PECVD), and the thickness is between 5000 and 10,000 angstroms. The method described in item 1 of the scope of patent application 'wherein the first opening is located in the aforementioned first insulating layer, using C4F8 as the toilet _ 14 _ This paper standard applies to Chinese National Standards (CNS) A4 regulations (210 X 297 mm) -----; -------- ^ -------- Order --------- Taste / (Please read the back first Please fill in this page before printing) Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 424M, ___g_ 6. The scope of the patent application is made by the anisotropic reactive ion etching (RIE) method. The saturation selectivity of silicon dioxide to silicon nitride is about 10 to 1. The first opening is in the aforementioned thin silicon nitride. The thin nitride gap layer is made after the formation of the layer, and the aforementioned thin nitride gap layer is made by using an anisotropic reactive ion etching (RIE) method using CH3F / 02 as an etchant. 5 to 1 〇6. The method according to item 1 of the patent application range, wherein the contact »« structure includes polycrystalline silicon having a thickness between 3000 and 6000 angstroms and produced by low pressure chemical vapor deposition (LPCVD) Sand layer, the polycrystalline sand layer is added with impurities such as arsenic or phosphorus in the environment of sand armored house in the process of ^ «. 7. The method as described in item 1 of the scope of patent application, wherein the contact_plug structure Including a tungsten layer having a thickness between 3000 and 6000 angstroms by a low pressure chemical vapor deposition (LPCVD) method. 8. The method as described in item 1 of the patent application scope, wherein the second insulating layer is dioxide Sand, using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemistry Made by vapor deposition (PECVD), with a thickness M between 1000 and 2000 angstroms. 9. The method according to item 1 of the scope of patent application, wherein the second opening is located on the second layer of insulation The first layer and the first insulating layer are produced by an anisotropic reactive ion etching (RIE) method using CHF3 as an etchant. If C4F8 / CO is used as the agent, the oxide sand or the sand will be oxidized. The selectivity of silicon to polycrystalline silicon is about 10 to 1. 10. The method according to item 1 of the scope of patent application, wherein the interconnect structure is formed of a polycrystalline silicon silicide layer, including a tungsten silicide layer located above, and an inner polycrystalline silicon layer located below. 15 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -----: —.—- t -------- Order --------- Taste (Please read the note on the back? Matters before filling out this page) OQ 8 8 99 ^ BCD 42i302 ^ VI. Scope of Patent Application · The method described in item 1 of the scope of patent application, where the interconnect structure is based on Tungsten is the foundation. Its composition includes a tungsten layer. Below it is a composite layer composed of titanium-titanium nitride. This layer is used as an adhesive barrier layer. 12, a method for fabricating a bit line interconnect structure on a semiconductor substrate, the bit line interconnect structure and a bit line contact window located in a hole of the bit line contact window. This method includes the steps of: forming a polycrystalline silicon silicide metal gate structure with a nitrided top cap in the aforementioned semiconductor substrate and the aforementioned shallow trench region filled with insulators; a nitrided sand layer; and using an anisotropic reaction The ion-etching (RIE) method removes a part of the nitrided sand layer between the polycrystalline silicon silicide metal gate structure with a nitrided top cap to obtain a nitrided sand layer, which is left over. In the area between the polycrystalline silicided metal gate structure with the nitrided top cap, good P is left untreated nitride between the polycrystalline sanded metal gate structure with the nitrided sand cap. Layer; in the active area of the device, the source / drain area is formed in the area not covered by the polycrystalline silicon silicide structure with the nitrided sand top cover; a layer of sand dioxide is sunk; A layer of sand dioxide and the silicon nitride layer A long contact window opening to expose the active area of the aforementioned elements in the semiconductor substrate, which includes exposing a group of polycrystalline silicon silicide metal gate structures with a nitrided sand top cover, and intervening nitride Source / drain region between polycrystalline silicon silicide metal gate structure of sand top cover; 16 paper size used in China National Standard (CNS) A4 specification (210 X 297 mm) ----- ^- --Γ --- t -------- Order --------- line (Please read the precautions on the back before filling this page) The Intellectual Property Bureau of the Ministry of Economic Affairs Employee Consumer Cooperative Press Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^^ 424302 C8 6. Application scope of patents: a polycrystalline sand layer; the polycrystalline sand layer is from the surface of the first dioxide sand layer, and the polycrystalline silicon nitride top cover The upper surface of the damascene metal gate structure is removed to produce a contact window plug structure located and self-aligned with the polycrystalline silicon silicide metal gate structure with the nitrided sand top cover. The polycrystalline silicide metal gate structure is exposed at In the long contact window opening, and the contact window plug is located in the source / Above the pole area; two layers of sand dioxide layer; among the second layer of sand dioxide layer and the first layer of sand dioxide layer, opening the aforementioned bit line contact window hole to expose the contact window plug structure One side is used to form the aforementioned bit_window plug structure, and a part of the aforementioned thin nitrided surface is exposed, and a part of the thin nitrided sand layer is located in the shallow trench area of the object surface Above, and the bit line contact window hole is self-aligned and is located between the two gate structures with the nitrided sand top cover; a polycrystalline silicon face layer is missing to completely fill the aforementioned bottle line Contacting the window hole; and patterning the polycrystalline silicided metal layer to generate the aforementioned bit line interconnect structure to contact one side of the steel plug structure with the bit line located in the bit line contact window hole Phase contact. 13. The method according to item 12 of the scope of the patent application, wherein the polycrystalline silicon silicide metal gate structure with a nitrided sand top cover includes an upper part, which is manufactured by the LPCVD method and has a thickness of 500 to 1500 angstroms. The tungsten silicide layer, which also contains one ^ underneath, is made by LPCVD and has a thickness of 17 papers. It is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 cm) -----;-^ --- -'^ -------- Order --------- Line .. {Please read the notes on the back before filling this page) 4243 Ο ^ g_ 6. The scope of patent application is between 500 and 1500 Angstroms of internally doped N-type polycrystalline silicon layer, including a polycrystalline silicon silicide layer with a nitrided sand cap, is a low pressure chemical vapor deposition method (LPCVD) or a plasma enhanced chemical vapor deposition method (PECVD). ) Made with a thickness between 1500 and 3000 Angstroms. 14. The method according to item 12 of the scope of patent application, wherein the thin gasified sand layer has a thickness between 100 and 300 angstroms, and is LPCVD or plasma-enhanced chemistry. Manufactured by vapor deposition (PECVD), first deposit a thickness of 300 to 600 angstroms, and then use anisotropic reactive ion etching (RIE) with CF4 / CHF3 as a uranium etchant to make it thinner. The method according to item 12, wherein the first layer of sand dioxide layer is made by LPCVD or PECVD, and the thickness is between 5000 and 10,000 Angstroms. 16. The method according to item 12 in the scope of patent application, wherein The punched contact window opening is made for the first time in the aforementioned first layer of sand dioxide layer. It is made by the anisotropic reactive ion etching (RIE) method using C4F8 as an etchant. The selectivity of _j is about 10 to 1, and then formed in the aforementioned thin nitrided layer. The silicon nitride is produced by an anisotropic reactive ion etching (RIE) method using ch3f / o2 as the etchant. The etch selectivity for silicon dioxide is about 5 to 1017. As described in item 12 of the scope of patent application The method, wherein the contact window plug structure includes a polycrystalline silicon layer having a thickness between 3000 and 6000 angstroms and manufactured by a low pressure chemical vapor deposition (LPCVD) method, and the polycrystalline sand layer is in a sand box environment during the deposition process. Add arsenic or phosphorus impurities to it to make it doped with impurities. 18. The method described in item 12 of the scope of patent application, wherein the second layer of dioxin 18 paper is again applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) Packing ---- One-port · III ί Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 83SS ASSCD 424302 It is made by Low Pressure Chemical Surface Method (LPCVD), which has a thickness between 1000 and 2000 Angstroms. 19. The method according to item 12 of the scope of the patent application, wherein the bit line contacting the window hole opening is made in the aforementioned second layer of sand dioxide layer and the aforementioned first layer of dioxide surface, using C4F8 / CO is an anisotropic reactive ion etching (RIE) method for the etchant. The saturation selectivity of sand dioxide to nitriding or sand dioxide to polycrystalline is about 10 to 10.20. The method according to item Π of the patent application scope, wherein the interconnect structure of the bit line is formed by a polycrystalline metallized metal layer with a thickness between 1500 and 2500 Angstroms, including a tungsten silicide layer located above And a N-type polycrystalline sand layer with an internal dimension change located below. 21. The method according to item 12 of the scope of patent application, wherein the interconnect structure of the bit line is based on tungsten and has a thickness between 1000 and 2000 angstroms, including a tungsten layer, and a A titanium-titanium nitride composite layer is used as an adhesion barrier layer. (Please read the notes on the back before filling out this page) Printed by the Consumers ’Cooperative of the Ministry of Intellectual Property Bureau This paper is sized to the Chinese National Standard (CNS) A4 (210x 297 mm)