TW468264B - Method for preventing Al-Si-Cu interconnect from protruding through via hole - Google Patents

Abstract

The present invention discloses a method for forming a metal interconnect in the semiconductor manufacturing process. The method comprises providing a barrier layer on a semiconductor substrate; then, depositing an Al-Si-Cu alloy layer on the barrier layer; next, depositing an Al-Cu alloy layer on the Al-Si-Cu alloy layer, wherein the Al-Si-Cu alloy layer and the Al-Cu alloy layer are referred as a first metal layer; then, performing a pattern transfer to the barrier layer and the first metal layer; next, providing a via hole on the first metal layer and performing a high-temperature baking process; and finally, filling a second metal layer into the via hole.

Description

468264 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to the formation of a metal interconnect in a semiconductor process, and in particular to the formation of an aluminum-silicon-copper metal interconnect in a semiconductor process Line approach. 5-2 Background of the Invention: When the integration degree of integrated circuits increases, so that the surface of the wafer cannot provide enough area to make the required interconnects, in order to match the increased interconnects after the reduction of metal oxide semiconductor transistors Line requirements, the design of two or more metal layers, have gradually become a necessary method for many integrated circuits. In particular, some products with more complex functions, such as microprocessors, even require four or five metal layers to complete the connection between the various components in the microprocessor. Basically, the production of this multi-metal interconnect (M u 1 t i 1 e v e 1 Interconnects) is started after the body of the metal oxide semiconductor transistor has been completed, so it can be regarded as an independent semiconductor process.

Page 4 Λ6 8 26 4 ⑵ Now the super large electrical properties are good because aluminum has aluminum and has a certain conductor industry. As a volume of copper, the aluminum alloy is connected to each other by Barrier or titanium tungsten. V. The description of the invention I Lu is caused by it . However, the silicon pair is therefore in a semi-alloy, with a contact resistance of 0.5% in order to prevent and reduce the barrier layer (titanium composite film-type integrated body, and the electro-transition solid state of the silicon-copper composite sand) Layer: The most commonly used conductive material for other material circuits, due to its good adhesion to the silicon dioxide layer (Electromigration), the problem of solubility (Solid Solubility), using aluminum conductors containing copper, or both copper and silicon, As common with 1% by weight silicon gold

Al-Si-Cu Alloy). In addition, a spiking phenomenon occurs at the contact interface. A layer of conductive material is usually added between aluminum alloy and silicon. The common one is titanium / nitriding. Refer to the first figure, which contains 1% silicon and 0% by weight in the traditional semiconductor industry. Disadvantages of a 5% copper copper sand alloy as its metal interconnect. First, a pattern-transferred barrier layer 140 and an aluminum-silicon-copper metal interconnect 14 2 are provided on a semiconductor substrate 100. Then, an internal metal dielectric 1 2 0 is formed by a chemical vapor deposition method, and a via hole 122 is formed by a via shoe (V i a E1: c h i n g). Next, a high temperature baking process is performed before depositing another layer of metal (not shown in the first figure). When the size of the metal interlayer hole 1 2 2 is about 0.6 to 丨 microns, after the high-temperature baking process, the aluminum-silicon-copper alloy is easy to interconnect the aluminum-silicon-copper metal due to its melting point and stress. The line 1 4 2 protrudes upward from the vias 1 2 2. Will cause the deposition of another layer of metal (not shown in the first picture) to cause more serious protrusions, making the other layer of metal prone to bridging after etching, affecting the metal interconnection system

〇 8 26 4 V. Description of the invention (3) Process. 5-3 Purpose and summary of the invention: In view of the above-mentioned background of the invention, the traditional use of aluminum-silicon-copper metal interconnects has the disadvantage of serious protrusions in the interlayer holes, but if the aluminum-copper alloy is used entirely when the metal interconnects are not Due to this disadvantage, in order to preserve the advantages of using aluminum-silicon-copper metal interconnects, the present invention deposits an aluminum-silicon-copper metal layer, deposits a copper alloy layer, and uses them as metal interconnects. An object of the present invention is to use a thin aluminum-copper metal layer on the aluminum-silicon-copper metal layer to solve the shortcoming of severe protrusions in the interlayer holes caused by a single aluminum-silicon-copper metal interconnect. According to the above-mentioned object, the present invention provides a method for forming a metal interconnect in a semiconductor process. The method at least includes providing a barrier layer on a semiconductor substrate. Then, an aluminum silicon copper alloy layer is deposited on the barrier layer. Next, an IS copper alloy layer is deposited on the Mingshixi copper alloy layer. The aluminum-silicon-copper alloy layer and the aluminum-copper alloy layer are collectively referred to as a first metal layer. Continuing, a pattern transfer is performed on the barrier layer and the first metal layer. Next, a via hole is provided in the first metal layer and a high temperature baking process is performed. Finally, a second metal layer is filled in the via hole.

468264 V. Description of the invention (4) 5-4 Detailed description of the invention: The semiconductor design of the present invention can be widely used in many semiconductor designs, and can be made using many different semiconductor materials. When the present invention is a preferred embodiment When explaining the method of the present invention, those skilled in the art should recognize that many steps can be changed, and materials and impurities can be replaced. These general replacements undoubtedly do not depart from the spirit and scope of the present invention. Secondly, the present invention is described in detail with a schematic diagram as follows. In the detailed description of the embodiments of the present invention, the cross-sectional view showing the semiconductor structure will not be partially enlarged according to the general scale in the semiconductor manufacturing process for the purpose of explanation. . In addition, the actual production should include three-dimensional space dimensions of length, width and depth. Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can also be widely implemented in other embodiments, and the scope of the invention is not limited, which is subject to the scope of subsequent patents. The present invention mainly provides the use of an aluminum-silicon-copper material as the interconnect to solve the phenomenon that the aluminum-silicon-copper material is protruded from the interlayer hole when the high-temperature baking is continued before the next layer of metal deposition, especially the width of the interlayer hole is in the range of 0. 6 to 1 micron. The method provided by the present invention at least includes providing a barrier layer on a semiconductor substrate. Then, deposit a copper alloy layer on the barrier layer. Then, sink again

4 6 8 26 4 V. Description of the invention (5) An aluminum-copper alloy layer is laminated on the aluminum-silicon-copper alloy layer. The aluminum-silicon-copper alloy layer and the copper copper alloy layer are referred to as a first metal layer. Continuing, a pattern transfer is performed on the barrier layer and the first metal layer. Next, a via hole is provided in the first metal layer and a high temperature baking process is performed. Finally, a second metal layer is filled in the via hole. The procedures mentioned above and the steps performed in the appropriate state will be described in detail in the following second to sixth figures. Referring to the second figure, a barrier layer 40 is on a semiconductor substrate 10. This barrier layer 40 is used to prevent the contact between the aluminum alloy layer and the silicon from spiking and to reduce the contact resistance between them. Common materials are titanium / titanium nitride composite film or titanium tungsten. First, a titanium substrate having a thickness of about 100 to 500 angstroms is deposited by direct current (DC) sputtering. Then, a thickness of about 500 to 1500 angstroms is deposited on the titanium by reactive direct current (DC) sputtering or nitriding after the deposition of titanium. Referring to the third figure, an aluminum-silicon-copper alloy layer 42 is deposited on the barrier layer 40. An aluminum-silicon-copper alloy (eight 1-Si-Cu Alloy) containing 1% by weight silicon and 0.5% by weight copper is used here, and the content of this ratio can prevent both "spikes" and "electric shift" at the same time. Wait for two common failure modes of aluminum metal wires and strengthen the reliability of aluminum wires. Sputtering is often used to deposit aluminum-silicon-copper alloy layer 4 2. In order to increase the gold deposit of the metal layer. 1 Mb ο Μ When ί is appropriate to actuate the film to move the crystal ㈣ ^ Normal quality, material strength, it can cover or cover the step table silicon in Jiazi than the original genus

Page 8 468264 5. In the description of the invention (6), a pattern transfer is performed on the aluminum-silicon-copper alloy layer 42 and the aluminum-copper alloy layer 44. Here, a Ming steel alloy containing 0 to 0.5% by weight copper is used. The melting point of the copper alloy is higher than that of the aluminum-silicon-copper alloy, so it is less prone to deformation after baking at high temperatures. It is also common to use an extinction: bond method to deposit a copper alloy layer 4 4. The aluminum-silicon-copper alloy layer 4 2 and the aluminum-copper alloy layer 4 4 are collectively referred to as a first metal layer. The aluminum-copper alloy layer 44 is used to avoid deformation protrusions caused by high-temperature baking, and the aluminum-silicon-copper alloy layer 42 is a main metal interconnect. The proportion of silicon-copper in the aluminum-silicon-copper alloy layer 42 is to prevent " spikes " and " electric shift n " and to enhance the reliability of aluminum wires. Therefore, the first metal layer is mainly an aluminum-silicon-copper alloy layer 4 2 The thickness range of the aluminum-silicon-copper alloy layer 42 is about 60% to 85% of the thickness of the first metal layer, and the preferred thickness range is about 80% to 85% of the thickness of the first metal layer. The thickness range of the aluminum-copper alloy layer 44 is about 15% to 40% of the thickness of the first metal layer, and the preferred thickness range is about 15% to 20% of the thickness of the first metal layer. Figure 5 provides a dielectric hole 22 on the first metal layer and a high temperature baking process. First, a dielectric layer 20 is deposited on the first metal layer and the semiconductor substrate 10 by a chemical vapor deposition method. Then, the lithography process is performed to remove a part of the dielectric 20 to expose the first metal layer to form a via hole 22. After that, in order to make the next deposited metal layer have better step coverage, a high temperature baking is performed. Baking process. At this time, after the high-temperature baking process, the first metal layer in the interlayer hole 2 2 can avoid the protrusion phenomenon, It does not affect the subsequent process.

4 6 B 26 4 V. Description of the invention (7) Referring to the sixth figure, a second metal layer 4 6 is filled in the interlayer hole 2 2. A second metal layer is deposited on the dielectric layer 20 and inside the via 22 2 by blanket deposition. Then, the second metal layer 46 overlying the dielectric layer 20 is removed by a dry-contact etch method, leaving only the second metal layer 46 in the dielectric hole 22. To sum up, the present invention mainly consists of using an aluminum-copper alloy on an aluminum-silicon-copper alloy. In addition to retaining the advantages of using Mingshixi copper alloy as the metal interconnect, it also avoids the protrusion of the aluminum-silicon-copper alloy in the interlayer holes after high temperature baking. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

Page 10 46 8 264 Brief description of the diagram The first diagram is a schematic cross-sectional view of a conventional aluminum-silicon-copper metal interconnect. The second figure is a schematic diagram of the process of forming other metal interconnections according to the technology disclosed in the present invention. The third figure is a schematic diagram of a faceted process for forming a metal interconnect according to the technology disclosed in the present invention. The fourth figure is a schematic cross-sectional flow chart of forming a metal interconnect according to the technology disclosed in the present invention. The fifth figure is a schematic cross-sectional flow chart of forming a metal interconnect according to the technology disclosed in the present invention. The sixth figure is a schematic cross-sectional flow diagram of forming a metal interconnect according to the technology disclosed in the present invention. Representative symbols of the main parts: 10 substrate 20 dielectric layer 22 via hole 40 barrier layer 4 2 aluminum silicon copper alloy layer

4 b 8 26 4 Brief description of the drawings Layer by layer Metal Alloy Copper 2 Aluminum 4 6 4 4 Ι111111! Ι Page 12

Claims (1)

468264 VI. Application for patent application 1. A method for forming a metal interconnect in a semiconductor process, the method at least comprises: providing a barrier layer on a semiconductor substrate; depositing an aluminum-silicon-copper alloy layer on the barrier Depositing an aluminum-copper alloy layer on the aluminum-silicon-copper alloy layer, wherein the aluminum-silicon-copper alloy layer and the aluminum-copper alloy layer are collectively referred to as a first metal layer; the barrier layer and the A pattern transfer is performed on the first metal layer; a via hole is formed on the first metal layer; a high-temperature baking process is performed; and a second metal layer is filled in the via hole. 2. The method according to item 1 of the scope of patent application, wherein the above barrier layer includes at least a titanium / titanium nitride composite film and Hehua Ito. 3. The method according to item 1 of the scope of patent application, wherein the aluminum-silicon-copper alloy layer is an ingot copper alloy containing 1% by weight and 0.5% by weight of copper. Page 13 46 8 26 4 VI. Scope of patent application The preferred thickness range of the layer is about 80% to 85% of the thickness of the first metal layer. 7. The method of claim 1 in which the thickness range of the above-mentioned aluminum-copper alloy layer is about 15% to 40% of the thickness of the first metal layer. 8. The method according to item 7 of the patent application range, wherein the preferred thickness range of the above-mentioned aluminum-copper alloy layer is about 15% to 20% of the thickness of the first gold chip layer. 9. The method according to item 1 of the patent application range, wherein the width of the above-mentioned via hole is about 0.6 to 1 micron. 10. A method of forming an aluminum metal interconnect in a semiconductor process, the method at least comprises: providing a barrier layer on a semiconductor substrate; depositing an aluminum-silicon-copper alloy layer on the barrier layer, The above aluminum-silicon-copper alloy layer is a sau-silicon-copper alloy containing 1% by weight of hard and 0.5% by weight of copper; an aluminum-copper alloy layer is deposited on the aluminum-silicon-copper alloy layer, wherein the above-mentioned aluminum broken copper alloy layer The copper content ranges from about 0% to 0.5% by weight, and the Mingshixi copper alloy layer and the Ming copper alloy layer are collectively referred to as a first metal layer; the barrier layer and the first metal layer Performing a pattern transfer; forming a via hole on the first metal layer; performing a high temperature baking process; and filling a second metal layer in the via hole. Page 14 4 6 8 26 4 6. Scope of patent application 11. The method according to item 1 of the scope of patent application, wherein the above barrier layer includes at least a chitin / titanium nitride composite film and a crane. 12. The method according to item 10 of the scope of patent application, wherein the thickness of the above aluminum-silicon-copper alloy layer ranges from about 60% to 85% of the thickness of the first metal layer. 13. According to the method of claim 12 in the scope of patent application, the preferred thickness range of the aluminum-silicon-copper alloy layer mentioned above is about 80% to 85% of the thickness of the first metal layer. 14. The method according to item 10 of the patent application range, wherein the thickness of the aluminum-copper alloy layer is in the range of about 15% to 40% of the thickness of the first metal layer. 15. The method according to item 14 of the scope of patent application, wherein the preferred thickness range of the above-mentioned aluminum-copper alloy layer is about 15% to 20% of the thickness of the first metal layer. 16. The method according to item 10 of the patent application range, wherein the width of the above-mentioned via hole ranges from about 0.6 to 1 micrometer. 1 7. A method for forming an aluminum-silicon-copper metal interconnect in a semiconductor process, the method at least comprising: providing a barrier layer on a semiconductor substrate; depositing a layer containing 1% by weight silicon and 0.5% A copper-aluminum-silicon-copper alloy layer is deposited on the barrier layer; a copper alloy layer having a copper content ranging from about 0% to 0.5% by weight is deposited on the barrier layer. Page 15 t 〇8 26 4 VI. Application scope The patent on the aluminum-silicon-copper alloy layer, wherein the aluminum-silicon-copper alloy layer and the aluminum-copper alloy layer are collectively referred to as a first metal layer, and the stone and copper alloy The thickness of the layer ranges from about 60% to 85% of the thickness of the first metal layer and the thickness of the aluminum-copper alloy layer ranges from about 15% to 40% of the thickness of the first metal layer; Performing a pattern transfer with the first metal layer; forming a via hole on the first metal layer, wherein a width of the aforementioned via hole ranges from about 0.6 to 1 micron; performing a high temperature, baking process; and A second metal layer is filled in the via hole. 18. The method according to item 17 of the scope of patent application, wherein the above barrier layer contains at least a titanium / titanium nitride composite film and titanium crane. 19. According to the method of claim 17 in the scope of patent application, the preferred thickness range of the above-mentioned aluminum-silicon-copper alloy layer is about 80% to 85% of the thickness of the first metal layer. 20. The method according to item 17 of the scope of patent application, wherein the preferred thickness range of the above-mentioned aluminum-copper alloy layer is about 15% to 20% of the thickness of the first metal layer. Page 16