6 6 67 ^. 44i>6tw i.dac/006 A7 經濟部智慧財產局員工消費合作杜印製 五、發明説明（f ) 本發明是有關於一種積體電路元件之製作方法，且特 別是有關於一種晶片上對準標記（Alignment Mark)架構之製 作方法。 微影（PhotoHthography)是將半導體元件所需的圖案 (Pattern)，轉移到晶片表面的一種製程技術，是製造半導 體元件成敗與否的關鍵步驟，故在半導體製程中佔有舉足 輕重的地位。由於積體電路技術發展快速，半導體產品的 細微線路圖案愈趨複雜，所需的光罩數量也越來越多。爲 使光罩的圖案能夠正確轉移到晶片上，於製程中每次執行 光阻(Photoresist)曝光之前，必須先做好各層之間的對準， 否則將產生不當的圖案轉移，進而導致整個晶片報廢。 在半導體製程中，晶片對準之方法是利用晶片邊緣之 V型凹槽（Notch)進行晶片定位，並在晶片之對準標示區形 成與光罩對應之對準標記。再利用對準標記使光波產生繞 射圖形，並爲對準感應器（Alignment Sensor)所接收，而達 到晶片對準之目的。 然而，在進行多重內連線製程時，完成每一層金屬連 線後，都要於其上方沈積介電層，並在介電層中形成接觸 窗或介層窗開口，以定義金屬插塞位置。接著在介電層上 方形成金屬層，且塡滿接觸窗或介層窗開口，再以化學機 械硏磨法去除介電層上方之部分金屬層，將晶片表面平坦 化，並形成金屬插塞。然後才能進行下一層金屬連線的製 作。 隨著沈積次數的增加，對準標記將爲晶片對準標示區 3 本紙張尺度適用中國國家標率（CNS ) A4規格（210X297公釐） -----------欢！ (請先閲讀背面之注意事項再填寫本頁) ()6 6 7 8 A7 B7 4406t w t\d〇c/Oi)6 五、發明説明（λ ) ^in n n ! n I (請先閲讀背面之注意事項再填寫本頁) 上方之膜層所覆蓋’使得對準檫記失去其階梯高度（Step Height)及輪廓特徵’導致所產生之繞射現象不夠明顯；而 且構成膜層之材料不同’其反射率及折射率亦不同。所以， 上述追些原因會造成對準is號（Alignment signal)微弱，或 雜訊比率（Noise RaUo)過大’使對準感應器無法偵測到適 當的對準信號進行辨別’而導致對準失誤(Misallgnment0& 象發生，造成圖案的不當轉移。 因此本發明提供一種對準標記架構之製作方法，使對 準標示區上僅覆有透明之介電材料，以利各材料層間準確 對位，防止晶片之主動區(Active Area, AA)發生對準失誤； 使導線層與閘極層之間具有安全間距（Guard Band) ’並以 介電材料包覆閘極，防止因金屬與多晶砂接觸而發生剝離 現象，抑制對準標示區內產生殘留物（氮化物、金屬等）影 響元件品質。 經濟部智慧財產局8工消費合作社印製 根據本發明之上述及其他目的，提出一種對準標記架 構之製作方法，首先提供半導體基底，其上包括具有主動 區之元件區與具有對準標記的對準標示區，且元件區之高 度高於對準標示區。然後於主動區上形成圖案化之罩幕 層，並在主動區之周緣形成用以隔離元件之溝渠，再於基 底上形成介電材料層，以塡滿溝渠與對準標記°移除部份 介電材料層，於溝渠中及對準標示區上，分別形成隔離介 電層與底部介電層。剝除罩幕層之後，於主動區上形成半 導體元件。其次在基底上形成平坦化之介電層，然後於主 動區h形成導線。其中導線與半導體元件是由介電層所區 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 ：i 6 6 7 8 44061Λ\ Γ doc/006 A7 B7 五、發明説明（3 ) 隔，且導線位於半導體元件之上，而導線與對準標示區之 距離大於元件與對準標示區之距離。淸除對準標示區內介 電材料以外之膜層，避免其他材料殘留，並防止對準失誤， 以利後續製程之進行；使用介電層包覆元件，可杜絕金屬 與元件直接接觸，抑制於後續製程可能產生之剝離現象。 以提高半導體元件之良率與品質。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A圖至第1H圖繪示依照本發明之較佳實施例，一 種對準標記架構之製作流程的剖面示意圖。 圖式之標記說明： 100 :基底 10 2 :兀件區 104 :對準標示區 106:主動區 108 :對準標記 110、110a :罩幕材料層 112 :溝渠 114、114a、114b ' 118 :介電層 116、丨20 :導電層 116a ··元件 12.0a :導線 5 (請先鬩讀背面之注意事項再恭寫本頁)6 6 67 ^. 44i > 6tw i.dac / 006 A7 Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. Du V. Description of the invention (f) The present invention relates to a method for manufacturing integrated circuit components, and in particular A manufacturing method of an alignment mark (Alignment Mark) structure on a wafer. PhotoHthography is a process technology that transfers the pattern required by a semiconductor device to the surface of the wafer. It is a key step in the success or failure of manufacturing a semiconductor device, so it plays an important role in the semiconductor manufacturing process. Due to the rapid development of integrated circuit technology, the fine circuit patterns of semiconductor products have become more complex, and the number of photomasks required has also increased. In order for the mask pattern to be correctly transferred to the wafer, the alignment between the layers must be done before each photoresist exposure in the manufacturing process, otherwise improper pattern transfer will occur, which will cause the entire wafer. scrapped. In the semiconductor manufacturing process, the method of wafer alignment is to use a V-shaped groove (Notch) on the edge of the wafer to position the wafer, and form an alignment mark corresponding to the photomask in the alignment mark area of the wafer. The alignment mark is then used to generate a diffraction pattern of the light waves, which is received by the alignment sensor and achieves the purpose of wafer alignment. However, in the multiple interconnection process, after each layer of metal connection is completed, a dielectric layer must be deposited thereon, and a contact window or a dielectric window opening must be formed in the dielectric layer to define the position of the metal plug. . Next, a metal layer is formed above the dielectric layer, and the contact window or the opening of the dielectric window is filled. Then, a part of the metal layer above the dielectric layer is removed by chemical mechanical honing, the surface of the wafer is flattened, and a metal plug is formed. Only then can the next metal connection be made. As the number of depositions increases, the alignment mark will be the wafer alignment mark area. 3 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) ----------- Huan! (Please read the notes on the back before filling this page) () 6 6 7 8 A7 B7 4406t wt \ d〇c / Oi) 6 V. Description of the invention (λ) ^ in nn! N I (Please read the back Note that please fill in this page again.) The film layer on top of it makes the alignment note lose its Step Height and contour features, which causes the diffraction phenomenon is not obvious enough; and the materials constituting the film layer are different. Reflectivity and refractive index are also different. Therefore, the above reasons may cause the alignment signal to be weak, or the noise ratio (Noise RaUo) may be too large, which will cause the alignment sensor to fail to detect the proper alignment signal for discrimination. (Misallgnment0 & phenomenon occurs, resulting in improper transfer of the pattern. Therefore, the present invention provides a method for making an alignment mark structure, so that the alignment mark area is covered with only transparent dielectric material, so as to facilitate accurate alignment between the material layers and prevent Misalignment occurs in the active area (AA) of the chip; the guard band is provided between the wire layer and the gate layer; and the gate is covered with a dielectric material to prevent contact between the metal and the polycrystalline sand The peeling phenomenon occurs, and the residues (nitrides, metals, etc.) in the alignment mark area are inhibited from affecting the quality of the components. The manufacturing method of the structure firstly provides a semiconductor substrate including an element region with an active region and an alignment mark region with an alignment mark, and the element region The height is higher than the alignment mark area. Then a patterned mask layer is formed on the active area, and a trench for isolating components is formed on the periphery of the active area, and then a dielectric material layer is formed on the substrate to fill the trench. And the alignment mark °, removing a part of the dielectric material layer, and forming an isolation dielectric layer and a bottom dielectric layer in the trench and the alignment mark area, respectively. After stripping the mask layer, a semiconductor element is formed on the active area. Secondly, a planarized dielectric layer is formed on the substrate, and then a conductive line is formed in the active area h. The conductive line and the semiconductor element are formed by the dielectric layer. 4 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). ) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs: i 6 6 7 8 44061Λ \ Γ doc / 006 A7 B7 V. Description of the invention (3), and the wire is located on the semiconductor element, and the wire and the alignment mark area The distance is greater than the distance between the component and the alignment mark area. 膜 Film layers other than the dielectric material in the alignment mark area, to avoid the remaining of other materials, and to prevent misalignment, so as to facilitate subsequent processes; use dielectric The layer-coated element can prevent direct contact between the metal and the element, and can suppress the peeling phenomenon that may occur in subsequent processes. In order to improve the yield and quality of the semiconductor element, in order to make the above and other objects, features, and advantages of the present invention more obvious It is easy to understand. The preferred embodiments are described in detail below in conjunction with the accompanying drawings. The brief description of the drawings is as follows: Figures 1A to 1H illustrate a preferred embodiment according to the present invention. The cross-sectional schematic diagram of the manufacturing process of the mark structure. The mark description of the diagram: 100: substrate 10 2: element area 104: alignment mark area 106: active area 108: alignment mark 110, 110a: mask material layer 112: trench 114, 114a, 114b '118: Dielectric layer 116, 20: Conductive layer 116a · Element 12.0a: Wire 5 (Please read the precautions on the back before writing this page)
*1T 本紙張尺度適用中國國家標準（CNS )人4規格（210X29?公釐） 67 δ r.vlOii/OOi· A7 B7 五、發明説明（γ) D ’·元:件與對準標示區之距離 D’ ：導線與對準標示區之距離 Η :階梯高度 溝渠深度 寶施例 請参照第1Α圖至第1Η圖，其所繪示的是依照本發明 之較佳實施例，一種對準標記架構之製作流程的剖面示意 圖。 如第1Α圖所示，首先提供半導體基底丨〇〇，例如是矽 晶圓（Wafer)等，其中分別具有元件區102及對準標示區 iOO而元件區102之高度高於對準標示區丨〇4，元件區102 與對準標示區104之間高度差所形成之階梯高度爲Η。在 元件區102中還具有用以製作元件之主動區106*對準標 示區104中則具有宽度約爲8微米(Micron)之對準標記 10S。然後在基底100上形成覃幕材料層1丨0，其材質例如 是氮化矽等，彤成之方法則包括化學氣相沈積法(Chemical Vapor Deposition, CVD)等 β 經濟部智怂財4垮資工消费合作杜印災 其次，請參照第1B圖，對第丨A圖中之罩幕材料層1丨0， 進行微影、蝕刻等製程將其圖案化，移除部份罩幕材料層* 形成覆蓋主動區丨06之罩幕層丨」0a，並將位於對準標示區 1〇4的部份基底100曝露出來。接著以罩幕餍U〇a爲蝕刻 罩幕，定義元件區102之基底丨00，於主動區ί〇6的周緣’ 形成用以隔離後續將形成之元件的溝渠112,例如是淺溝 渠隔離結構中以非等向性飽刻方法般成之溝渠等其中溝 6 本紙張尺度通用中阑國家標準（CMS ) Λ4現格（2丨ΟΧ 公嫠） 4 6 6 6 7 b A7 4 〇 (¾ j t' cJ 0 c / 0 0 6 五、發明説明（f) 渠112之深度爲Η’，位於對準標示區1Q4之對準標記丨卯2 的深度與約等於溝渠深度Η，，而階梯高度Η亦約等於溝> 渠深度Η’。 繼續參照第1Β圖，於表面覆有圖案化之罩幕層u〇t 的基底100上’依序形成襯氧化層(未顯示於圖中）及初期.. 介電層U.4’並將由絕緣材料構成之初期介電層114塡滿 溝渠112及對準標記1〇8。其.中形成襯氧化層之方法例如 楚熱氧化法，而製作初期介電層114之方法包括化學氣相 沈積法等’例_如是吊壓化學氣相沈積（APCVD )法或低壓 化學氣相沈積（LPCVD)法等，而初期介簞層之材質包括 氧化矽、硼磷矽玻璃等，其厚度則約爲8000埃(Angstrom) > 续濟部智总財產馬员4消费合作社印說 請參照第1C圖’以罩幕餍li〇a爲終止層，移除部份 初期介電層U4，在元件區102之溝渠112中形成隔離介 電層U4b，在位於對準標示區丨〇4之部份基底1〇〇上形成 底部介電層lUae其中移除部份由絕緣材料構成之初期介 爾餍U4的方法，包括進行回蝕刻(Etching Back)，例如等 向性触刻等，或者是化學機械硏磨法(Chemica】 Mechanical PoUshing，CMP)，而所形成之底部介電層U4a之厚度約爲 4000 埃。 接著如第1D圖所示，將第1C圖中作爲終止層的置幕 …層110a移除，使位於主動區1〇6之部份基底\〇〇曝露出來。 例如是使闬熱磷酸溶液以濕式漫潰(Wet D丨p)方式，移除材 質爲氮化矽之眾幕層ll〇a。再於基底100上形成導電層 116，其材質包括多晶矽、金屬等導電材料，形成之方法 ,Γ ___ •一 I--* 太錄认通料 ( CNS ) ( 2)ox297公;¢.) 67* 1T This paper size is applicable to China National Standard (CNS) Person 4 specification (210X29? Mm) 67 δ r.vlOii / OOi · A7 B7 V. Description of the invention (γ) D '· Yuan: The part and the alignment mark area Distance D ': the distance between the lead and the alignment mark area Η: step height ditch depth treasure For an example, please refer to Fig. 1A to Fig. 1, which shows an alignment mark according to a preferred embodiment of the present invention. A schematic cross-sectional view of the fabrication process of the framework. As shown in FIG. 1A, a semiconductor substrate is first provided, such as a silicon wafer (Wafer), which has a device region 102 and an alignment mark region iOO, respectively, and the height of the device region 102 is higher than the alignment mark region. 〇4, the step height formed by the height difference between the element region 102 and the alignment mark region 104 is Η. In the device region 102, there is also an active region 106 * for making the device. The alignment mark region 104 has an alignment mark 10S with a width of about 8 micrometers (Micron). Then, a Qin curtain material layer 1 丨 0 is formed on the substrate 100. The material is, for example, silicon nitride, and the method of forming it includes chemical vapor deposition (Chemical Vapor Deposition, CVD), etc. Du Yin disaster of cooperation between capital and industry. Secondly, please refer to Figure 1B. The mask material layer 1 丨 0 in Figure 丨 A is patterned by lithography, etching and other processes to remove part of the mask material layer. * Form a mask layer covering the active area 丨 06 ″ ″ 0a, and expose a part of the substrate 100 located at the alignment mark area 104. Then use the mask 餍 Ua as an etching mask to define the base of the component area 102. 00 is formed on the periphery of the active area 〇6 to form a trench 112 for isolating the component to be formed later, such as a shallow trench isolation structure. The trenches formed by the anisotropic saturation method in China and Israel are among the trenches. 6 The paper standard is the national standard (CMS) Λ4. (2 丨 〇Χ 嫠) 4 6 6 6 7 b A7 4 〇 (¾ jt 'cJ 0 c / 0 0 6 V. Description of the invention (f) The depth of the canal 112 is Η', the alignment mark 丨 卯 2 located at the alignment mark area 1Q4 is approximately equal to the ditch depth Η, and the step height Η It is also approximately equal to the trench > trench depth Η. Continue to refer to FIG. 1B, and sequentially form a liner oxide layer (not shown in the figure) on the substrate 100 with a patterned mask layer u 0t on its surface and an initial stage. .. The dielectric layer U.4 'will fill the trench 112 and the alignment mark 108 with an initial dielectric layer 114 made of an insulating material. Among them, a method for forming an oxide liner is, for example, the Chu thermal oxidation method, and the initial stage is made. The method of the dielectric layer 114 includes a chemical vapor deposition method, and the like. For example, if it is a suspended chemical vapor deposition (APCVD) method or a low pressure Chemical vapor deposition (LPCVD) method, etc., and the material of the initial interposer includes silicon oxide, borophosphosilicate glass, etc., and its thickness is about 8000 angstroms (Angstrom) Please refer to FIG. 1C for the print. With the mask 餍 li〇a as the termination layer, remove part of the initial dielectric layer U4, and form an isolation dielectric layer U4b in the trench 112 of the element region 102.丨 〇4 Part of the substrate 100 is formed with a bottom dielectric layer 1Uae, in which a portion of the initial dielectric U4 is formed by an insulating material, including an etch back (e.g., isotropic etching) Etc., or chemical mechanical honing (Chemica) Mechanical PoUshing (CMP), and the thickness of the bottom dielectric layer U4a formed is about 4000 Angstroms. Then as shown in Figure 1D, Figure 1C is used as the termination layer. The curtain ... layer 110a is removed, exposing a part of the substrate located in the active area 106. For example, the hot phosphoric acid solution is wet-dipped (Wet D 丨 p), and the material removed is The curtain layer 110a of silicon nitride. A conductive layer 116 is formed on the substrate 100, and the material package is The method of polysilicon, metal or other conductive material, is formed of, Γ ___ • a I - * too identified through recorded material (CNS) (2) ox297 well;. ¢) 67
67 .Joc/OOiS Λ7 B767 .Joc / OOiS Λ7 B7
五、發明説明（乙） I 例如是化學氣相沈積法等。 再請參照第丨E圖，定義第]D圖中之導電層116，.移: 除部份導電材料使其圖案化，定義步驟中包括微影、飯刻丨 等’以形成半導體結構中所需之元件116a，例如是作爲阐| .極結構之多晶矽層’或者是作爲內連線之金屬層等，並移： 除位於對準標示區104之導電材料，使對準標示區丨04內： 之底部介電層114a曝露出來。若所形成之元件116a爲蘭| 極’則於作爲基底100之晶圓上’形成配合閘極之源極與丨 汲極，以完成半導體元件之製作。 * 如第1F圖所示’接著在基底1〇〇上形成甶絕緣材料| 構成且平坦化之介電層118，其中介電層1丨8例如是內屬| 介電材料層（Inter-Layer Didectric，ILD)、內金饜介電層j (Inter-Metai Didectric, LMD)等’材質包括氧化矽等，形成j 之方法則包括化學氣相沈積法等。而製作平坦化之介電層i 118 ’可以先形成介電材料層，再以化學機械硏磨法將其j 平坦化；或者是以旋塗式玻璃法(Spin-On Glass, SOG)直接：丨 形成平坦化之介電層118。 經濟部智"財產局β工消费合作钍印裝 請参照第1G圖，於基底丨00表面所被覆之平坦化介 電層118上’形成一層導電材料層12〇，其形成方法包括 物理氣相沈積法 '化學氣相沈積法等，材質則包括鋁和銅 等u然後如第1Η圖所示I定義第1G圖中之導爾材料層120， 經微影、蝕刻等步驟將其圖案化，移除部份拿電材料，以 形成導線120a，並使位於對準標示區1〇4的卒坦化介電層 118曝露出來β其中位於元件區1〇2之導線120與對準標V. Description of the Invention (B) I For example, chemical vapor deposition. Please refer to Figure 丨 E to define the conductive layer 116 in Figure DD. Remove: Remove some conductive materials to pattern them. The definition step includes lithography, rice carving, etc. to form semiconductor structures. The required element 116a is, for example, a polycrystalline silicon layer as a polar structure or a metal layer as an interconnect, and is moved: except for the conductive material located in the alignment mark area 104, so that the alignment mark area 04 The bottom dielectric layer 114a is exposed. If the formed element 116a is a blue electrode, a source electrode and a drain electrode matching the gate electrode are formed on the wafer 100 as the substrate 100 to complete the fabrication of the semiconductor device. * As shown in FIG. 1F ', a 甶 insulating material is then formed on the substrate 100. The dielectric layer 118 is formed and planarized, and the dielectric layer 1 丨 8 is, for example, an intrinsic | dielectric material layer (Inter-Layer Didectric (ILD), inter-metal dielectric layer j (Inter-Metai Didectric, LMD) and other materials include silicon oxide, and the method of forming j includes chemical vapor deposition. To make the planarized dielectric layer i 118 ', a dielectric material layer can be formed first, and then j can be flattened by chemical mechanical honing; or by a spin-on glass (SOG) method:丨 Form a planarized dielectric layer 118. The Ministry of Economic Affairs " Property Bureau, β Industrial and Consumer Cooperation, Printing and Printing Please refer to FIG. 1G. A conductive material layer 12 is formed on the planarized dielectric layer 118 covered on the surface of the substrate 00. The formation method includes physical gas Phase deposition method 'chemical vapor deposition method, etc. The materials include aluminum and copper, etc. Then, as shown in Fig. 1, I define the conductive material layer 120 in Fig. 1G, and pattern it by lithography and etching. A part of the electrifying material is removed to form the conductive line 120a, and the dielectric layer 118 located at the alignment mark area 104 is exposed. Among them, the conductive line 120 and the alignment mark located at the device area 102 are exposed.
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五、發明説明（q) 經濟智慧財產局員工消費合作社印製 小區丨〇4，兩者之間的距離爲d，，而元件區102中的元件 116a與對準標示區丨04之間的距離爲d。如圖所示，導線 與對準標示區之距離D，大於元件與對準標示區之距離d， 因此導線120a與元件U6a之間具有安全間距(D，一 D)。 由上述本發明之較佳實施例可知，本發明爲進行對準 之便利性，將位於對準標示區之各種材料膜層進行選擇性 移除，使對準標示區上僅留有透明之介電材料，以利後續 形成之材料層與之前形成之材料層進行對準，防止因不同 材料之折射率、反射率差異導致主動區對準失誤。 而在形成元件區之隔離層時，同時移除位於對準標示 區內之部份介電材料形成底部介電層，可以防止後續沈積 之材料於底部介電層的凹陷側壁形成殘留物，避免在後續 步驟中對基底造成微粒污染。 此外’元件區內之導線與元件之間係由介電層所區 隔’元件爲介電層所包覆，導線則是位於介電層上。其中 導線與對準標示區之距離大於元件與對準標示區之距離， 使導線與元件之間具有安全間距，防止導線中之氮化鈦與 元件中之多晶矽直接接觸，抑制剝離現象發生影響元件品 質。 因此應用本發明，可以防止對準失誤、對準標示區內 殘留物和元件區之材料層剝離現象等產生，並可提高半導 體元件之品質、良率及可靠度。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 9 本紙張尺度適用中國國家棣準（CNS ) A4規格（210X297公釐） --tut nt n I I ^^^1 n 士 In ^^^1 一OJ (請先閲讀背面之注意事項再楨寫本頁) A7 4 6 6 4 4 () 61 \\ f d o c / Ο Ο 6 B7 五、發明説明（8 ) 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) —装- .11 經濟部智慧財產局員工消費合作社印製 ο 本纸張尺度適用中國國家標車（CNS ) A4規格（2丨Ο X 297公釐）V. Description of the invention (q) The printed area of the employee's cooperative of the Economic and Intellectual Property Bureau. The distance between the two is d, and the distance between the component 116a in the component area 102 and the alignment mark area 04. Is d. As shown in the figure, the distance D between the conductive line and the alignment mark area is greater than the distance d between the component and the alignment mark area, so there is a safe distance (D, -D) between the conductive line 120a and the component U6a. It can be known from the above-mentioned preferred embodiments of the present invention that, for the convenience of alignment, the present invention selectively removes various material film layers located in the alignment mark area, so that only the transparent medium remains on the alignment mark area. Electrical materials to facilitate subsequent alignment of material layers formed previously with the previously formed material layers, preventing misalignment of the active area due to differences in refractive index and reflectivity of different materials. When forming the isolation layer in the device region, at the same time, remove a portion of the dielectric material located in the alignment mark region to form a bottom dielectric layer, which can prevent subsequent deposited materials from forming residues on the recessed sidewalls of the bottom dielectric layer. Particle contamination of the substrate in subsequent steps. In addition, the wires in the 'element region and the elements are separated by a dielectric layer' and the elements are covered by the dielectric layer, and the wires are located on the dielectric layer. The distance between the conductive line and the alignment mark area is greater than the distance between the component and the alignment mark area, so that there is a safe distance between the conductive line and the component, preventing the titanium nitride in the conductive line from directly contacting the polycrystalline silicon in the component, and preventing the peeling phenomenon from affecting the component. quality. Therefore, the application of the present invention can prevent misalignment, peeling of residues in the alignment mark area, and peeling of the material layer in the device area, etc., and can improve the quality, yield and reliability of the semiconductor device. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art will not deviate from the spirit of the present invention. 9 This paper size applies to China National Standard (CNS) A4 specification (210X297 Mm) --tut nt n II ^^^ 1 n 士 In ^^^ 1 1 OJ (Please read the notes on the back before writing this page) A7 4 6 6 4 4 () 61 \\ fdoc / Ο 〇 6 B7 5. In the description of the invention (8) and the scope, various modifications and retouching can be made. Therefore, the scope of protection of the present invention shall be defined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) — Pack-.11 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ο This paper size applies to China National Standard Car (CNS) A4 Specification (2 丨 〇 X 297) %)