TW465266B - Wiring board for bump bonding, semiconductor device assembled from the wiring board and manufacturing method of wiring board for bump bonding - Google Patents

Wiring board for bump bonding, semiconductor device assembled from the wiring board and manufacturing method of wiring board for bump bonding Download PDF

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Publication number
TW465266B
TW465266B TW88111252A TW88111252A TW465266B TW 465266 B TW465266 B TW 465266B TW 88111252 A TW88111252 A TW 88111252A TW 88111252 A TW88111252 A TW 88111252A TW 465266 B TW465266 B TW 465266B
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Taiwan
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layer
block
wiring board
exposed
wiring
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TW88111252A
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Chinese (zh)
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Eizaburo Kanda
Takumi Shimoji
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Sumitomo Metal Mining Co
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Abstract

A wiring board for bump bonding which allows to prevent the occurrence of broken connections between bumps and wiring, and has small deviations in bump heights, and is superior in productivity; a semiconductor device assembled from the wiring board; and a manufacturing method of the wiring board for bump bonding are to be provided. In manufacturing a wiring board for bump bonding using an insulating layer having a conductive layer provided on its one surface, first, on the one surface of the conductive layer, a first resist layer is provided, exposed and developed, and the first resist layer in an area other than bump formation sections is eliminated, the conductive layer is half-etched to form bumps, then after eliminating the first resist layer as necessary, a second resist layer is provided, exposed and developed, and by etching the exposed conductive layer, a wiring pattern is formed. Thereafter, after the resist on the wiring pattern is eliminated as necessary, a protective resist layer is provided on the entire surface of the wiring pattern side, exposed and developed, and the surfaces of the bumps are exposed, then the protective resist layer is cured. Via holes are then formed by etching from the surface of the insulating layer side in desired sections, and the exposed bottom surfaces of the via holes and the surfaces of the bumps are metal-plated.

Description

4 6 526 S 五、發明說明(1) 發明背景 發明領域 本發明係闕於用於各種電子設備之半導體封裝所 塊形接合用佈線板,一種自佈線板組合而成之半導體的 置’以及一種塊形接合用佈線板的製造方法。 s 相關技術插 為符合近年來對電子設備微型化及減輕重量的要求,“ 導體封裝的構造正從線接合的型式(使用金線連接丰半 封裝與佈線板),朝向塊形接合的型式變動,如 體 利於微型化。在此種塊形接合型式的半導體封襞中,有 體晶片與安裝晶片之佈線材料(wiring material ’半導 :連接’ &經由半導體晶片上的電極接墊與成形於曰安的電曰 片之佈線材料上的塊形得到。 裝曰日 傳統上,這類具有塊形的佈線材料,是在由一 例如銅箱等導電層之聚醯亞胺膜所構成之材料的導有 塗:一層光阻,接著以所欲圖案之光罩遮罩: 圖宏。妓丁水 接 刻導電層以得到所要的佈魏 膜:昭射::以激發 '二氧化碳之類的雷射從聚醢亞胺 Μ側射,以形成所欲直徑的孔道。 u佈線圖案侧塗敷一層絕緣樹 案’接著在孔道底部截面所暴露出的導電層表 鋼,以椹成她形^ 〒私’衣®上生長鍍 道以做為外部π點接Γ來,以雷射照射絕緣樹脂膜形成孔 k Μ做為外而點。最後,為便於與半 塾接合,在做為外邻诚既夕$Λ D接 4知點之孔道底部截面所暴露出的鋼表4 6 526 S V. Description of the invention (1) Background of the invention The present invention relates to a wiring board for block bonding used in semiconductor packages for various electronic devices, a semiconductor device composed of wiring boards, and a A method for manufacturing a wiring board for block bonding. s Relevant technology is inserted to meet the requirements for miniaturization and weight reduction of electronic devices in recent years. It is good for miniaturization. In this type of block junction type semiconductor package, the wiring material of the body wafer and the mounting wafer (wiring material 'semiconductor: connection' & via electrode pads and forming on the semiconductor wafer) The block shape of the wiring material of Yu Yuean's electric chip is obtained. Traditionally, this type of wiring material with a block shape is composed of a polyimide film with a conductive layer such as a copper box. The guide of the material is coated: a layer of photoresist, and then masked with a photomask of the desired pattern: Figure macro. The conductive layer is engraved to obtain the desired cloth film: Zhao She :: to excite the carbon dioxide and the like The laser is fired from the side of the polyimide M to form a channel of a desired diameter. U The side of the wiring pattern is coated with an insulating tree case, and then the conductive layer surface steel exposed on the bottom section of the channel is formed into her shape ^ Sham The growth plated on the clothing is used as the external π point to connect Γ, and the insulating resin film is irradiated with a laser to form a hole Μ as the external point. Finally, in order to facilitate the connection with the semi-concrete, it is necessary to be a neighbor. $ Λ D The steel watch exposed by the bottom section of the tunnel with 4 points of knowledge

EH 88111252.ptdEH 88111252.ptd

第6頁 465266 五、發明說明(2)Page 6 465266 V. Description of the invention (2)

面’以及塊形的表面上鍍金D 為接合經由上述製程所得之佈線材料與半導體晶片,使 用熱-壓法或熱-壓與超音波結合的方法,此外,在成形為 外部端點的孔道中填充焊塊,供安裝於印刷伟線板上。 不過,按上述的傳統製造方法,在鋼箔(它是銅佈線的 原材料)與以電鍍方式構成之塊形的介面間,會發生晶粒 邊界的不連續斷面,於是產生—個問題,在接合半導體晶 片時所產生的應力,會使塊形與佈線間的連接發生破裂的 情形。 此外’由於塊形的形成’是在孔道的底部斷面生長電鍍 金屬,溥片的厚度至少要等於或大於做為絕緣樹脂層的聚 醯亞胺臈’因此,電鍍金屬的製程需要長時間,這導致生 產力無法提升。 此外,由於塊形是以電鍍金屬的方式生長,因此,塊形 的南度偏差無法縮小。 _發明概述 本發明考慮以上的情況,其目標是提供一種供塊形接合 用的佈線板,它可防止塊形與佈線間連接的破裂,且塊形 兩度的偏差小’並具有極佳的生產力,以及一種從佈線板 組合而成的半導體裝置,以及供塊形接合用佈線板的製造 方法。 ,為解決上述問題,與本發明第一種態樣有關的是一種塊 形接合用佈線板,包括一絕緣層,置於絕緣層一表面上的 一佈線層,在所欲的位置上有與佈線一體成形的塊形,以The surface and the block-shaped surface are plated with gold D to join the wiring material and the semiconductor wafer obtained through the above process, and a thermo-compression method or a method of combining thermo-compression and ultrasonic waves is used. Filler pads for mounting on printed wiring boards. However, according to the above-mentioned traditional manufacturing method, discontinuous cross sections of grain boundaries occur between the steel foil (which is the raw material of copper wiring) and the block-shaped interface formed by electroplating, so a problem arises, in The stress generated when the semiconductor wafer is bonded may cause the connection between the block shape and the wiring to be broken. In addition, 'because of the formation of a block shape', electroplated metal is grown on the bottom section of the channel, and the thickness of the cymbal must be at least equal to or greater than that of polyimide, which is an insulating resin layer. Therefore, the process of electroplated metal requires a long time. This makes it impossible to increase productivity. In addition, since the block shape is grown by electroplated metal, the south deviation of the block shape cannot be reduced. _Summary of the Invention The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a wiring board for block bonding, which can prevent the connection between the block and the wiring from being broken, and the deviation of the block two degrees is small and has excellent Productivity, and a semiconductor device combined from a wiring board, and a method for manufacturing a wiring board for block bonding. In order to solve the above-mentioned problem, related to the first aspect of the present invention is a wiring board for block bonding, which includes an insulating layer, a wiring layer placed on a surface of the insulating layer, and has a position at a desired position. Integrated block shape for wiring

8S111252,ptd 第7頁 4 6526 6 五、發明說明(3) 及在絕緣層的一表面上有保護阻蝕層,並露出塊形表面, 且其中的孔道配置於絕緣層的另一表面。 此外’與本發明第二種態樣有關的是一種半導體裝置, 其特徵是它是使用具有上述結構之塊形接合用佈線板組合 而成。 此外’與本發明第三種態樣有關的是塊形接合用佈線板 的製造方法,包括: (a) 在配置於一絕緣層之一表面上之導電層表面上施加 第一阻蝕層的製程; (b) 執行曝光及顯影的製程,以去除要成形塊形之區域 以外區域的第一阻蝕層; (c) 對露出的導電層執行半餘(half-etching)以構成塊 形的製程; (d) 在導電層上施加第二阻蝕層的製程; (e) 執行曝光、顯影並蝕刻所露出之導電層的製程,以 構成一佈線圖案; (f) 在佈線圖案侧的整個表面施加保護阻银層的製程; (g) 執行曝光及顯影的製程,以露出塊形的表面,並硬 化保護阻蝕層; (h) 在絕緣層的另一表面施加第三阻|虫層的製程; (i) 在第三阻韻層上執行曝光及顯影的製程,以形成一 Ί虫刻圖案;以及 (j)蝕刻露出的絕緣層以形成孔道的製程;且其中; 在钮刻露出之的絕緣層形成孔道之後,進一步在孔道底部 〇8S111252, ptd Page 7 4 6526 6 V. Description of the invention (3) There is a protective corrosion-resistant layer on one surface of the insulating layer, and a block-shaped surface is exposed, and the channels therein are arranged on the other surface of the insulating layer. In addition, a second aspect of the present invention relates to a semiconductor device, which is characterized in that it is a combination of a block bonding wiring board having the above-mentioned structure. In addition, related to the third aspect of the present invention is a method for manufacturing a block bonding wiring board, including: (a) applying a first resist layer on a surface of a conductive layer disposed on one surface of an insulating layer; Manufacturing process; (b) performing an exposure and development process to remove the first resist layer in areas other than the area to be formed into a block shape; (c) performing half-etching on the exposed conductive layer to form a block shape (D) a process of applying a second resist layer on the conductive layer; (e) performing a process of exposing, developing, and etching the exposed conductive layer to form a wiring pattern; (f) the entirety of the wiring pattern side A process of applying a protective silver barrier layer on the surface; (g) performing a process of exposing and developing to expose a block-shaped surface and hardening the protective resist layer; (h) applying a third barrier layer on the other surface of the insulating layer (I) a process of exposing and developing on the third rhombohedral layer to form a worm-etched pattern; and (j) a process of etching the exposed insulating layer to form a channel; and wherein; exposing on the button After the insulating layer is formed, Department 〇

88111252.ptd 第8頁 五、發明說明(4) ----- 細面所露出的導電層表面及塊形表面電鍍金屬,導電層是 鋼,以及絕緣層是聚醯亞胺膜。 圖圖1疋本發明之塊形接合用佈線板之一種具體例的截面 1 絕緣層 2 塊形 一1 3 4 5 薄層 佈線層 保護阻蚀層 孔道 薄層 在 ’將配合附圖解釋本發明。 圖1顯示土 @ 圖,其妹播^發明之塊形接合用佈線板第一種具體例的概 由鋼ϋ由是在絕緣層1 (如聚醯亞胺膜)的一表面上配置 形的塊形2,的+佈線層3,在所欲的位置有與佈線層3一體成 加有保i卩且#絕緣層1上配置有佈線層3之側的表面上施 另並露出塊形2的表面,並在絕緣扪的 π no呢置孔道5,在塊形2的 好f-層金或銀的薄層2-1、5-1。 d的底表面最 ^此’使用本發明的塊形接合 非常容易,# Η衡难祕士土 4用佈線板組裝半導體裝置 吏用與傳統方法相同的方法接合半導體晶ίί 465266 五、發明說明(5) 塊形’以焊球填充孔道,經由此再接合到印刷佈線板。 接下來’要解釋製造本發明之塊形接合用佈線板的製 程。 首先’使用由一絕緣層(諸如聚醯亞胺膜)及—導電層製 成的銅-聚醯亞胺基底’最好是使用銅箔層積於它的一表 面’在基底之銅箔侧的表面層積一層乾膜阻飯層。 接下來’以光罩遮蔽乾膜阻蝕層,以紫外線照射曝光及 顯影’接著’將乾膜阻蝕層中要成形塊形區域以外的區 除去。 °° 一 半蝕以此種方法暴露出的銅箔導電層以形成塊形。 之後,在導電層侧再層積一層上述的阻蝕膜,但事先必 須先將塊形上的乾膜阻蝕層除去。 ' 以具有所欲佈線圖案的光罩遮蔽層積而成的阻蝕層,並 以紫外線照射曝光,接著蝕刻顯影後所暴露出的導 以形成伟線圖案。 此外,例如以真空層積法在佈線圖案側的整個表面声 —層乾膜光阻,以構成保護阻蝕層,但事先要將佈線^案 上先前的阻蚀層除去。 '、 接下來,對保護阻蝕層曝光及顯影,以除去塊形上 膜光阻,之後’硬化保護阻蝕層。 就以做為保護阻餘層的阻钱層而言,以液態塗敷的方 法,或是事先層,樹脂膜以形成乾膜層的方法等都可以使 用,不過’從容易成形-厚度均句之膜的角度來看,最好 是使用乾膜光阻。 取88111252.ptd Page 8 V. Description of the Invention (4) ----- The surface of the conductive layer and the block-shaped surface exposed by the fine surface are electroplated metal, the conductive layer is steel, and the insulating layer is a polyimide film. Fig. 1 的 A cross-section of a specific example of a block-type bonding wiring board of the present invention 1 Insulating layer 2 Block-shaped 1 3 4 5 Thin-layer wiring layer protection corrosion-resistance channel thin layer . Fig. 1 shows the figure of the soil. The first concrete example of the block-joint wiring board for the invention of the invention is a steel wire, which is arranged on a surface of an insulating layer 1 (such as a polyimide film). Block shape 2, + wiring layer 3, at the desired position, is integrated with wiring layer 3 to form a protective layer, and # insulation layer 1 is arranged on the surface of the wiring layer 3 side, and block shape 2 is exposed. Surface, and the holes 5 are placed in the π no of the insulating 扪, and the thin f-layers of gold or silver 2-1, 5-1 in the block shape 2. The bottom surface of the substrate is most easy to use. The present invention is very easy to use, and the semiconductor device is assembled with a wiring board using a wiring board. The semiconductor wafer is joined in the same way as the traditional method. 465266 5. Description of the invention ( 5) The block shape fills the vias with solder balls and is then bonded to the printed wiring board. Next, the process of manufacturing the wiring board for block bonding according to the present invention will be explained. First 'use a copper-polyimide substrate made of an insulating layer (such as a polyimide film) and a conductive layer', preferably using a copper foil laminated on one surface 'on the copper foil side of the substrate A dry film layer is laminated on the surface. Next, "mask the dry film resist layer with a photomask, and expose and develop it with ultraviolet light irradiation". Next, the area of the dry film resist layer other than the area to be formed into a block is removed. °° A half-etched copper foil conductive layer exposed in this way to form a block shape. After that, another layer of the above-mentioned resist film is laminated on the conductive layer side, but the dry film resist layer on the block must be removed beforehand. '' The laminated resist layer is shielded with a photomask having a desired wiring pattern, exposed to ultraviolet radiation, and then the exposed leads after development are etched to form a pattern of great lines. In addition, for example, the entire surface acoustic-layer dry film photoresist is formed on the wiring pattern side by a vacuum lamination method to constitute a protective resist layer, but the previous resist layer on the wiring pattern is removed in advance. 'Next, the protective resist is exposed and developed to remove the block-type photoresist, and then the protective resist is hardened. As for the money barrier layer that protects the residual barrier layer, a liquid coating method, or a prior layer, a resin film to form a dry film layer, etc. can be used, but 'from easy forming-thickness uniform sentence From the perspective of film, it is best to use dry film photoresist. take

4 6 526 6 五、發明說明(6) 之後’在銅-聚驢亞胺基底之聚醯亞胺絕緣層的表面層 積一層乾膜阻蝕層。 在此時’最好也在佈線圖案側的整個表面塗布相同的乾 膜阻蝕層,以便在後續的蝕刻製程中保護塊形。 接下來,遮罩上述的乾膜阻蝕層,曝光及顯影以在絕緣 層上形成蝕刻圖案。 钮刻暴露出的聚醯亞胺絕緣層以形成孔道。 經過這些製程’即可製造出本發明的塊形接合用佈線 板。 此外’在本發明中,最好能在以上述方法成形之孔道的: 底表面内的導電層表面以及塊形表面上電鍍一層金屬,關」 於此點’可以按需要選擇銀鍍層或金鍍層等。 如前所述,由於塊形與佈線是以相同的導電層一體成 形,塊形與佈線間不會發生晶粒邊界的不連續斷面,此 外’由於形成塊形是執行半蝕,因此不需要傳統方法中電 鐘金屬製程所需要的時間,因此可以得到極佳的生產力。 具體例描述 以下將解釋本發明的具體例及比較例。 具體例: 首先,在由厚50微米、寬35毫米、長20公分之聚醯亞胺 膜及配置於其一表面上厚25微米之銅箔所構成的銅-聚醯 亞胺基底的銅箔側,層積一層厚度丨5微米的鹼性顯影型負 _ 乾膜光阻’以光罩遮蔽阻银層,再以強度2 〇 〇毫焦耳的紫、 外線照射曝光’並顯影’因此,在銅-聚醯亞胺基底之鋼4 6 526 6 V. Description of the invention (6) Afterwards, a dry film corrosion-resistant layer is laminated on the surface of the polyimide insulation layer of the copper-polydonimine substrate. At this time ', it is preferable to apply the same dry film resist on the entire surface of the wiring pattern side in order to protect the block shape in the subsequent etching process. Next, the dry film resist layer is masked, exposed and developed to form an etching pattern on the insulating layer. The exposed polyimide insulation layer is engraved to form holes. Through these processes', the block-type bonding wiring board of the present invention can be manufactured. In addition, in the present invention, it is desirable to be able to plate a layer of metal on the surface of the conductive layer and the block-shaped surface in the channel formed by the above method. At this point, a silver plating or a gold plating can be selected as required. Wait. As mentioned above, since the block shape and the wiring are integrally formed with the same conductive layer, a discontinuous cross-section of the grain boundary does not occur between the block shape and the wiring. In addition, because the formation of the block shape is performed by half-etching, it is not necessary The time required for the metal process of the electric clock in the traditional method, therefore, excellent productivity can be obtained. Description of Specific Examples Specific examples and comparative examples of the present invention will be explained below. Specific examples: First, a copper-polyimide-based copper foil composed of a polyimide film having a thickness of 50 micrometers, a width of 35 millimeters, and a length of 20 cm and a copper foil disposed on one surface of the film having a thickness of 25 micrometers On the side, a layer of 5 μm alkaline developing type negative dry film photoresist is laminated with a photomask to shield the silver resist layer, and then exposed to violet and external light with an intensity of 2000 millijoules. Copper-polyimide-based steel

4 6 526 6 五、發明說明(7) 猪上,構成在長度方向之間距為丨9毫米的圖案,每一條上 成形有200個塊形’在寬度方向的間距為12〇微米。 接下來,露出的鋼箔區域與溫度4〇。〇的商用氯化銅蝕液 接觸,鋼箔區域經過半蝕以形成塊形,之後,以氫氧化鈉 溶液姓去塊形上的阻餘層。 此外,在銅箔側再層積一層同類型的乾膜阻蝕層,以具 有所欲佈線圖案的光罩遮蔽,經過相同的曝光及顯影製 程,得到佈線圖案。 接下來,利用上述相同的方法蝕刻銅箔以形成佈線圖 案,並除去阻蝕層。 之後’以真空層積法在佈線圖案側的整個表面層積一層 厚度3 5微米的鹼性顯影型乾膜光阻。接著對此層積的乾臈 阻蚀層曝光及顯影’並去除塊形表面上的乾媒阻蝕層,接 著以1 7 0 °C加熱基底,對剩下的乾膜阻蝕層進行硬化處 理。 之後,在佈線圖案側及聚醯亞胺膜側,各層積一層厚度 25微米的耐鹼性乾膜阻蝕層,在基底之聚醯亞胺側的阻蝕 層表面上以指定的光罩遮蔽,曝光及顯影以形成直徑22〇 微米的開口 ’並蝕刻暴露出的聚醯亞胺膜以形成孔道。之 後,去除兩側剩下的阻蝕層。 最後,使用商用的氰根型鍍金溶液,在孔道的底表面及 塊形的表面上電鍍厚度大約2微米的金。 在以上述製程得到塊形接合用佈線板的塊形後,以4 〇 〇 倍的光學顯微鏡觀察’發現所得到的塊形戴面是梯形,4 6 526 6 V. Description of the invention (7) On the pig, a pattern with a distance of 9 mm in the longitudinal direction is formed, each of which is formed with 200 blocks' with a pitch of 120 microns in the width direction. Next, the exposed area of the steel foil is at 40 ° C. 〇Commercial copper chloride etching solution was contacted, and the steel foil area was half-etched to form a block shape. After that, the sodium hydroxide solution was used to remove the residual layer on the block shape. In addition, a dry film corrosion layer of the same type is further laminated on the copper foil side, masked with a mask having a desired wiring pattern, and the wiring pattern is obtained through the same exposure and development process. Next, the copper foil was etched by the same method as described above to form a wiring pattern, and the resist was removed. After that, an alkaline developing type dry film photoresist having a thickness of 35 µm was laminated on the entire surface of the wiring pattern side by a vacuum lamination method. Then expose and develop the laminated dry corrosion resist layer and remove the dry dielectric resist layer on the block surface. Then heat the substrate at 170 ° C to harden the remaining dry film resist layer. . Then, a layer of an alkali-resistant dry film with a thickness of 25 micrometers was laminated on each of the wiring pattern side and the polyimide film side, and the surface of the polyimide side of the substrate was masked with a designated photomask. , Expose and develop to form an opening of 22 μm in diameter and etch the exposed polyimide film to form a channel. After that, the remaining resist layers on both sides are removed. Finally, a commercially available cyanide-type gold plating solution was used to plate gold with a thickness of about 2 microns on the bottom surface of the channel and the massive surface. After obtaining the block shape of the block-type bonding wiring board by the above-mentioned process, observation with an optical microscope at a magnification of 4,000 times' found that the obtained block-shaped wearing surface was trapezoidal,

88111252.ptd 第12頁88111252.ptd Page 12

^ S526S 五、發明說明(8) -------- 此外,當此塊形接合用佈線扳以3〇〇^:的溫度、1〇 / 形的負荷持續30秒與印刷佈線板㈣接合後,進行破壞性 檢驗研究塊形與佈線間連接的破裂情形,結果觀察不 何連接破裂。 比較例 在=厚30微求、寬35毫求、長2〇公分之聚醯亞胺膜及配 置於其一纟面上厚18微米之㈣所#成的銅一聚酿亞胺基 底的銅箔側,層積一層鹼性顯影型的負乾膜光阻,以光 遮蔽阻敍層’並以強度200毫焦耳的紫外線照射曝光,並 顯影,以形成佈線圖案。 .、 接下來,暴露出的銅ϋ區域以溫度451之氯化鋼所構成、 的#液#刻,之後除去阻飯層。 接下來’以氬氣雷射照射鋼_聚醯亞胺基底的聚醯亞胺 侧’以形成直徑50微来的孔道,並暴露出孔道底部截面的 銅箔8 在佈線圖案側施加丙烯類樹脂做為金屬電鍍的保護膜’ 並使其乾燥後,使用硫酸類的蝕液清洗孔道之底部截面的 铜箔表面,之後,使用硫酸銅電鍍液電鍍〇· 5小時以形成 塊形。之後,使用酮類溶液溶解除去丙烯類樹脂的保護 膜。 〇 此外,在佈線圖案侧的整個表面印刷鹼性顯影型的阻焊 層’並以特定的光罩遮蔽,曝光及顯影以形成截面2 00微 米的開口,接著將基底加熱到i 7{rc進行阻焊層的硬化。 最後,在佈線圖案側之阻烊層之開口的截面以及塊形表^ S526S V. Description of the invention (8) -------- In addition, when the block bonding wiring board is used at a temperature of 300 ° C and a load of 10 / shape for 30 seconds, the printed wiring board 布线After joining, a destructive test was performed to study the breakage of the connection between the block and the wiring, and as a result, no connection breakage was observed. Comparative Example: Polyimide film made of polyimide film with thickness of 30 micron, width of 35 millimeters, and length of 20 cm and copper disposed on one surface of 18 micrometers thick. On the foil side, a layer of a negative dry film photoresist of alkaline development type is laminated, the photoresist layer is shielded with light and exposed to ultraviolet light with an intensity of 200 millijoules, and developed to form a wiring pattern. . Next, the exposed area of copper ϋ is engraved with # 液 # composed of chlorinated steel at a temperature of 451, and then the rice blocking layer is removed. Next, irradiate the polyimide side of the steel_polyimide substrate with an argon laser to form a 50 micron diameter channel and expose the copper foil at the bottom cross section of the channel. 8 Apply an acrylic resin to the wiring pattern side. After being dried as a protective film for metal plating, the surface of the copper foil at the bottom section of the tunnel was washed with a sulfuric acid-based etchant, and then plated with a copper sulfate electroplating solution for 0.5 hours to form a block shape. After that, the protective film of the propylene-based resin was dissolved and removed using a ketone-based solution. 〇 In addition, the entire surface of the wiring pattern side was printed with an alkali-developed solder resist layer 'and masked with a specific mask, exposed and developed to form an opening with a cross section of 200 microns, and then the substrate was heated to i 7 {rc for Hardening of solder mask. Finally, the cross-section of the opening of the barrier layer on the side of the wiring pattern and the block form

__

465266 五、發明說明(9) ::使用商用的氰根型鍍金溶液電鍍厚度大約2微米的 rm法得到塊形接合用佈線板之塊形後’以300 ί:: Γg 形的負荷持續3 0小時與印刷佈線板熱 π之彳進行破壞性檢驗研究塊形與佈線間連接的破 裂情形,結果發現832個塊形中有9個塊形受損。 本發明的效果: 、465266 V. Description of the invention (9) :: After using the commercial cyanide-type gold plating solution to plate a thickness of about 2 micrometers by the rm method to obtain the block shape of the block bonding wiring board, a load of 300 Γ :: Γg lasts for 3 0 Destructive inspection was conducted with the heat of π of the printed wiring board to study the rupture of the connection between the block and the wiring. As a result, 9 of the 832 blocks were damaged. Effects of the invention:,

σ剛文的解釋,由於本發明是先半蝕銅箔以成形塊形接 二用佈線板的塊形後再蝕出佈線,因此可以很有效率地成 形塊形,且在塊形與佈線間不會發生晶粒邊界的不連續斷 面’此外’由於塊形是半蝕具有同等厚度的銅箔而成,因 此可以得到塊形高度偏差很小的佈線板。The explanation of σ Gangwen, because the present invention is to etch copper wiring after half-etching the copper foil to form the block shape of the wiring board, and then etch the wiring, so the block shape can be formed very efficiently, and between the block shape and the wiring No discontinuous cross-section of the grain boundary will occur. In addition, since the block shape is a half-etched copper foil with the same thickness, a wiring board with a small block height deviation can be obtained.

88111252.ptd 第14頁88111252.ptd Page 14

Claims (1)

46526 6 六、申請專利範圍 1'種供塊形接合用之佈線板,包拓一組鏠JS 於該絕緣層-表面上的佈線層,具有::=,1置 的塊形,以及配置於續絕緣声之嗲有:欲截:之-體成形 層按延種方式可以得到該塊形露出的表 盆巾蝕 置於該絕緣層的另一表面。 丨的表® “孔道配 二專利範圍第1項的塊形接合用之佈線板,复Φ 忒鬼形的表面及該孔道的底部表面鍍有金屬。 /、中 、fU半導體裝置’組合自中請專利範圍第1或2項所卜 述的塊形接合用佈線板。 所私 4. 一種塊形接合用佈線板之製造 . (:)在配置於一絕緣層之一表面上之\電包二^ 施加弟一阻蝕層的製程; 工 (b)執行曝光及顯影的製程,以除去該第一阻蝕 成形塊形區域以外的區域; 要 ί = ί S :導電層執行半蝕以構成塊形的製程; (d)在該導電層上施加第二阻蝕層的製程. 以(』):行/Λ、/影並餘刻所露出之該導電廣的製程, 以構成一佈線圖案; a) j佈=案側的整個表面施加保護 並硬化保護阻飯層; 卩得到表面露出的塊形, α)在該絕緣層的另一表面施加 (i )在該第三阻蝕層上勃仵温L ^ 增的表紅’ -蝕刻圖案;以及 丁曝先及顯影的製程,以形成 4 6526 6 六、申請專利範圍 (j)蝕刻暴露出的絕緣層以形成孔道的製程。 5. 如申請專利範圍第4項之塊形接合用佈線板之製造方 法,其中在蝕刻該暴露之絕緣層形成孔道後,在孔道之底 部表面所暴露之導電層表面及塊形表面電鍍金屬。 6. 如申請專利範圍第4或5項之塊形接合用佈線板之製造 方法,其中該導電層是銅,以及絕緣層是聚醯亞胺膜。46526 6 VI. Scope of patent application 1 'A type of wiring board for block bonding, including a set of 鏠 JS on the insulation layer-surface wiring layer, has: ==, 1 block type, and is arranged in Continuing insulation sounds include: To cut off:-The body-forming layer can be obtained by extending the block-shaped exposed table towel to the other surface of the insulating layer.丨 's Table ® "The channel is equipped with the wiring board for block bonding of item 1 of the second patent scope. The surface of the Φ 忒 and the bottom surface of the channel are plated with metal. Please use the wiring board for block bonding as specified in item 1 or 2 of the patent. 4. The manufacture of a wiring board for block bonding. (:) \ Electric package on one surface of an insulating layer (2) a process of applying a resist layer; (b) performing a process of exposing and developing to remove the area other than the block area of the first resist forming block; ί = ί S: the conductive layer is subjected to half-etching to form Block-shaped process; (d) A process of applying a second corrosion-resistant layer on the conductive layer. (”): Row / Λ, / shadow and the exposed conductive process in the rest of the time to form a wiring pattern A) j cloth = the entire surface of the case side is applied to protect and harden the rice block layer; 卩 get the block shape exposed on the surface, α) apply (i) to the third corrosion layer on the other surface of the insulating layer博 仵 温 L ^ Increased surface red '-etching pattern; and Ding Xianxian and development process to form 4 65 26 6 VI. Patent application scope (j) Process of etching the exposed insulating layer to form a channel. 5. For example, the manufacturing method of the block bonding wiring board according to item 4 of the patent application scope, wherein the exposed insulating layer is etched After the channel is formed, the conductive layer surface and the block-shaped surface exposed on the bottom surface of the channel are electroplated with metal. 6. For example, a method for manufacturing a block-joint wiring board according to item 4 or 5 of the patent application scope, wherein the conductive layer is copper And the insulating layer is a polyimide film. S81I]252‘ptd 第16頁S81I] 252‘ptd page 16
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Publication number Priority date Publication date Assignee Title
JP3760731B2 (en) 2000-07-11 2006-03-29 ソニーケミカル株式会社 Bumped wiring circuit board and manufacturing method thereof
JP2002111185A (en) 2000-10-03 2002-04-12 Sony Chem Corp Wiring circuit board with bumps and method of manufacturing the same
JP4335075B2 (en) * 2004-06-08 2009-09-30 株式会社伸光製作所 Multilayer printed wiring board and manufacturing method thereof

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