TW465186B - Logic gate having temperature compensation and method - Google Patents

Abstract

A logic gate (10) having temperature compensation. The logic gate (10) includes an input stage (11) and an emitter follower output stage (12) coupled to a temperature compensation circuit (13). The temperature compensation circuit (13) includes a pair of bipolar transistors (23, 24) that generate temperature dependent currents (I23, I24). The temperature dependent currents (I23, I24) alter the voltages appearing at the respective base terminals of the emitter follower output stage (12). The altered voltages compensate for temperature variations of the emitter follower output stage (12).

Description

465186 A7 B7 V. Description of the invention (BACKGROUND OF THE INVENTION The present invention is generally related to logic circuits, more specifically, to logic circuits and temperature compensation. Basic logic circuits are widely used in including, automatic, aerospace, electricity: Such as on industrial machines. In these many applications, "we all want the output level to be independent of temperature to avoid the noise margin becoming smaller. In a series circuit that uses an emitter follower to generate the output logic level, the The logic logic should be equipped with a temperature compensation circuit to avoid the degradation of the noise level of the output logic level. If / when there is compensation, the output logic level will be due to the negative temperature of the base junction of the bipolar transistor. The effect of the coefficient varies. The temperature of the emitter base voltage drops when the temperature rises; on the contrary, the emitter base voltage rises when the temperature drops. Connect the input differential pair to the collector terminal and connect a resistor in series with a back-to-back diode. Is a technology that provides temperature compensation. However, this technology reduces the high switching performance of the bipolar transistor manufactured by a high-efficiency bipolar process. In addition, in When the temperature is lower than about 25 degrees Celsius (° C), the compensation performance provided by this technology is not good. Therefore, having a temperature compensation logic circuit that can provide temperature compensation at a temperature lower than 2 51 Beneficial. It is beneficial to manufacture the circuit in an integrated circuit by a manufacturing process. '' Brief description of the diagram The circuit diagram of FIG. 疋 The first specific embodiment of the logic gate connected to the temperature compensation network of the present invention; The circuit diagram of 2 is the logical question of the connection between the present invention and the temperature compensation network-specific embodiments; 4 The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Jing Xianjian read the back of the note (Please fill in this page for matters) Packing ------- Order --- ο Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employee Cooperatives of the Ministry of Economic Affairs Intellectual Property Bureau printed 465186 A7 ----- D7__ V. Invention Explanation (2) The circuit diagram of FIG. 3 is a third specific embodiment of the logic gate connected to the temperature compensation network according to the present invention; FIG. 4 is a characteristic curve of the output logic level of the temperature gated logic gate according to the present invention. Detailed description 1 is a circuit diagram of the temperature-compensated logic gate 10 according to the first embodiment of the present invention. The logic gate 10 is composed of a differential input stage t1 and an output stage 12 connected to the temperature compensation stage 13. Considering this example, the differential input stage 11 includes a pair of bipolar transistors 14 and 17, and the emitter terminals of the two transistors 14 and 17 pass through the resistors 5 and 6 respectively, and are connected to the current The source 18 ° current source 18 is connected to the operating potential source marked Vee. The collector terminals of the two transistors 14 and 17 are connected through resistors 9 and 20 respectively to the Vcc marked Operating the potential source. The load resistors 19 and 20 form a load circuit for the differential input stage 11. The base terminals of transistors 4 and 17 are connected separately to receive the input signals VIN1 and VIN2. It must be noted that the emitter and collector terminals of the bipolar transistor can also be referred to as conductive electrodes, and the base terminal can also be referred to as the control electrode a. The output stage 1 2 is connected by a pair The emitter-level configuration is composed of bipolar transistors 21 and 22. So the bipolar transistor 21 is usually connected to the collector terminal of the bipolar transistor 14 and connected to the load resistor 19 to the node 28; while the base terminal of the bipolar transistor 22 is usually connected to the dual load The collector terminal of the transistor 17 is connected to the load resistor 20 at the node 2 9. The collector terminals of the bipolar transistors 21 and 22 are both connected to receive the operating voltage source Vcc. Typically, the emitter terminals of the bipolar transistor 2 1 and 2 2 are both -5- This paper size applies to the Chinese National Standard (CNS) A4 specification (210x297 mm) (Page) Install -------- Order ---- ο. 4 6518

D A7 B7 5. Description of the invention (3) Floating so that the user can connect his desired load to the logic gate 10. It must be noted that the 'logic gate 10 typically drives a 50 ohm load. Therefore, the logic gate 10 shown in the diagram is pushed by two 50 ohm resistors 33 and 34. Specifically, the resistor 3 3 is connected between the wheel-out node 31 and the bias voltage Vtt, and the resistor 34 is connected between the output node 32 and the bias voltage τττ. The output ^ number V0UT # VOUT2 is generated at nodes 3 1 and 3 2 0 respectively. The temperature compensation circuit 13 is composed of a pair of bipolar transistors 23 and 24 and a pair of resistors 25 and 26. More specifically, the base terminals of the bipolar transistors 23 and 24 are connected together and are commonly connected to the bias potential VBIAS. It must be understood that VB1AS is an adjustable voltage, which can be adjusted between about 0.8 volts + Vee to about 1.2 volts + VBE over a temperature range from -40 ° C to 125 ° C. The emitter terminals of the bipolar transistors 23 and 24 are respectively connected to the operating voltage source Vee through the resistors 25 and 26 respectively. The collector terminal of the bipolar transistor 23 is usually connected to the base terminal of the bipolar transistor 21, the collector terminal of the bipolar transistor 14, and the terminal of the resistor 19 at the node 28. The collector terminal of the bipolar transistor 24 is usually connected to the base terminal of the bipolar transistor 22, the collector terminal of the bipolar transistor 17, and the terminal of the resistor 20 at the node 29. Although the emitter terminals of the two-carrier transistors 23 and 24 are connected to the operating voltage source through the resistors 25 and 26, respectively, as described above, it should be understood that the present invention is not connected in this way. Limited. For example, the emitter terminals of the bipolar transistors 23 and 24 can be connected directly to the operating voltage source. -6-This paper size applies to Chinese national standards (CNS> A4 size (2) 0x297 mm) < Please read the notes on the back before filling this page) -XO- Μ -------- Order ---- ο. Printed by the Intellectual Property Bureau staff of the Ministry of Economic Affairs, printed by the cooperatives of the Ministry of Economic Affairs, printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics 4 65 1 8 6 A7 ------ B7 V. Description of the invention (4) In operation The input signals Vin! And V [N2 will be sent to the base terminals β of transistors 14 and 17 respectively. In this example, Vcc is about 0 volts, νΕΕ is about -5.2 volts, and VBIAS is about -4.2. VTT is approximately -2 volts, the logic high signal of the ECL is approximately -0.9 volts, and the logic low signal of the ECL is approximately -1.7 volts. It should be understood that the logic levels described herein are for example only, and the present invention is not limited thereto. It should also be understood that the differential input stage is not limited to receiving a differential input signal, that is, the differential input stage may be connected to receive a single-ended input signal in addition to being connected to receive a differential input signal. If a single-ended input signal is received, the base terminal of one of the transistors 14 and 17 must be connected to receive the reference voltage commonly referred to as VBB 'and the base terminal of the other transistor is connected. To receive a time-varying voltage signal. When the input signal VINI is an ECL logic high input signal, and the input signal ViN2 is an ECL logic low input signal, the transistor 14 is turned on and the transistor 17 is not connected to the β current. The watt 114 flows into the collector terminal of the transistor 14 and flows into the The current Iη of the collector terminal of the crystal 17 is approximately zero amperes. The voltage at node 28, Vu, is approximately equal to vcc minus the voltage drop across resistor 19, and the voltage at node 29, Vm ', is approximately equal to Vcc. The voltage V0 at the output terminal 31 is:

Vouti = V28-VBE2i = Vcc-VR19-VBE2] where Vbe2i is the emitter-to-base voltage drop of transistor 2 1. The voltage votJT2 on output terminal 32 is: V〇UT2 = ν29-νΒΕ22 = vcc-vBE22 where Vbe22 is the emitter-to-base voltage drop of transistor 22. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public love) Crack I ---- Order ---- (Please read the precautions on the back before filling this page) 4 65186 A7 B7 Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Cooperatives. 5. Description of the invention (5) When the input signal Vini is an ECL logic low input signal and the input signal VlN2 is an ECL logic high input #, the transistor 17 is on and the transistor 14 is off. The current Ii7 flows into the collector terminal of the electric body 17, and the current I4 into the collector terminal of the transistor 14 is too zero ampere. The voltage at node 29, V29, is roughly equal to Vcc minus the voltage drop across resistor 20. The voltage at node 28, V28, is roughly equal to Vcc. The voltage V0uti on the output terminal 31 is: VoUTl-V2g-VBE21-Vcc-VbE21 where Vb E 21 is the emitter-to-base voltage drop of transistor 2 1. The voltage V0UT2 on the output terminal 32 is: V〇UT2-^ 29-VBE22 = Vcc-VR2〇-VBE22 where VBE22 is the emitter-to-base voltage drop of transistor 22. The input stage 11 is designed to produce a collector current that is substantially independent of voltage and temperature. However, for the output stage 1 2, due to the inherent negative temperature coefficient of the emitter bases of the transistors 21 and 22, an increase in temperature will cause the emitter-to-base voltage drop of the transistors 21 and 22 to decrease. Changes in the emitter-to-base voltage drop cause changes in the output voltage ▽ 01 ^ 1 and VOUT2. The temperature compensation circuit i 3 will compensate the change of the emitter-to-base voltage drop caused by the temperature, so as to compensate the output voltages V0UT 丨 and V0UT2. According to the present invention, the temperature compensation circuit 13 provides temperature compensation of the output logic level. In operation, a voltage vBIAs is sent to the base terminals of the bipolar transistors 23 and 24 connected together. The temperature rise causes the emitter-to-base voltage drop of the bipolar transistors 23 and 24 to decrease, resulting in an increase in the currents l23 and ^. The currents In and la flow through the resistors j 9 and 2 respectively, so the current is -8-the national standard of this paper in a timely manner (CNSM4 specification (210 X 297 cm)) (Mako first read the precautions on the back before filling this page )-Install -------- Order ----

nin 1 «I ο Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 465186 A7 --------- B7__ V. Description of the invention (6) The increase of I23 and 〖24 will lead to resistances 1 9 and 2 0 respectively The increase of the voltage drop causes the voltages of the nodes 28 and 29 to decrease, and further decreases the voltages of the output terminals 31 and 32. Therefore, the temperature compensation circuit 13 compensates for the change in the emitter-to-base voltage drop. FIG. 2 is a circuit diagram of a logic gate 40 according to a second embodiment of the present invention with a temperature compensation circuit. It should be noted that the same reference numerals used in the figures represent the same elements. The logic gate 40 is composed of a differential input stage 41 and an output stage 12 connected to a temperature compensation stage 13. According to this second specific embodiment, the differential input stage 41 includes an N-channel field effect transistor 4 4 and 47 which are connected in common to their source terminals. The source terminals of the field effect transistors 4 4 and 4 7 connected together are connected to the operating voltage source labeled VEE through the current source 48. The field effect transistors 4 4 and 4 7 are connected to the operating voltage source labeled vcc2 through load resistors 49 and 50. The load resistors 49 and 50 form a load circuit of the differential input stage 41. The gate terminals of transistors 4 4 and 4 7 are respectively connected to receive input signals VIN ^ VIN2. It should be noted that the drain and source terminals of a field effect transistor can also be called conductive electrodes, and the gate electrode can also be called a control electrode. Just like the first embodiment, the base terminals of the bipolar transistors 2 1 and 2 2 of the output stage 12 are connected to the nodes 28 and 29 respectively. The collector terminals of the same 'amplifier transistor 21 and 22 are also connected to the nodes 28 and 29, respectively. The operation of the temperature compensation circuit 13 is similar to that in the logic circuit. -9- This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm). -------- Order ---- {Jing first read the precautions on the back before filling in this page)

I ο Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 65186 A7 I --------- B7 V. Description of the invention (7) Figure 3 is a third embodiment of the present invention with a temperature compensation circuit-logic Circuit diagram of gate 51. It should be noted that the same reference numerals used in the figures represent the same components. The logic gate 51 is composed of a differential input stage i i and an output stage 丨 2 connected to a temperature compensation stage 13. According to this third embodiment, the 'differential input stage 1 4 includes an NPN bipolar transistor 14 and 17 which are connected together to their emitter terminals. ^ The bipolar transistor 1 4 and 1 which are connected together The emitter terminal of 7 is connected to the operating voltage source labeled Vee through the current source 18. Bipolar transistors 1 * and 17 (collector terminals are connected to an operating voltage source labeled vcc through load resistors 19 and 20. Load resistors 19 and 20 form a load circuit with a differential input stage ^. The base terminals of crystals 14 and 17 are respectively connected to receive the input signals VIN1 and VIN2. As in the first embodiment, the double terminals of output stage 12 are double-charged to the base terminals of transistors 2 1 and 2 2. Are respectively connected to the nodes 28 and 29. According to this third embodiment, the temperature compensation circuit 13 is composed of a pair of field effect transistors 5 3 and 5 4 having insulated gates. More specifically Ground, the gate terminals of the insulated gate field effect transistors 5 3 and 54 are connected together in common and connected to the bias VBIAS. The source terminals of the insulated gate field effect transistors 5 3 and 54 are Connected to receive the operating voltage source ve E. The drain terminal of the insulated field effect transistor 5 3 is usually the base terminal connected to the bipolar transistor 2], the collector terminal of the bipolar transistor 14 and the resistor 19 on the terminal of node 2 8. The drain of the insulated gate field effect transistor $ 4 is usually Connected to the base terminal of the bipolar transistor _2 2 and the bipolar -10- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling (This page)-Installation -------- Order ---- 4 65186 A7 B7 V. Description of the invention (8) The collector terminal of transistor 17 and the resistor 20 at the terminal 29 of node 29 0 Temperature compensation The operation of the circuit 13 is similar to that of the logic circuit 10. Fig. 4 is a characteristic curve 5 5 of the output logic level of the logic gate with temperature compensation according to the present invention. In the fan garden to ⑽, its level change is small (mV). Curve 57 shows the output high logic level (v0h) in the fan garden whose temperature is from -40 ° C to 125T: Less than about 40 millivolts (mV). At this point, you should be happy to see that a temperature compensation circuit for a logic gate and a method for temperature compensation output logic levels have been provided. The temperature compensation circuit of the present invention improves _40 ° Temperature compensation from C to 125 ° C. In addition, the temperature compensation circuit is easily compatible with high-efficiency dual-carrier circuits The body of the process. Ministry of Economic Affairs Intellectual Property Office employees consumer cooperatives printed quasi-standard country house in the country with a moderately-foot sheets of paper

211 (Class 14) A Fat 97

Claims (1)

Sixth, the scope of patent application A8 B8 C8 D8 Printed by Economic, Intellectual Property, Consumers and Consumers Cooperatives 1. A logic circuit with temperature compensation, including a differential pair, with first and second inputs and One and a second output; an output stage having first and second inputs connected to the respective first and second turns in of the differential pair, and having first and second logic turns out; and A temperature compensation stage having a first terminal, which is directly connected to the first output of the differential pair and the first input of the output stage; a second terminal, which is directly connected to the differential pair A second output and a second input of the output stage; and an input connected to receive a bias signal. 2. The logic circuit according to item 1 of the patent application scope, wherein the differential pair comprises: a current source having at least one conductive terminal; / a first transistor having first and second conductive electrodes and-for connection A control electrode for receiving a first signal, wherein the first conductive electrode is a conductive terminal connected to at least one of the current sources; a second transistor having first and second conductive electrodes and a connection for A control electrode for receiving a second signal, wherein the -transistor =?, The conductive electrode is a? -Conducting and ° load circuit connected to the second transistor, and has a second-conductor connected to the? Rst transistor? The first terminal, and a second terminal connected to the second conductive element of the second transistor (Jing Xianjian read the back of the v note, please fill out this page) -C binding --------- 3. The logic circuit of item 2 of Fan Qingdi, as claimed in the patent, which is the second and second 12- This paper is printed in China National Standard (CNS) A4 specification (210 X 297 mm printed by the Employees ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs) A8 B8 CS D8 6 The transistor in the scope of patent application is a bipolar transistor. 4. For the logic circuit in the scope of the patent application, the load circuit includes one of the passive load or the active load. A circuit in which the second conductive electrode of the first transistor is connected to the second conductive electrode of the second transistor. 6. The logic circuit of item 1 in the patent application scope, wherein the temperature compensation stage includes a first transistor Has a first conductive electrode connected to the first output of the temperature compensation stage and a control electrode connected to the input of the temperature compensation stage; and a second electrode having a connection to the second output of the temperature compensation stage A second conductive electrode and a control electrode connected to the input of the temperature compensation stage. 7. The logic circuit of item 6 of the patent application, wherein the first and second transistors are bipolar transistors. 8. If The logic circuit under the scope of patent application No. 6 wherein the first and second transistors are field effect transistors. 9. A logic circuit includes: a logic gate connected to receive a first A first input signal and a second input signal, wherein the logic gate generates first and second output signals in response to the first and second voltages appearing on the first and second internal nodes respectively; and a temperature compensation circuit connected to To the first and second nodes, the temperature compensation circuit changes the first and second voltages. 10 The logic circuit according to item 9 of the patent application scope, wherein the temperature compensation circuit includes: a first transistor, It has a control electrode and first and second guides -13-This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) --- ----- Order * -------- * Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 ti Q B8 ΛC8 D8 VI. Patent application scope Electric electrode, where the first conductive electrode is connected to The first node, the second conductive electrode is connected to receive an operating voltage source; and a second transistor having a control electrode and first and second conductive electrodes, wherein the first and second transistors are controlled Electrodes are connected Since the first conductive electrode coupled to the second node, and a second conductive electrode coupled to receive the operating voltage source. 11. For example, the logic circuit of item 10 of the patent application scope further includes first and second resistors, wherein the second conductive electrode of the first transistor is connected through the first resistor to receive the operating voltage source, and the A second conductive electrode of the second transistor passes through the second resistor and is connected to receive the operating voltage source. 12. The logic circuit according to item 10 of the patent application, wherein the first and second resistors are NPN bipolar transistors. 13. The logic circuit of item 9 in the patent application scope, wherein the logic gate includes a pair of transistors configured as a common conductive electrode; a first shot-stage follower having a control electrode is connected to the pair A conductive electrode of a first transistor of the transistor; and a second emitter follower having a control electrode 'a conductive electrode connected to the second transistor of the pair of transistors. 14. The logic circuit according to item 13 of the application, wherein the pair of transistors is a pair of bipolar transistors. 15. The logic circuit of item 14 in the scope of patent application, wherein the bipolar transistors are NPN bipolar transistors. _ 16. If you apply for the logic circuit of item 13 of the patent fan garden, where the pair of transistors is -14- This paper size applies to the Chinese national standard (CNSM4 specification (210 X 297 mm) {Please read the precautions on the back before (Fill in this page) -C To -------- Order --------- " 5 ^ 0 · 4 65 AS L l R8 C8 Π8 6. The scope of patent application is a pair of field effect power Crystal. 17. A method for compensating temperature variation in integrated circuits, which includes the steps of: generating first and second currents in response to a first temperature; and using the first and second currents to generate first and A second output voltage; changing one of the first and second currents in response to the second temperature; and using the first and second current changing voltages to generate changed first and second output voltages, respectively. 18. The method of claim 17 in the patent application park, wherein the steps of using the first and second currents further include adding a third current to the first current, and adding a fourth current to the first current. Two currents. 19. The method according to item 18 of the scope of patent application, further comprising using a pair of bipolar transistors to generate the first and second currents, and using a differential pair and a current source to generate the third and second currents. Four voltages. 20. The method of claim 17 in the scope of patent application, wherein the step of generating the first and second currents includes using two bipolar transistors to generate the first and second currents. (Please read the notes on the back before filling out this page) -------- ^ 1 ----- ----Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -15- This paper size applies to China National Standard (CNS) A4 size mo X 297 mm)