WO2000051238A1

WO2000051238A1 - Logic gate having temperature compensation and method

Info

Publication number: WO2000051238A1
Application number: PCT/US2000/003810
Authority: WO
Inventors: Philip A. Jeffery
Original assignee: Semiconductor Components Industries, L.L.C.
Priority date: 1999-02-22
Filing date: 2000-02-15
Publication date: 2000-08-31
Also published as: TW465186B; AU3231600A

Abstract

A logic gate (10) having temperature compensation. The logic gate (10) includes an input stage (11) and an emitter follower output stage (12) coupled to a temperature compensation circuit (13). The temperature compensation circuit (13) includes a pair of bipolar transistors (23, 24) that generate temperature dependent currents (I23, I24). The temperature dependent currents (I23, I24) alter the voltages appearing at the respective base terminals of the emitter follower output stage (12). The altered voltages compensate for temperature variations of the emitter follower output stage (12).

Description

LOGIC GATE HAVING TEMPERATURE COMPENSATION AND METHOD

Background of the Invention

The present invention relates, in general, to logic circuits and, more particularly, to temperature compensation of logic circuits.

Basic logic circuits are used in a wide variety of applications including automotive, aerospace, computer, industrial machinery, etc. In many of these applications, it is desirable for the output logic levels to be independent of temperature to prevent degradation of noise margins . In logic circuits using emitter followers to generate the output logic levels, temperature compensation circuitry should be included with the logic gate to prevent degradation of the noise margins of the output logic levels . Without temperature compensation, the output logic levels vary due to the negative temperature coefficient associated with the base-to-emitter junction of the bipolar transistor. As the temperature increases, the base-to-emitter voltage decreases, and conversely, as the temperature decreases, the base-to-emitter voltage increases.

One technique for providing temperature compensation is to couple a resistor that is in series with back-to- back diodes between the collector terminals of an input differential pair. This technique degrades the switching performance of bipolar transistors that are manufactured using high performance bipolar processes. Further, this technique does not provide adequate compensation at temperatures below about 25 degrees Celsius (°C).

Accordingly, it would be advantageous to have a temperature compensated logic circuit capable of providing temperature compensation at temperatures below 25 °C. It would be of further advantage for the circuit to be manufacturable in an integrated circuit manufacturing process.

Brief Description of the Drawings

FIG. 1 is a schematic diagram of a logic gate connected to a temperature compensation network in accordance with a first embodiment of the present invention; FIG. 2 is a schematic diagram of a logic gate connected to a temperature compensation network in accordance with a second embodiment of the present invention;

FIG. 3 is a schematic diagram of a logic gate connected to a temperature compensation network in accordance with a third embodiment of the present invention; and

FIG. 4 is a characteristic curve of the output logic levels of logic gates having temperature compensation in accordance with the present invention.

Detailed Description of the Drawings

FIG. 1 is a schematic diagram illustrating a logic gate 10 having temperature compensation in accordance with a first embodiment of the present invention. Logic gate 10 is comprised of a differential input stage 11 and an output stage 12 coupled to a temperature compensation stage 13. By way of example, differential input stage 11 includes a pair of NPN bipolar transistors 14 and 17 having their emitter terminals coupled to a current source 18 via resistors 15 and 16, respectively. Current source 18 is connected to a source of operating potential, labeled V_EE. The collector terminals of bipolar transistors 14 and 17 are coupled to a source of operating potential, labeled V_cc, via load resistors 19 and 20. Load resistors 19 and 20 form a load circuit of differential input stage 11. The base terminals of transistors 14 and 17 are coupled for receiving input signals V_IN1 and V_IN2, respectively.

It should be noted that the emitter and collector terminals of a bipolar transistor are also referred to as conduction electrodes and the base terminal is also referred to as a control electrode. Output stage 12 is comprised of a pair of bipolar transistors 21 and 22 coupled in an emitter follower configuration. Accordingly, the base terminal of bipolar transistor 21 is commonly connected to the collector terminal of bipolar transistor 14 and to load resistor 19 at node 28; whereas the base terminal of bipolar transistor 22 is commonly connected to the collector terminal of bipolar transistor 17 and to load resistor 20 at node 29. The collector terminals of bipolar transistors 21 and 22 are coupled for receiving the source of operating potential V_cc. Typically, the emitter terminals of bipolar transistors 21 and 22 are left floating to allow the end user to couple a desired load to logic gate 10. It should be noted that the end user typically drives a 50 Ohm load with logic gate 10. Therefore, logic gate 10 is shown to be driving two 50 Ohm resistors 33 and 34. In particular, resistor 33 is coupled between output node 31 and a bias voltage V_^ and resistor 34 is coupled between output node 32 and bias voltage V-_^. Output signals V_ouτl and V_ouτ2 are produced at nodes 31 and 32, respectively.

Temperature compensation circuit 13 is comprised of a pair of bipolar transistors 23 and 24 and a pair of resistors 25 and 26. More particularly, the base terminals of bipolar transistors 23 and 24 are commonly connected together and to a bias potential V . It should be understood that V_BIAS is a regulated voltage that may range between approximately 0.8 volts + V_EE to approximately 1.2 volts + V_EE over a temperature range from -40 °C to 125 °C, respectively. The emitter terminals of bipolar transistors 23 and 24 are coupled for receiving the source of operating potential, V_EE, via resistors 25 and 26, respectively. The collector terminal of bipolar transistor 23 is commonly connected to the base terminal of bipolar transistor 21, the collector terminal of bipolar transistor 14, and one terminal of resistor 19 at node 28. The collector terminal of bipolar transistor 24 is commonly connected to the base terminal of bipolar transistor 22 , the collector terminal of bipolar transistor 17, and one terminal of resistor 20 at node 29.

Although the emitter terminals of bipolar transistors 23 and 24 are described as being coupled to the source of operating potential via resistors 25 and 26, respectively, it should be understood this is not a limitation of the present invention. For example, the emitter terminals of bipolar transistors 23 and 24 may be connected directly to the source of operating potential . In operation, input signals V_IN1 and V_IN2 are applied to the base terminals of transistors 14 and 17, respectively. For the purposes of this example, V_cc is approximately 0 volts, V_EE is approximately -5.2 volts, V_BIAΞ is approximately -4.2 volts, V_π is approximately -2 volts, an ECL logic high signal is approximately -0.9 volts, and an ECL logic low signal is approximately -1.7 volts. It should be understood that the voltage levels described herein merely serve as examples and are not limitations of the present invention. It should be further understood that the differential input stage is not limited to receiving differential input signals, i.e., the differential input stage can be coupled for receiving a differential input signal or a single-ended input signal. In the case of a single ended input signal, the base terminal of one of transistors 14 and 17 is coupled for receiving a reference voltage, commonly referred to as V_BB, while the base terminal of the other transistor is coupled for receiving a time varying voltage signal.

When input signal V_IN1 is an ECL logic high input signal and input signal V_IN2 is an ECL logic low input signal, transistor 14 is rendered conductive and transistor 17 is rendered non-conductive. A current I₁₄ flows in the collector terminal of transistor 14, while the current I₁₇ flowing in the collector terminal of transistor 17 is substantially zero amperes. The voltage appearing at a node 28, V₂₈, is approximately equal to V_cc less the voltage drop across resistor 19, whereas the voltage appearing at node 29, V₂₉, is approximately equal to V_cc. The voltage V_0OT1, appearing at output terminal 31 is given by:

^V0UT1 ^{_ V}28 ~ ^BE21 ^— "CC ~ ^R19 ~~ "BE21 where V_BE21 is the base-to-emitter voltage drop across transistor 21.

The voltage, V_ouτ2, appearing at output terminal 32 is given by:

^VOUT2 ^{— V}29 ^VBE22 ^— "cc ~ "BE22 where V_EE22 is the base-to-emitter voltage drop across transistor 22.

When input signal V_ral is an ECL logic low input signal and input signal V_IN2 is an ECL logic high input signal, transistor 17 is rendered conductive and transistor 14 is rendered non-conductive. Current I₁₇ flows in the collector terminal of transistor 17, while the current I₁₄ flowing in the collector terminal of transistor 14 is substantially zero amperes. The voltage appearing at a node 29, V₂₉, is approximately equal to V_cc less the voltage drop across resistor 20, whereas the voltage appearing at node 28, V₂₈, is approximately equal to V_cc. The voltage V_ouτl, appearing at output terminal 31 is given by:

^V0UT1 ^{"" V}28 ^{_ V}BE21 ^— " cC ~ BE21

where V_BE21 is the base-to-emitter voltage drop across transistor 21.

The voltage, V_ouτ2, appearing at output terminal 32 is given by:

"OUT2 ~ ^V29 ~ ^VBE22 ^— "CC ~^" "R20 ~^* ^BE22

where V_BE22 is the base-to-emitter voltage drop across transistor 22.

Input stage 11 is designed to produce collector currents that are substantially independent of voltage and temperature. However, for output stage 12, an increase in temperature causes the base-to-emitter voltage drops across transistors 21 and 22 to decrease due to the inherent negative coefficient of temperature associated with the base-emitter junctions of transistors 21 and 22. The change in the base-to-emitter voltage drops results in a change in the output voltages V_ouτl and V_ouτ2. Temperature compensation circuit 13 compensates for the changes in the base-to-emitter voltage drop due to temperature, thereby compensating the output voltages V_ouτl ^and v_ouτ2.

In accordance with the present invention, temperature compensation circuit 13 provides temperature compensation of the output logic levels. In operation, a voltage, V_BIAS, is applied to the commonly connected base terminals of bipolar transistors 23 and 24. An increase in temperature lowers the base-to-emitter voltage drops across bipolar transistors 23 and 24 and results in an increase in currents I₂₃ and I₂₄. Currents I₂₃ and I_2i flow through resistors 19 and 20, respectively, thereby increasing the voltage drops across resistors 19 and 20 and lowering the voltages at nodes 28 and 29 as well as at output terminals 31 and 32, respectively. Thus, temperature compensation circuit 13 compensates for the changes in base-to-emitter voltage drops .

FIG. 2 is a schematic diagram illustrating a logic gate 40 having temperature compensation in accordance with a second embodiment of the present invention. It should be noted that the same reference numbers are used in the figures to represent the same elements. Logic gate 40 is comprised of a differential input stage 41 and output stage 12 coupled to temperature compensation stage 13. In accordance with the second embodiment, differential input stage 41 includes a pair of N-channel field effect transistors 44 and 47 having their source terminals commonly connected together. The commonly connected source terminals of field effect transistors 44 and 47 are coupled to a source of operating potential, labeled V_EE, via a current source 48. The drain terminals of field effect transistors 44 and 47 are coupled to a source of operating potential, labeled V_cc, via load resistors 49 and 50. Load resistors 49 and 50 form a load circuit of differential input stage 41. The gate terminals of transistors 44 and 47 are coupled for receiving input signals V_IN1 and V^, respectively. It should be noted that the drain and source terminals of a field effect transistor are also referred to as conduction electrodes and the gate terminal is also referred to as a control electrode. As in the first embodiment, the base terminals of bipolar transistors 21 and 22 of output stage 12 are connected to nodes 28 and 29, respectively. Likewise, the collector terminals of bipolar transistors 23 and 24 are connected to nodes 28 and 29, respectively. The operation of temperature compensation circuit 13 is similar to that described for logic circuit 10.

FIG. 3 is a schematic diagram illustrating a logic gate 51 having temperature compensation in accordance with a third embodiment of the present invention. It should be noted that the same reference numbers are used in the figures to represent the same elements . Logic gate 51 is comprised of a differential input stage 11 and output stage 12 coupled to temperature compensation stage 13. In accordance with the third embodiment, differential input stage 14 includes a pair of NPN bipolar transistors 14 and 17 having their emitter terminals commonly connected together. The commonly connected emitter terminals of bipolar transistors 14 and 17 are coupled to a source of operating potential, labeled V_EE, via a current source 18. The collector terminals of bipolar transistors 14 and 17 are coupled to a source of operating potential, labeled V_cc, via load resistors 19 and 20. Load resistors 19 and 20 form a load circuit of differential input stage 11. The base terminals of transistors 14 and 17 are coupled for receiving input signals V_IN1 and V^, respectively.

As in the first embodiment, the base terminals of bipolar transistors 21 and 22 of output stage 12 are connected to nodes 28 and 29, respectively.

In accordance with the third embodiment, temperature compensation circuit 13 is comprised of a pair of insulated gate field effect transistors 53 and 54. More particularly, the gate terminals of insulated gate field effect transistors 53 and 54 are commonly connected together and to a bias potential V_BIAS. The source terminals of insulated gate field effect transistors 53 and 54 are coupled for receiving the source of operating potential, V_EE. The drain terminal of insulated gate field effect transistor 53 is commonly connected to the base terminal of bipolar transistor 21, the collector terminal of bipolar transistor 14, and one terminal of resistor 19 at node 28. The drain terminal of insulated gate field effect transistor 54 is commonly connected to the base terminal of bipolar transistor 22, the collector terminal of bipolar transistor 17, and one terminal of resistor 20 at node 29.

The operation of temperature compensation circuit 13 is similar to that described for logic circuit 10. FIG. 4 is a characteristic curve 55 of the output logic levels of logic gates having temperature compensation in accordance with the present invention. Curve 56 shows that the output low logic level (V_0L) varies by less than approximately 100 millivolts (mV) over a temperature ranging between -40 C and 125 C. Curve 57 shows that the output high logic level (V_0H) varies by less than approximately 40 millivolts (mV) over a temperature ranging between -40 C and 125 C.

By now it should be appreciated that a temperature compensation circuit for a logic gate and a method for temperature compensating the output logic levels have been provided. The temperature compensation circuit of the present invention has improved compensation over the temperature range from -40 C and 125 C. Further, the temperature compensation circuit is readily compatible with processes capable of manufacturing high performance bipolar transistors.

Claims

1. A logic circuit having temperature compensation, comprising: a differential pair having first and second inputs and first and second outputs; an output stage having first and second inputs coupled to the respective first and second outputs of the differential pair, and having first and second logic circuit outputs; and a temperature compensation stage having a first terminal directly connected to the first output of the differential pair and to the first input of the output stage, a second terminal directly connected to the second output of the differential pair and to the second input of the output stage, and an input coupled for receiving a bias signal.

2. The logic circuit of claim 1, wherein the differential pair comprises: a current source having at least one conduction terminal; a first transistor having first and second conduction electrodes and a control electrode coupled for receiving a first signal, wherein the first conduction electrode is coupled to the at least one conduction terminal of the current source; a second transistor having first and second conduction electrodes and a control electrode coupled for receiving a second signal, wherein the first conduction electrode of the first transistor is coupled to the first conduction electrode of the second transistor; and load circuitry having a first terminal coupled to the second conduction electrode of the first transistor and a second terminal coupled to the second conduction electrode of the second transistor.

3. The logic circuit of claim 2, wherein the first and second transistors are bipolar transistors.

4. The logic circuit of claim 2, wherein the load circuitry comprises one of a passive load or an active load.

5. The logic circuit of claim 2, wherein the second conduction electrode of the first transistor is coupled to the second conduction electrode of the second transistor.

6. The logic circuit of claim 1, wherein the temperature compensation stage comprises a first transistor having a first conduction electrode coupled to the first output of the temperature compensation stage and a control electrode coupled to the input of the temperature compensation stage and a second transistor having a second conduction electrode coupled to the second output of the temperature compensation stage and a control electrode coupled to the input of the temperature compensation stage.

7. The logic circuit of claim 6, wherein the first and second transistors are bipolar transistors.

8. The logic circuit of claim 6, wherein the first and second transistors are field effect transistors.

9. A logic circuit comprising: a logic gate coupled for receiving first and second input signals, wherein the logic gate generates first and second output signals in response to first and second output signals in response to first and second voltages appearing a first and second internal nodes, respectively; and a temperature compensation circuit coupled to the first and second nodes, wherein the temperature compensation circuit alters values of the first and second voltages.

10. The logic circuit of claim 9, wherein the temperature compensation circuit comprises: a first transistor having a control electrode and first and second conduction electrodes, wherein the first conduction electrode is coupled to the first node and the second conduction electrode is coupled for receiving a source of operating potential; and a second transistor having a control electrode and first and second conduction electrodes, wherein the control electrodes of the first and second transistors are coupled together, the first conduction electrode is coupled to the second node, and the second conduction electrode is coupled for receiving the source of operating potential.

11. The logic circuit of claim 10, further including first and second resistors, wherein the second conduction electrode of the first transistor is coupled for receiving the source of operating potential via the first resistor, and the second conduction electrode of the second transistor is coupled for receiving the source of operating potential via the second resistor.

12. The logic circuit of claim 10, wherein the first and second resistors are NPN bipolar transistors.

13. The logic circuit of claim 9, wherein the logic gate includes a pair of transistors in a common conduction electrode configuration, a first emitter follower having a control electrode coupled to a conduction electrode of a first transistor of the pair of transistors, and a second emitter follower having a control electrode coupled to a control electrode of a second transistor of the pair of transistors.

14. The logic circuit of claim 13, wherein the pair of transistors is a pair of bipolar transistors.

15. The logic circuit of claim 14, wherein the bipolar transistors are NPN bipolar transistors.

16. The logic circuit of claim 13, wherein the pair of transistors is a pair of field effect transistors.

17. A method for compensating for temperature variations in an integrated circuit, comprising the steps of: generating first and second currents in response to a first temperature; using the first and second currents in the generation of first and second output voltages, respectively; changing values of the first and second currents in response to a second temperature; and using the changed values of the first and second currents to generate altered first and second output voltages, respectively.

18. The method of claim 17, wherein the step of using the first and second currents further includes summing a third current with the first current and summing a fourth current with the second current.

19. The method of claim 18, further including using a pair of bipolar transistors to generate the first and second currents and using a differential pair and a current source to generate the third and fourth voltages .

20. The method of claim 17, wherein the step of generating first and second currents includes using two bipolar transistors to generate the first and second currents .