TW463463B - Data receiver - Google Patents

Data receiver Download PDF

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Publication number
TW463463B
TW463463B TW089125180A TW89125180A TW463463B TW 463463 B TW463463 B TW 463463B TW 089125180 A TW089125180 A TW 089125180A TW 89125180 A TW89125180 A TW 89125180A TW 463463 B TW463463 B TW 463463B
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TW
Taiwan
Prior art keywords
transistor
clock signal
reference voltage
voltage
response
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Application number
TW089125180A
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Chinese (zh)
Inventor
Ki-Whan Song
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Samsung Electronics Co Ltd
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Publication of TW463463B publication Critical patent/TW463463B/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/013—Modifications of generator to prevent operation by noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
    • H03K3/356139—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption

Abstract

A data receiver is provided for stabilizing a reference voltage to which input data is compared. The data receiver includes a differential amplification flip flop for comparing input data to a reference voltage in response to a clock signal, an amplifier for amplifying the results of the comparison, a latch for storing the logic level of the input data, and a counter coupling circuit for reducing the variation of the reference voltage caused by the operation of the differential amplification flip flop in response to an inverted clock signal. In the data receiver, the reference voltage is stably preserved without minimized variation. Also, there is substantially no consumption of direct current (DC) when the data receiver operates.

Description

A7 B7 46 3 46 3 6959pif. doc/00 6 五、發明說明（I ) 本發明是有關於一種半導體積體電路，且特別是有 關於一種穩定在資料接收器中之參考電壓之裝置與方法= 資料接收器電路之先前描敘可在由B丄ua等人之〗SSC (1998 年 10 月）之”A 2.6 Gbyte/s multipurpose Chip-to-Chip interface”中找到。 第1圖顯示包括第一、第二與第三級11、12與13之 傳統資料接收器10。第一級11包括用於比較輸入資料(DIN) 與參考電壓（VREF)之比較器，第二級12包括用以感應與 放大第一級11之輸出之感應放大器正反器（SAFF)〇第三 級13包括如S-R栓鎖器之栓鎖器，用以栓鎖第二級12之 輸出。 第一級11之比較器係由偏壓電壓BIAS所致能，以 比較輸入資料（DIN)與參考電壓（VREF)。因此，參考電壓 (VREF)需要穩定，而沒有波動。參考電壓(VREF)與偏壓電 壓BIAS具有既定DC準位，且由傳統電壓產生器所提供。 第二級12之SAFF係回應於時脈信號（CLK)而致能，以放 大第一級11所比較之結果。第三級13利用S-R栓鎖器而 穩定地栓鎖第二級12之輸出。 參考電壓（VREF)需要穩定於一準位間，沒有波動， 以提供第一級11之穩定操作。因此，電壓產生器產生參 考電壓(VREF)以具有定電壓。然而，當要施加至第一級時， 參考電壓（VREF)係變動。迫是，當第一級之比較器操作而 偏壓電壓BIAS正在作用時，參考電壓（VREF)之電位係被 在VREF線之耦合電容値造成變動，此耦合電容値包括在 4 (請先閱讀背面之注意事項再填寫本頁) 裝ill·! —訂---------線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNSM4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4 6 3 46 3 五、發明說明（1) 參考電壓（VREF)線與NMOS電晶體MN之汲極X間之耦合 電容，以及在參考電壓（VREF)線與NMOS電晶體MN之源 極Y間之耦合電容。此耦合電容，係必然地且寄生性產生 於電晶體之製造’代表在閘極與汲極間或閘極與源極間之 電容。 由耦合電容所造成之參考電壓（VREF)之準位變動係 稱爲反彈(kick-back)雜訊。反彈雜訊可由在參考電壓(VREF) 線與接地電壓VSS(未示出）間連接分流電容而減少。此分 流電容係設定成具有比耦合電容較大之電容値，且減少由 耦合電容在VREF線上所造成之反彈雜訊。 然而，當增加分流電容時，所產生之問題在於，接 地電壓VSS之電壓反彈係大大地耦合至參考電壓(VREF)。 VREF線之電壓準位之變動會降低操作速度’或造成 當比較VREF與輸入資料DIN之電壓時之錯誤動作。 因而，需要資料接收器，其能穩定地操作’而避免 參考電壓(VREF)因爲接地電壓之反彈、反彈雜訊或相似訊 號而變動。 本發明之一實施例提供一資料接收器，以回應於時 脈信號而接收輸入資料。此資料接收器包括：一接收器’ 回應於該時脈信號而比較該輸入資料與一參考電壓’放大 該比較結果’且儲存該輸入資料之邏輯準位；以及一計數 稱合電路，回應於一反相時脈信號，而補償由該接收器所 造成之該參考電壓之變動。 較好是，該接收器，包括：一第一與第二預充電單 5 家標準（CNS)A4 規格（210 X 297 公釐) " I — JI — ΙΊ 裝 i — ll·— — 訂 il· — · — —··^ {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 6 3 46 3 A7 6959pif.doc/006 _^_B7___ 五、發明說明（> ) 元，用以回應於該反相時脈信號而起始該接收器至一電源 電壓；以及一比較器，回應於該時脈信號而比較該輸入資 料與該參考電壓。 該比較器較好包括：一第一與第二反相器，交叉耦 合，分別連接至該些預充電單元，其中該第一反相器之該 輸出係連接至該第二反相器之該輸入，而該第一反相器之 該輸入係連接至該第二反相器之該輸出；一第一與第二比 較電晶體，分別連接至該些反相器之該些輸出，且分別受 控制於該輸入資料與該參考電壓；以及一開關電晶體，連 接於該些比較電晶體與一接地電壓間，且回應於該時脈信 號而受控制。 該計數耦合電路，根據本發明之一較佳實施例，包 括：一第一電晶體，其源極連接至一電源電壓，該第一電 晶體係回應於連接至該第一電晶體之該閘極之該反相時脈 信號而受控制；一第二電晶體，其源極連接至該第一電晶 體之該汲極，該第二電晶體係回應於連接至該第二電晶體 之該閘極之該參考電壓而受控制；一第三電晶體，其爲二 極體型，其源極連接至該第二電晶體之汲極，其閘極與汲 極係彼此相連接；以及一第四電晶體，其汲極連接至該第 三電晶體之該汲極，其源極連接至一電源電壓，該第四電 晶體係回應於連接至該第四電晶體之該閘極之該反相時脈 信號而受控制。 根據本發明之另一實施例，提供一種資料接收器， 回應於一時脈信號而接收輸人資料。該資料接收器包括： {請先閲讀背面之注意事項再填寫本頁) -裝-! l·! — 訂------ιϊί& 本紙張尺度適用_國國家標準（CNS)A4規格（2〗〇χ297公釐） A7 B7 463463 6959pif.doc/006 五、發明說明（（(：） 一第一與第二預充電單元，用以回應於一反相時脈信號而 起始該接收器至一電源電壓。該資料接收器更包括：一第 -與第二反相器，交叉耦合，分別連接至該第一與第二預 充電單元，其中該第一反相器之該輸出係連接至該第二反 相器之該輸入，而該第-反相器之該輸入係連接至該第二 反相器之該輸出。該資料接收器也包括：一第一與第二比 較電晶體，分別連接至該第一與第二反相器之該些輸出， 且分別受控制於該輸入資料與該參考電壓。較好，該資料 接收器包括：一開關電晶體，連接於該些比較電晶體與一 接地電壓間，且回應於該時脈信號而受控制。該資料接收 器也包括：一第一電晶體，其源極連接至一電源電壓，該 第一電晶體係回應於連接至該第一電晶體之該閘極之該反 相時脈信號而受控制；一第二電晶體，其源極連接至該第 一電晶體之該汲極，該第二電晶體係回應於連接至該第二 電晶體之該閘極之該參考電壓而受控制；一第三電晶體， 其爲二極體型，其源極連接至該第二電晶體之汲極，其閘 極與汲極係彼此相連接；以及一第四電晶體，其汲極連接 至該第三電晶體之該汲極，其源極連接至一電源電壓，該 第四電晶體係回應於連接至該第四電晶體之該閘極之該反 相時脈信號而受控制。 根據本發明之又一實施例，資料接收器包括：差動 正反器，以比較輸入資料與參考電壓：栓鎖器，具有一設 定端與一重設端，以栓鎖該差動放大正反器之輸出；一計 數耦合電路，連接至該參考電壓，以補償該參考電壓之變 7 — — — — — — I-HI—.i 裝 _ I — L I — I 訂. — — I —--I 梭 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 463463 6 9 5 91 :/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（<) 動寬度約30%。 較好是，該差動正反器包括一開關電晶體，回應於 一時脈信號而致能一比較器，該比較器回應於該時脈信號 而比較該輸入資料與該參考電壓。 該計數耦合電路，較好包括依序連接於一電源電壓 與一接地端間之四個電晶體，以補償參考電壓，其中連接 至電源電壓之第二電晶體係受控制於該比較器之參考電壓 輸入。該比較器包括：一第一比較電晶體，以接收該輸入 資料；以及一第二比較電晶體，以接收該補償後參考電壓。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 圖式之簡單說明： 第1圖繪示傳統資料接收器； 第2圖繪示依照本發明一較佳實施例之資料接收器； 第3圖繪示在第2圖之差動放大資料接收器之參考電 壓中之耦合雜訊之電路圖； 第4圖繪示在第2圖之資料接收器中之模型化計數耦 合電路；以及 第5圖繪示根據是否採用第2圖之資料接收器之參考 電壓（VREF)變動之模擬結果； 各別圖示中之相似參考符號係代表相同或相似元 件。 標號說明：A7 B7 46 3 46 3 6959pif.doc / 00 6 V. Description of the Invention (I) The present invention relates to a semiconductor integrated circuit, and in particular to a device and method for stabilizing a reference voltage in a data receiver = A previous description of the data receiver circuit can be found in "A 2.6 Gbyte / s multipurpose Chip-to-Chip interface" by B 丄 ua et al. SSC (October 1998). Fig. 1 shows a conventional data receiver 10 including first, second and third stages 11, 12, and 13. The first stage 11 includes a comparator for comparing input data (DIN) with a reference voltage (VREF), and the second stage 12 includes a sense amplifier flip-flop (SAFF) for sensing and amplifying the output of the first stage 11. The third stage 13 includes a latch, such as an SR latch, to lock the output of the second stage 12. The comparator of the first stage 11 is enabled by the bias voltage BIAS to compare the input data (DIN) with the reference voltage (VREF). Therefore, the reference voltage (VREF) needs to be stable without fluctuations. The reference voltage (VREF) and the bias voltage BIAS have a predetermined DC level and are provided by a conventional voltage generator. The SAFF of the second stage 12 is enabled in response to the clock signal (CLK) to enlarge the comparison result of the first stage 11. The third stage 13 uses an S-R latch to stably lock the output of the second stage 12. The reference voltage (VREF) needs to be stable between a certain level without fluctuations to provide stable operation of the first stage 11. Therefore, the voltage generator generates a reference voltage (VREF) to have a constant voltage. However, when applied to the first stage, the reference voltage (VREF) varies. It is imperative that when the first stage comparator operates and the bias voltage BIAS is acting, the potential of the reference voltage (VREF) is changed by the coupling capacitance 値 on the VREF line. This coupling capacitance 値 is included in 4 (please read first Note on the back, please fill out this page again) Install ill ·! —Order --------- Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with Chinese national standards (CNSM4 specification (210 X 297) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 3 46 3 V. Description of the invention (1) Coupling capacitance between the reference voltage (VREF) line and the drain X of the NMOS transistor MN, and the reference voltage (VREF ) Line and the NMOS transistor MN source Y coupling capacitor. This coupling capacitor is necessarily and parasitic generated from the transistor's manufacturing 'represents the capacitance between the gate and the drain or between the gate and the source The level change of the reference voltage (VREF) caused by the coupling capacitor is called kick-back noise. The bounce noise can be connected between the reference voltage (VREF) line and the ground voltage VSS (not shown). The shunt capacitor is reduced. This shunt capacitor is set It has a larger capacitance than the coupling capacitance, and reduces the bounce noise caused by the coupling capacitance on the VREF line. However, when the shunt capacitance is increased, the problem is that the voltage rebound of the ground voltage VSS is greatly coupled. To the reference voltage (VREF). A change in the voltage level of the VREF line will reduce the operation speed 'or cause an erroneous operation when comparing the voltage of VREF and the input data DIN. Therefore, a data receiver is needed, which can operate stably' and Avoid reference voltage (VREF) changes due to ground voltage bounce, bounce noise, or similar signals. One embodiment of the present invention provides a data receiver to receive input data in response to a clock signal. The data receiver includes: A receiver 'compares the input data with a reference voltage to' amplify the comparison result 'and stores the logic level of the input data in response to the clock signal; and a counting and combining circuit responds to an inverted clock signal While compensating for changes in the reference voltage caused by the receiver. Preferably, the receiver includes: a first and a second precharge Single 5 standard (CNS) A4 specifications (210 X 297 mm) " I — JI — ΙΊ Equipment i — ll · — — Order il · — · — — ·· ^ {Please read the precautions on the back before filling (This page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 3 46 3 A7 6959pif.doc / 006 _ ^ _ B7___ V. Description of the invention (>) Yuan, which is used to start in response to the inverse clock signal The receiver to a power supply voltage; and a comparator that compares the input data with the reference voltage in response to the clock signal. The comparator preferably includes: a first and a second inverter, which are cross-coupled and connected to the precharge units, respectively, wherein the output of the first inverter is connected to the second inverter. Input, and the input of the first inverter is connected to the output of the second inverter; a first and a second comparison transistor are respectively connected to the outputs of the inverters, and Controlled by the input data and the reference voltage; and a switching transistor connected between the comparison transistors and a ground voltage and controlled in response to the clock signal. The counting coupling circuit according to a preferred embodiment of the present invention includes a first transistor whose source is connected to a power supply voltage, and the first transistor system responds to the gate connected to the first transistor. The inverse clock signal of the electrode is controlled; a second transistor whose source is connected to the drain of the first transistor, and the second transistor system responds to the second transistor The reference voltage of the gate is controlled; a third transistor, which is a diode type, whose source is connected to the drain of the second transistor, and whose gate and drain are connected to each other; and a first A four transistor whose drain is connected to the drain of the third transistor, whose source is connected to a power supply voltage, and the fourth transistor system responds to the reaction of the gate connected to the fourth transistor. The phase clock signal is controlled. According to another embodiment of the present invention, a data receiver is provided to receive input data in response to a clock signal. The data receiver includes: {Please read the precautions on the back before filling out this page) -Install-! L ·! — Order ------ ιϊί & This paper is applicable to _National Standard (CNS) A4 specifications ( 2〗 〇χ297mm) A7 B7 463463 6959pif.doc / 006 V. Description of the invention (((:) A first and second pre-charging unit for starting the receiver in response to an inverted clock signal To a power supply voltage. The data receiver further includes: a first- and a second inverter, cross-coupled and connected to the first and second pre-charging units, respectively, wherein the output of the first inverter is connected To the input of the second inverter, and the input of the -inverter is connected to the output of the second inverter. The data receiver also includes: a first and a second comparison transistor , Respectively connected to the outputs of the first and second inverters, and respectively controlled by the input data and the reference voltage. Preferably, the data receiver includes a switching transistor connected to the comparisons. The transistor is connected to a ground voltage and is controlled in response to the clock signal. The material receiver also includes a first transistor whose source is connected to a power supply voltage, and the first transistor system is controlled in response to the inverse clock signal of the gate connected to the first transistor. A second transistor whose source is connected to the drain of the first transistor, and the second transistor system is controlled in response to the reference voltage of the gate connected to the second transistor; A third transistor whose source is connected to the drain of the second transistor and whose gate and drain are connected to each other; and a fourth transistor whose drain is connected to the first transistor The source of the drain of the triode is connected to a power supply voltage, and the fourth transistor system is controlled in response to the inverse clock signal of the gate connected to the fourth transistor. In yet another embodiment, the data receiver includes: a differential flip-flop to compare input data with a reference voltage: a latch with a set end and a reset end to latch the output of the differential amplifier flip-flop ; A count coupling circuit connected to the reference voltage to compensate Change of reference voltage 7 — — — — — — I-HI—.i equipment_ I — LI — I order. — — I —-- I shuttle (Please read the precautions on the back before filling this page) Wisdom of the Ministry of Economic Affairs Printed by the Employees ’Cooperatives of the Property Bureau This paper is printed in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 463463 6 9 5 91: / 006 A7 B7 Printed by the Employees’ Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (≪) The moving width is about 30%. Preferably, the differential flip-flop includes a switching transistor, which enables a comparator in response to a clock signal, and the comparator compares the clock signal in response to the clock signal. The input data and the reference voltage. The counting coupling circuit preferably includes four transistors connected in sequence between a power supply voltage and a ground terminal to compensate the reference voltage. The second transistor system connected to the power supply voltage is subject to Controlled by the comparator's reference voltage input. The comparator includes: a first comparison transistor to receive the input data; and a second comparison transistor to receive the compensated reference voltage. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 shows Traditional data receiver; Figure 2 shows a data receiver according to a preferred embodiment of the present invention; Figure 3 shows a circuit diagram of coupling noise in the reference voltage of the differentially amplified data receiver of Figure 2; Fig. 4 shows the modeled counting coupling circuit in the data receiver of Fig. 2; and Fig. 5 shows the simulation result according to whether the reference voltage (VREF) of the data receiver of Fig. 2 is adopted; Similar reference symbols in the figures represent the same or similar elements. Label description:

S I ( Ί---Ί f --ill·--ί 訂----—----终 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS>A4規格（210 * 297公釐） A7 B7 463463 6959pif.doc/006 五、發明說明（么） 10、100 :資料接收器 11 :第一級 12 :第二級 13 :第三級 20 :差動放大正反器 30 : S-R栓鎖器 40 :計數耦合電路 21 :第一預充電單元 24 :第二預充電單元 22、 25 : PMOS 電晶體 23、 26 : NMOS 電晶體 27 ' 28 :電晶體 29 :開關電晶體 41 :第一(PMOS)電晶體 42 :第二(PMOS)電晶體 43 :第三(PMOS)電晶體 44 :第四(NM0S)電晶體 較佳富施例 附圖描敘本發明之較佳實施例，且係可參考以了解 本發明之優點，其操作與伴隨本發明之操作之目的。 之後，本發明係藉由參考附圖來詳細解釋本發明之 較佳實施例而描敘。各別圖示中之相似參考符號係代表相 同或相似元件。 參考第2圖，其顯示本發明之較佳實施例之資料接收 I 1---I — I- J -裝！ l·!— 訂----I --- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用t S國家標準（CNS)A4規格（210 X 297公釐） 463463 6959pif.doc/006 五、發明說明（q ) 器’該資料接收器100包括差動放大正反器20，S-R栓鎖 器30與計數耦合電路40。 差動放大正反器20回應於時脈信號(CLK)比較輸入資 料與參考電壓（VREF)。差動放大正反器20包括第-與第 二預充電單元21與24。第一與第二預充電單元21與24 回應於該時脈信號(CLK)與比較器(CMP)。CMP包括交叉耦 合反相器INV1與INV2,其分別連接至第一與第二預充電 單元21與24。交叉耦合反相器INV1與INV2比較分別連 接至交叉耦合反相器INV1與INV2之電晶體27與28。電 晶體27與28係由輸入資料(DIN)與參考電壓(VREF)控制， 且開關電晶體29連接於比較電晶體27、28以及接地端VSS 間。開關電晶體29係回應於時脈信號(CLK)而致能。 在S-R栓鎖器30之操作中，當邏輯高準位係由設定 端S所接收，輸出信號(〇UT)係設成邏輯高準位。當邏輯 高準位係由設定端S所接收，輸出信號（OUT)係設成邏輯 低準位。 計數耦合電路40包括第一(PM0S)電晶體41，其回應 於反相時脈信號(/CLK)而受控制；第二（PM0S)電晶體42， 其回應於參考電壓（VREF)而受控制；二極電晶體型之第三 (PM0S)電晶體43 ;以及第四(NM0S)電晶體44，其回應於 反相時脈信號(/CLK)而受控制。第一至第四電晶體41〜44， 係依序彼此連接於電源電壓（VDD)與第二接地端VSS間。 也就是，第一（PM0S)電晶體41具有連接至電源電壓 (VDD)之源極，且係回應於連接至其閘極之反相時脈信號 本紙張尺度適用中國圉家標準（CNS)A4規格（210*297公楚） (請先閱讀背面之注^h項再填寫本頁) *^-----^---訂------1!%· 4 6 3 6 3 6959pif .doc/006 _B7___ 五、發明說明（分） (請先閱讀背面之注意事項再填寫本頁) 而受限制。第二（PM0S)電晶體42之源極連接至第一電晶 體之汲極。第二（PM0S)電晶體42係回應於連接至其閘極 之參考電壓而受限制。二極體型之第三（PM0S)電晶體43 之源極連接至第二電晶體之汲極，且其閘極與汲極係彼此 連接。第四電晶體44之汲極連接至第三電晶體之汲極， 且其源極連接至第二接地端VSS，且係回應於連接至其閘 極之反相時脈信號而受限制。 將描敘，根據假設爲輸入資料(DIN)之電壓係低於參 考電壓（VrEF)時，資料接收器1〇〇之操作。第一與第二預 充電單元21與24係回應於時脈信號（CLK)之下降邊緣而 導通，使得節點N1與N2係受電源電壓（VDD)之充電。此 時，CMP並不動作，因爲CMP內之開關電晶體29係處於 關閉狀態。之後，開關電晶體29係回應於時脈信號（CLK) 之上升邊緣而導通，使得CMP受到致能。因爲輸入資料(DIN) 之電壓係低於參考電壓（VREF)，流經第一比較電晶體27 之電流II係低於流經第二比較電晶體28之電流12。 經濟部智慧財產局員工消費合作社印製 也就是，因爲流經第—比較電晶體2 8之電流12係相 當高，節點N2之電壓係變低。節點N2之變低後電壓係被 比較器(CMP)內之第一交叉耦合反相器INV1所接收，因而 增加節點N1之電位。節點N1之變高後電壓係被比較器 (CMP)內之第二交叉耦合反相器INV2所接收，因而更降低 節點N2之電位。藉由重複這些動作，節點N1變成邏輯高 電位，而節點N2變成邏輯低電位。SI (Ί --- Ί f --ill · --ί order ------------ final (please read the precautions on the back before filling out this page) This paper size applies the Chinese National Standard (CNS > A4 Specifications (210 * 297 mm) A7 B7 463463 6959pif.doc / 006 V. Description of the invention (10) 100: Data receiver 11: First stage 12: Second stage 13: Third stage 20: Differential amplification Flip-flop 30: SR latch 40: Count coupling circuit 21: First pre-charge unit 24: Second pre-charge unit 22, 25: PMOS transistor 23, 26: NMOS transistor 27 '28: Transistor 29: Switching transistor 41: first (PMOS) transistor 42: second (PMOS) transistor 43: third (PMOS) transistor 44: fourth (NM0S) transistor The preferred embodiment can be referred to to understand the advantages of the present invention, its operation and the purpose accompanying the operation of the present invention. Hereinafter, the present invention is described by explaining the preferred embodiment of the present invention in detail with reference to the drawings. The similar reference symbols in the respective figures represent the same or similar elements. Referring to FIG. 2, it shows the data receiving of the preferred embodiment of the present invention. I 1 --- I — I- J -Pack! L ·! — Order ---- I --- (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Paper size applies to national standard (CNS) A4 specifications (210 X 297 mm) 463463 6959pif.doc / 006 V. Description of the invention (q) device 'The data receiver 100 includes a differential amplifier flip-flop 20, SR plug The latch 30 and the count coupling circuit 40. The differential amplifier flip-flop 20 compares the input data with a reference voltage (VREF) in response to the clock signal (CLK). The differential amplifier flip-flop 20 includes first and second precharge units. 21 and 24. The first and second precharge units 21 and 24 respond to the clock signal (CLK) and the comparator (CMP). The CMP includes cross-coupled inverters INV1 and INV2, which are connected to the first and the second, respectively. Two pre-charging units 21 and 24. The cross-coupled inverters INV1 and INV2 are respectively connected to the transistors 27 and 28 of the cross-coupled inverters INV1 and INV2. The transistors 27 and 28 are composed of the input data (DIN) and the reference voltage. (VREF) control, and the switching transistor 29 is connected between the comparison transistors 27 and 28 and the ground terminal VSS. The switching transistor 29 is Corresponding to the clock signal (CLK) can be caused when in S-R latch 30 of operating, when the logic high level is received by the system set terminal S, the output signal (〇UT) lines is set to a logic high level. When the logic high level is received by the setting terminal S, the output signal (OUT) is set to the logic low level. The count coupling circuit 40 includes a first (PM0S) transistor 41 which is controlled in response to an inverted clock signal (/ CLK); a second (PM0S) transistor 42 which is controlled in response to a reference voltage (VREF) A third (PM0S) transistor 43 of a bipolar transistor type; and a fourth (NM0S) transistor 44 which are controlled in response to an inverted clock signal (/ CLK). The first to fourth transistors 41 to 44 are sequentially connected to each other between a power supply voltage (VDD) and a second ground terminal VSS. That is, the first (PM0S) transistor 41 has a source connected to a power supply voltage (VDD), and responds to an inverse clock signal connected to its gate. This paper is compliant with China National Standard (CNS) A4. Specifications (210 * 297 Gongchu) (Please read the note ^ h on the back before filling this page) * ^ ----- ^ --- Order ------ 1!% · 4 6 3 6 3 6959pif .doc / 006 _B7___ 5. Description of the invention (minutes) (please read the precautions on the back before filling this page) and be restricted. The source of the second (PM0S) transistor 42 is connected to the drain of the first transistor. The second (PM0S) transistor 42 is limited in response to a reference voltage connected to its gate. The source of the diode-type third (PM0S) transistor 43 is connected to the drain of the second transistor, and its gate and drain are connected to each other. The drain of the fourth transistor 44 is connected to the drain of the third transistor, and its source is connected to the second ground terminal VSS, and is limited in response to an inverting clock signal connected to its gate. The operation of the data receiver 100 will be described based on the assumption that the voltage of the input data (DIN) is lower than the reference voltage (VrEF). The first and second pre-charging units 21 and 24 are turned on in response to the falling edge of the clock signal (CLK), so that the nodes N1 and N2 are charged by the power supply voltage (VDD). At this time, the CMP does not operate because the switching transistor 29 in the CMP is turned off. Thereafter, the switching transistor 29 is turned on in response to the rising edge of the clock signal (CLK), so that the CMP is enabled. Because the voltage of the input data (DIN) is lower than the reference voltage (VREF), the current II flowing through the first comparison transistor 27 is lower than the current 12 flowing through the second comparison transistor 28. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs That is, because the current 12 flowing through the first-comparison transistor 28 is relatively high, the voltage at the node N2 becomes low. After the voltage at node N2 goes low, it is received by the first cross-coupled inverter INV1 in the comparator (CMP), thereby increasing the potential of node N1. After the voltage at node N1 becomes high, it is received by the second cross-coupled inverter INV2 in the comparator (CMP), thereby further reducing the potential of node N2. By repeating these actions, the node N1 becomes a logic high potential and the node N2 becomes a logic low potential.

邏輯高電位節點N1係被S-R栓鎖器30之重.設端R 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐） 463463 69 5 9pi f- doc/〇 五、發明說明（?） 所接收，使得其輸出信號（out)係重設爲邏輯低電位。輸 出信號（OUT)之重設符合於輸入資料（DiN)之電壓係低於參 考電壓(VREF)之假設’使得資料接收器100之輸出係邏輯 低電位。 將描敘，根據假設爲輸入資料(DIN)之電壓係高於參 考電壓(VREF)時，資料接收器100之操作。在此情況下， 流經第一比較電晶體27之電流Π係高於流經第二比較電 晶體28之電流12。因而，節點N1之電壓係變低。節點N1 之變低後電壓係被比較器(CMP)內之第二交叉耦合反相器 INV2所接收，因而增加節點N2之電位。節點N2之變高 後電壓係被比較器(CMP)內之第一交叉耦合反相器INV1所 接收，因而更降低節點N1之電位。藉由重複這些動作， 節點N1變成邏輯低電位，而節點N2變成邏輯高電位。 邏輯高電位節點N2係被S-R栓鎖器30之設定端S 所接收，使得其輸出信號(OUT)係設定爲邏輯高電位。輸 出信號（OUT)之設定符合於輸入資料（din)之電壓係低於參 考電壓(VREF)之假設’使得資料接收器100之輸出係邏輯 高電位。 如上所述’資料接收器100可在不需偏壓電壓BIAS 下操作’相較於由偏壓電壓BIAS所致能之第1圖中之傳 統資料接收器10。因此，在資料接收器1〇〇之例中，不會 出現偏壓電壓BIAS所造成之DC消耗。 第3圖顯示在第2圖之資料接收器1〇〇中之參考電壓 (VREF)線上造成反彈雜訊之分流電容値之電路圖同樣 n n n n n JJ ί I* » 1 1 - n n I n n n _aJ* n 1 n i f f t> t (請先閲讀背面之注意事項再填窝本頁) '我張尺度適用中國國家標準（CNS)A4規格（210 X 297 6959pi f.doc/006The logic high potential node N1 is weighted by the SR latch 30. Setting end R This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) 463463 69 5 9pi f-doc / 〇 5. Invention Explanation (?) Is received so that its output signal (out) is reset to a logic low. The reset of the output signal (OUT) is in accordance with the assumption that the voltage of the input data (DiN) is lower than the reference voltage (VREF), so that the output of the data receiver 100 is a logic low potential. The operation of the data receiver 100 will be described based on the assumption that the voltage of the input data (DIN) is higher than the reference voltage (VREF). In this case, the current Π flowing through the first comparative transistor 27 is higher than the current 12 flowing through the second comparative transistor 28. Therefore, the voltage of the node N1 becomes low. After the voltage at node N1 goes low, it is received by the second cross-coupled inverter INV2 in the comparator (CMP), thereby increasing the potential of node N2. After the voltage at node N2 becomes high, the voltage is received by the first cross-coupled inverter INV1 in the comparator (CMP), thereby lowering the potential of node N1. By repeating these actions, the node N1 becomes a logic low potential and the node N2 becomes a logic high potential. The logic high potential node N2 is received by the setting terminal S of the S-R latch 30, so that its output signal (OUT) is set to a logic high potential. The setting of the output signal (OUT) is in accordance with the assumption that the voltage of the input data (din) is lower than the reference voltage (VREF), so that the output of the data receiver 100 is a logic high potential. As described above, the 'data receiver 100 can be operated without a bias voltage BIAS' as compared to the conventional data receiver 10 in the first figure enabled by the bias voltage BIAS. Therefore, in the case of the data receiver 100, the DC consumption caused by the bias voltage BIAS does not occur. Figure 3 shows the circuit diagram of the shunt capacitor 造成 that causes bounce noise on the reference voltage (VREF) line in the data receiver 100 of Figure 2. nnnnn JJ ί I * »1 1-nn I nnn _aJ * n 1 niff t > t (Please read the precautions on the back before filling in this page) 'We use Chinese National Standard (CNS) A4 specifications (210 X 297 6959pi f.doc / 006)

五、發明說明（/P) 463463 地’第3圖顯示，在時脈信號(CLK)之下降邊緣時，連接 至參考電壓（VREF)線之電路路徑之等效或模型。就是，第 3圖顯示第二預充電單元24，第二反相器INV2內之NM〇s 電晶體26，第二比較電晶體28與開關電晶體29彼此連接 之路徑。在此，第二反相器INV2內之NMOS電晶體26係 模型化爲二極體型電晶體，其汲極與閘極係彼此連接，因 爲第2圖之節點N1與N2在時脈信號(CLK)之下降邊緣處 由預充電單元21與24充電而具相同電壓。 在模型化耦合路徑之例中，寄生耦合電容存在於第 二比較電晶體28之閘極/汲極間，以及閘極/源極間。寄生 耦合電容造成在VREF線之電壓變的。也就是，參考電壓 (VREF)係耦合至在節點a與b之電壓準位中之變動，因而 有變動。 節點a之電壓，在開始時，係從0V改變至，在時脈 信號(CLK)之下降邊緣時，將電源電壓（VDD)減去第二反相 器INV2內之NMOS電晶體26之臨界電壓(Vtn)所獲得之電 壓(VDD-Vtn)。因此，節點a之電壓變化，如，係（VDD-Vtn)-0，也就是VDD-Vtn。節點b之電壓，在開始時，係 從0V改變至，在時脈信號(CLK)之下降邊緣時，將參考電 壓(VREF)減去第二比較電晶體28之臨界電壓（Vtn)所獲得 之電壓（VREF-Vtn)，因爲開關電晶體29係在時脈信號(CLK) 之F降邊緣時關閉。因此，節點b之電壓變化，Ab，係 (VREF-Vtn)-O，也就是 VREF-Vtn。 因此，節點a與b之電壓變化總和（如+仙）’也就是 本紙張尺度適用中國國家標準（CNS)A4規袼（210 * 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝-----„----訂*1 線 經濟部智慧財產局員工消費合作社印製 A7 B7 6 9 5 9pi f. doc / 0 0 6 五、發明說明（//) VDD+VREF-2Vtn，經由耦合電容改變參考電壓（VREF)之電 壓。如果 VDD 是 2.5V，VREF 是 1.25V，Vtn 是 0.5V，電 壓變化總和（如+灿)是2.75V。 第4圖是耦合路徑之等效或模型化電路圖，其上，第 3圖之模型所顯示之參考電壓（VREF)之變化，係由計數耦 合電容40所補償。在模型化耦合路徑之例中，寄生耦合 電容存在於第二PMOS電晶體42之閘極/汲極，與閘極/源 極間。寄生耦合電容造成（VREF)線之電壓變動，且補償第 3圖之模型所示之參考電壓（VREF)之變動。 參考電壓(VREF)係耦合至在節點c與d之電壓準位中 之變動，因而有變動。節點c之電壓，在開始時，係從電 源電壓（VDD)改變至，將參考電壓（VREF)加上第二PMOS 電晶體42之臨界電壓（Vtp)所獲得之電壓（VREF+ | Vtp | )， 因爲在時脈信號（CLK)下降邊緣時，第一 PMOS電晶體係 關閉。因此，節點c之電壓變化，△<；，係（VREF+丨Vtp | +VDD。節點d之電壓，在開始時，係從電源電壓（VDD)改 變至第三PMOS電晶體43之臨界電壓(Vtp)，因爲在時脈 信號(CLK)下降邊緣時，第二PMOS電晶體係導通。因此， 節點d之電壓變化，Ad，係| Vtp | -VDD。 因此，節點c與d之電壓變化總和(Ac+Ad)，也就是 VREF+2 | Vtp卜VDD，經由耦合電容改變參考電壓（VREF) 之電壓。如果 VDD 是 2.5V，VREF 是 1.25V，| Vtp 丨是 0.5V， 電壓變化總和（Ac+Ad)是-2.75V。 因此，節點a與b之電壓變化總和（Δίΐ+ΔΙ))，其改變 本紙張尺度適用中囷國家標準（CNS)A4規格（210 X 297公爱） — in.---1 — I I l· I I —tT-1 — — —--I I (請先閱讀背面之注意事項再填寫本頁> 經濟部智慧財產局員工消費合作社印製 46346 3 經濟部智慧財產局員工消費合作社印製 A7 69 5 9pi f ^ d〇c/ 006 β? 五、發明說明（丨之） 如第3圖之模型所示之參考電壓(VREF)之電壓’爲2.75V ’ 補償節點c與d之電壓變化總和(ΔαΜ) ’其改變如第3圖 之計數耦合電路所執行之模型所示之參考電壓（VREF)2電 壓，係-2.75V。兩電壓變化(如+灿)與（&+加)彼此補償’使 得參考電壓（VREF)幾乎沒有變化° 因此，在根據本發明之資料接收器中’參考電壓係 穩定維持而沒有變動’使得輸入資料⑴ΪΝ)係比較於正確 之參考電壓（VREF)，且因而相關邏輯準位係輸出當成比較 結果。第5圖顯示當本發明之資料接收器應用計數耦合電 路時，以及當本發明之資料接收器沒有應用計數耦合電路 時，在參考電壓（VREF)之變動上所進行之模擬。 在第5圖中，輸入資料(DIN)係同步接收於時脈信號 (CLK)，且參考電壓(VREF)係設成1.4V。可由第5圖看出， 當沒有應用計數耦合電路時，參考電壓（VREF)在每個時脈 信號(CLK)之邊緣從1.36V變動到1.42。變動寬度係分配於 1.0之任意値。 另一方面，當應用計數耦合電路時，參考電壓(VREF) 在每個時脈信號(CLK)之邊緣從1.37V變動到1.41。因此， 參考電壓（VREF)之變動寬度係約0.7，相比當沒有應用計 數耦合電路時之1.0之任意分配變動寬度。因此，明顯地， 當應用計數耦合電路時，參考電壓（VREF)之變動寬度係減 少約30%，比起當沒有應用計數耦合電路時之參考電壓 (VREF)變動寬度。所用之計數耦合電路之電容値，係簡單 分流電容値之一半，且提供即使接地電壓有反彈時之穩定 參紙張尺度適用_國國家標準（CNS>A4規格（210 X 297公3 ) (請先閱讀背面之注意事項再填寫本頁) 裝-----^! —訂---------線 A7 B7 463 4b 3 6959pif.doc/006 五、發明說明（I V) 度。 綜上所述，雖然本發明已以一較佳實施例揭露如上， 然其並非用以限定本發明，任何熟習此技藝者，在不脫離 本發明之精神和範圍內，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者爲 準。 <請先閱讀背面之注意事項再填寫本頁) 線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）V. Description of the invention (/ P) 463463 Ground 'The third figure shows the equivalent or model of the circuit path connected to the reference voltage (VREF) line at the falling edge of the clock signal (CLK). That is, FIG. 3 shows a path in which the second pre-charging unit 24, the NMOS transistor 26 in the second inverter INV2, and the second comparison transistor 28 and the switching transistor 29 are connected to each other. Here, the NMOS transistor 26 in the second inverter INV2 is modeled as a diode transistor, and its drain and gate are connected to each other, because nodes N1 and N2 in Figure 2 are in the clock signal (CLK ) Is charged at the falling edge by the pre-charging units 21 and 24 and has the same voltage. In the example of the modeled coupling path, the parasitic coupling capacitance exists between the gate / drain and the gate / source of the second comparison transistor 28. The parasitic coupling capacitance causes the voltage on the VREF line to change. That is, the reference voltage (VREF) is coupled to a change in the voltage levels of the nodes a and b, and thus changes. The voltage of the node a is changed from 0V to the beginning. At the falling edge of the clock signal (CLK), the power supply voltage (VDD) is subtracted from the threshold voltage of the NMOS transistor 26 in the second inverter INV2 (Vtn) The obtained voltage (VDD-Vtn). Therefore, the voltage of node a changes, for example, (VDD-Vtn) -0, that is, VDD-Vtn. The voltage of node b is changed from 0V to the beginning, and is obtained by subtracting the reference voltage (VREF) from the threshold voltage (Vtn) of the second comparison transistor 28 at the falling edge of the clock signal (CLK). The voltage (VREF-Vtn), because the switching transistor 29 is turned off at the F-falling edge of the clock signal (CLK). Therefore, the voltage change at node b, Ab, is (VREF-Vtn) -O, which is VREF-Vtn. Therefore, the sum of the voltage changes of nodes a and b (such as + sen) 'is the Chinese standard (CNS) A4 (210 * 297 mm) for this paper size (Please read the precautions on the back before filling this page ) Install ----- „---- Order * 1 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 6 9 5 9pi f. Doc / 0 0 6 V. Description of Invention (//) VDD + VREF -2Vtn, change the voltage of the reference voltage (VREF) through the coupling capacitor. If VDD is 2.5V, VREF is 1.25V, Vtn is 0.5V, the sum of the voltage changes (such as + Can) is 2.75V. Figure 4 is the coupling path An equivalent or modeled circuit diagram, in which the change in the reference voltage (VREF) shown in the model in Figure 3 is compensated by the count coupling capacitor 40. In the example of the modeled coupling path, the parasitic coupling capacitor exists in the first The gate / drain and the gate / source of the two PMOS transistor 42. The parasitic coupling capacitance causes the voltage variation of the (VREF) line, and compensates for the variation of the reference voltage (VREF) shown in the model in Figure 3. The reference voltage (VREF) is coupled to changes in the voltage levels of nodes c and d, and therefore changes The voltage of the node c is changed from the power supply voltage (VDD) to the voltage (VREF + | Vtp |) obtained by adding the reference voltage (VREF) to the threshold voltage (Vtp) of the second PMOS transistor 42, Because at the falling edge of the clock signal (CLK), the first PMOS transistor system is turned off. Therefore, the voltage change at node c, △ <;, (VREF + 丨 Vtp | + VDD. The voltage at node d is at the beginning It is changed from the power supply voltage (VDD) to the threshold voltage (Vtp) of the third PMOS transistor 43 because the second PMOS transistor system is turned on when the clock signal (CLK) falls. Therefore, the voltage at the node d changes. , Ad, is | Vtp | -VDD. Therefore, the sum of the voltage changes at the nodes c and d (Ac + Ad), that is, VREF + 2 | Vtp and VDD, changes the voltage of the reference voltage (VREF) via the coupling capacitor. If VDD It is 2.5V, VREF is 1.25V, | Vtp 丨 is 0.5V, and the total voltage change (Ac + Ad) is -2.75V. Therefore, the sum of the voltage changes of nodes a and b (Δίΐ + ΔΙ)), which changes the paper Standards apply to China National Standard (CNS) A4 specification (210 X 297 public love) — in .--- 1 — II l · II —TT-1 — — —-- II (Please read the notes on the back before filling out this page> Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 46346 3 Printed by the Employees’ Cooperative of the Intellectual Property Bureau of the Ministry of Economy A7 69 5 9pi f ^ doc / 006 β? V. Description of the invention (丨 of) The voltage of the reference voltage (VREF) shown in the model in Figure 3 is 2.75V 'The sum of the voltage changes of the compensation nodes c and d (ΔαΜ) 'The change is the reference voltage (VREF) 2 voltage shown in the model implemented by the counting coupling circuit in Figure 3, which is -2.75V. The two voltage changes (such as + can) and (& + plus) compensate each other 'so that the reference voltage (VREF) hardly changes. Therefore, in the data receiver according to the present invention, the' reference voltage system is stably maintained without change 'makes The input data (N) is compared to the correct reference voltage (VREF), and thus the relevant logic level output is used as the comparison result. Fig. 5 shows the simulation of the variation of the reference voltage (VREF) when the data receiver of the present invention applies a count coupling circuit and when the data receiver of the present invention does not apply a count coupling circuit. In Figure 5, the input data (DIN) is received synchronously with the clock signal (CLK), and the reference voltage (VREF) is set to 1.4V. It can be seen from Fig. 5 that when the count coupling circuit is not applied, the reference voltage (VREF) changes from 1.36V to 1.42 at the edge of each clock signal (CLK). The change width is assigned to any arbitrary 1.0. On the other hand, when a count coupling circuit is applied, the reference voltage (VREF) changes from 1.37V to 1.41 at the edge of each clock signal (CLK). Therefore, the variation width of the reference voltage (VREF) is about 0.7, compared with an arbitrary distribution variation width of 1.0 when a count coupling circuit is not applied. Therefore, it is clear that when the count coupling circuit is applied, the variation width of the reference voltage (VREF) is reduced by about 30%, compared with the reference voltage (VREF) variation width when the count coupling circuit is not applied. The capacitance 计数 of the counting coupling circuit used is half of the simple shunt capacitance 且, and it provides stable reference parameters even when the ground voltage has rebounded. The paper size is applicable. _National Standards (CNS > A4 Specification (210 X 297 Male 3)) (Please first Read the precautions on the back and fill in this page.) -------- ^! —Order --------- line A7 B7 463 4b 3 6959pif.doc / 006 5. Description of the invention (IV). Summary As mentioned above, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. ≪ Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Applicable to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

經濟部智慧財產局員工消費合作社印製 4 6 3 46 3 6959pif.doc/006 六、申請專利範圍 1. 一種資料接收器，回應於一時脈信號而接收輸入 資料，該資料接收器包括： --接收器，回應於該時脈信號而比較該輸入資 料與一參考電壓，放大該比較結果，且儲存該輸入資料之 邏輯準位；以及 一計數耦合電路，回應於該時脈信號，而補償 由該接收器之一或多個電晶體所造成之該參考電壓之變 動。 2. 如申請專利範圍第1項所述之資料接收器，其中 該計數耦合電路包括耦合至該參考電壓之一或多個電晶 體，且回應於一反相時脈信號。 3. 如申請專利範圍第2項所述之資料接收器，其中 該一或多個電晶體包括： 一第一電晶體，其源極連接至一電源電壓，該 第一電晶體係回應於連接至該第一電晶體之該閘極之該反 相時脈信號而受控制： 一第二電晶體，其源極連接至該第一電晶體之 該汲極，該第二電晶體係回應於連接至該第二電晶體之該 閘極之該參考電壓而受控制； 一第三電晶體，其爲二極體型，其源極連接至 該第二電晶體之汲極，其閘極與汲極係彼此相連接；以及 一第四電晶體，其汲極連接至該第三電晶體之 該汲極，其源極連接至一電源電壓，該第四電晶體係回應 於連接至該第四電晶體之該閘極之該反相時脈信號而受控 (請先閱讀背面之注意事項再填寫本頁) ------— —訂------I I 雀*^ I _ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 463463 :/006 AS B8 C8 D8 六 經濟部智慧財產局員工消費合作社印製 申請專利範圍 制。 4. 如申請專利範圍第1項所述之資料接收器，包括： 一第一與第二預充電單元，用以回應於該反相 時脈信號而起始該接收器至一電源電壓；以及 一比較器，回應於該時脈信號而比較該輸入資 料與該參考電壓。 5. 如申請專利範圍第2項所述之資料接收器，其中 該比較器包括： 一第一與第二反相器，交叉耦合，分別連接至 該些預充電單元，其中該第一反相器之該輸出係連接至該 第二反相器之該輸入，而該第一反相器之該輸入係連接至 該第二反相器之該輸出； 一第一與第二比較電晶體，分別連接至該些反 相器之該些輸出，且分別受控制於該輸入資料與該參考電 壓；以及 一開關電晶體，連接於該些比較電晶體與一接 地電壓間，且回應於該時脈信號而受控制。 6. 一種資料接收器，回應於一時脈信號而接收輸入 資料，該資料接收器包括： 一第一與第二預充電單元，用以回應於一反相 時脈信號而起始該接收器至一電源電壓； 一第一與第二反相器，交叉耦合，分別連接至 該第一與第二預充電單元，其中該第一反相器之該輸出係 連接至該第二反相器之該輸入，而該第一反相器之該輸入 (請先閱讀背面之注意事項再填寫本頁) ^•丨|-----訂·!------線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） 4 6 3 4 6 3 as B8 6959pif.doc/006 惡 六、申請專利範圍 係連接至該第二反相器之該輸出； 一第一與第二比較電晶體，分別連接至該第 與第二反相器之該些輸出，且分別受控制於該輸入資料與 該參考電壓； 一開關電晶體，連接於該些比較電晶體與一接 地電壓間，且回應於該時脈信號而受控制； 一第一電晶體，其源極連接至一電源電壓，該 第一電晶體係回應於連接至該第一電晶體之該閘極之該反 相時脈信號而受控制； 一第二電晶體，其源極連接至該第一電晶體之 該汲極，該第二電晶體係回應於連接至該第二電晶體之該 閘極之該參考電壓而受控制； 一第三電晶體，其爲二極體型，其源極連接至 該第二電晶體之汲極，其閘極與汲極係彼此相連接；以及 一第四電晶體，其汲極連接至該第三電晶體之 該汲極，其源極連接至一電源電壓，該第四電晶體係回應 於連接至該第四電晶體之該閘極之該反相時脈信號而受控 制。 經濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 7. 如申請專利範圍第6項所述之資料接收器，更包 括一栓鎖器，其具有分別用以接收該些反相器之該些輸出 之一設定端與一重設端，以儲存該輸入資料之該邏輯準 位。 8. 一種資料接收器，回應於一時脈信號而接收輸入 資料，該資料接收器包括： 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 6 3 46 3 g88 6959pif.doc/006 轉 六、申請專利範圍 j妾收器，回應於該時脈信號而比較該輸入資 料與一參考電壓，且用以栓鎖一比較器之該輸出，該參考 電壓係施加至一 NM0S電晶體之閘極，該參考電壓在該 N Μ ◦ S電晶體回應於該時脈信號之動作期間具有電壓變 動；以及 -計數耦合電路，具有一或多個M0S電晶體， 其中該參考電壓係施加至一 PM0S電晶體，以補償該參考 電壓在該PM0S電晶體回應於一反相時脈信號之動作期間 所具有之電壓變動。 9.如申請專利範圍第8項所述之資料接收器，其中該 計數耦合電路更包括一第二PM0S電晶體，用來將該PM0S 電晶體耦合到一電壓供應源，該反相時脈信號係施加至該 第二PM0S電晶體的閘極。 (請先閱讀背面之注意事項再填寫本頁) .衣.-------訂----I ( I--線I 經濟部智慧財產局員工消費合作社印^ί 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 3 46 3 6959pif.doc / 006 6. Scope of Patent Application 1. A data receiver that receives input data in response to a clock signal. The data receiver includes:- The receiver compares the input data with a reference voltage in response to the clock signal, amplifies the comparison result, and stores the logic level of the input data; and a counting coupling circuit responds to the clock signal and compensates for A change in the reference voltage caused by one or more transistors of the receiver. 2. The data receiver as described in item 1 of the patent application scope, wherein the counting coupling circuit includes one or more electric crystals coupled to the reference voltage and responds to an inverted clock signal. 3. The data receiver according to item 2 of the patent application scope, wherein the one or more transistors include: a first transistor whose source is connected to a power supply voltage, and the first transistor system responds to the connection The inverse clock signal to the gate of the first transistor is controlled: a second transistor whose source is connected to the drain of the first transistor, and the second transistor system responds to The reference voltage of the gate connected to the second transistor is controlled; a third transistor, which is a diode type, whose source is connected to the drain of the second transistor, and whose gate and drain The poles are connected to each other; and a fourth transistor whose drain is connected to the drain of the third transistor and whose source is connected to a power supply voltage, the fourth transistor system responds to the fourth transistor The gate of the transistor is controlled by the inverting clock signal (please read the precautions on the back before filling in this page) -------- --Order ------ II Tit * ^ I _ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 463463: / 006 AS B8 C8 D8 Economic Affairs Intellectual Property Office employees consumer cooperatives printed patent scope system. 4. The data receiver according to item 1 of the patent application scope, comprising: a first and a second pre-charging unit for initiating the receiver to a power supply voltage in response to the inverse clock signal; and A comparator compares the input data with the reference voltage in response to the clock signal. 5. The data receiver according to item 2 of the scope of patent application, wherein the comparator comprises: a first and a second inverter, cross-coupled and connected to the precharge units, respectively, wherein the first inverter The output of the inverter is connected to the input of the second inverter, and the input of the first inverter is connected to the output of the second inverter; a first and a second comparison transistor, Respectively connected to the outputs of the inverters and controlled by the input data and the reference voltage; and a switching transistor connected between the comparison transistors and a ground voltage and responding to the time Pulse signal. 6. A data receiver for receiving input data in response to a clock signal, the data receiver comprising: a first and a second pre-charging unit for starting the receiver in response to an inverted clock signal to A power supply voltage; a first and a second inverter, cross-coupled and connected to the first and the second precharge unit, respectively, wherein the output of the first inverter is connected to the second inverter This input, and this input of the first inverter (Please read the precautions on the back before filling this page) ^ • 丨 | ----- Order ·! ------ Line · This paper size applies China National Standard (CNS) A4 specification (210 * 297 mm) 4 6 3 4 6 3 as B8 6959pif.doc / 006 Evil 6. The scope of patent application is the output connected to the second inverter; a first And the second comparison transistor are respectively connected to the outputs of the first and second inverters, and are respectively controlled by the input data and the reference voltage; a switching transistor is connected between the comparison transistors and a Ground voltage, and controlled in response to the clock signal; a first transistor Body, whose source is connected to a power supply voltage, the first transistor system is controlled in response to the inverse clock signal of the gate connected to the first transistor; a second transistor whose source is The drain connected to the first transistor, the second transistor system is controlled in response to the reference voltage of the gate connected to the second transistor; a third transistor, which is a diode type Its source is connected to the drain of the second transistor, its gate and drain are connected to each other; and a fourth transistor whose drain is connected to the drain of the third transistor, its source The electrode is connected to a power voltage, and the fourth transistor system is controlled in response to the inverse clock signal of the gate connected to the fourth transistor. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) 7. The data receiver described in item 6 of the scope of patent application, including a latch, which has a separate use A setting terminal and a reset terminal for receiving the outputs of the inverters are stored to store the logic level of the input data. 8. A data receiver that receives input data in response to a clock signal, the data receiver includes: This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 6 3 46 3 g88 6959pif.doc / 006 六 、 Patent application range j 妾 receiver, in response to the clock signal, compares the input data with a reference voltage, and is used to latch the output of a comparator, the reference voltage is applied to an NMOS The gate of the crystal, the reference voltage having a voltage change during the operation of the N Μ S transistor in response to the clock signal; and a count coupling circuit having one or more M0S transistors, where the reference voltage is applied To a PMOS transistor to compensate for the voltage variation of the reference voltage during the action of the PMOS transistor in response to an inverse clock signal. 9. The data receiver according to item 8 of the scope of patent application, wherein the counting coupling circuit further includes a second PM0S transistor for coupling the PM0S transistor to a voltage supply source, and the inverse clock signal Is applied to the gate of the second PMOS transistor. (Please read the precautions on the back before filling out this page). Clothing .------- Order ---- I (I--line I printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ ί This paper size applies China National Standard (CNS) A4 specification (210 X 297 mm)
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