TW463354B - Method for reducing resistance value of metal conducting wire - Google Patents
Method for reducing resistance value of metal conducting wire Download PDFInfo
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- TW463354B TW463354B TW89125536A TW89125536A TW463354B TW 463354 B TW463354 B TW 463354B TW 89125536 A TW89125536 A TW 89125536A TW 89125536 A TW89125536 A TW 89125536A TW 463354 B TW463354 B TW 463354B
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46335 4 五、發明說明(l) 發明之領域 本發明提供一種降低一含鋁之金屬導線阻值的方法。 背景說明 多重金屬化製程(multilevel metallization process)是利用數層的金屬導線層來將半導體晶片上的各 個金属氧化半導體(metal oxide semiconductor, M0S)元 件彼此串接起來,以形成堆疊化迴路的架構。由於多重金 屬化製程可以提尚半導體晶片的積集度(integration), 因此被廣泛地應用於各種超大型積體電路(very large scale integration, VLSI)的製程 ° 圖一為習知一金屬導線以及複數個接觸插塞的結構 圖,習知金屬導線層鋁-銅/鈦/氮化鈦結構的製作流程 通常是先以錢錄法於半導體晶片表面沉積一紹金屬廣。然 而由於i呂原子的電致遷移(electron migration)現象,可 能導致金屬銘線的斷路(open),因此習知技術大多是利用 在鋁金屬中加入含量約0. 5%到4%之間的銅,來防止斷路機 構的發生。 , 隨後再於鋁銅金屬1 0的表面沉積一鈦金屬層1 2,沉積 的厚度約在200到500埃(angstrom)之間,接下來是於鈦金46335 4 V. Description of the Invention (l) Field of the Invention The present invention provides a method for reducing the resistance of a metal wire containing aluminum. Background Description A multilevel metallization process uses a plurality of metal wire layers to serially connect metal oxide semiconductor (MOS) components on a semiconductor wafer to each other to form a stacking circuit architecture. Because the multiple metallization process can improve the integration of semiconductor wafers, it is widely used in various very large scale integration (VLSI) processes. Figure 1 shows a conventional metal wire and For the structure diagrams of the plurality of contact plugs, it is known that the manufacturing process of the metal wire layer aluminum-copper / titanium / titanium nitride structure is generally to deposit a metal film on the surface of the semiconductor wafer by the money recording method. 5% 至 4% 之间 的 However, due to the electromigration of electron atoms (electron migration), which may cause the metal name line to open (open), most of the conventional techniques use the content of about 0.5% to 4% in aluminum metal. Copper to prevent the occurrence of disconnection mechanism. Then, a titanium metal layer 12 is deposited on the surface of the aluminum copper metal 10, and the thickness is about 200 to 500 angstroms, followed by titanium gold.
4 6 335 4 五、發明說明(2) 屬層1 2表面形成一厚度約為5 0 0到1 5 0 0埃之間層氮化鈦層 作為阻障層1 4。一般而言,阻障層1 4有兩種不同的製作方 法,一種是對鈦金屬層12進行一氣化反應 (Nitridation),以於欽金屬層12表面形成一層氮化飲 層;另一種則是以反應性濺鍍的方法,直接於鈦金屬層1 2 表面沉積一層化鈦層。 在完成金屬導線層的結構之後,接著再利用黃光暨蝕 刻製程來定義出金屬導線的圖案。隨後於M0S電晶體與各 個金屬導線層之間形成一介電層(dielectrics layer), 用來隔離並保護半導體晶片上的元件。而為了使這些MOS 電晶體元件能與各個金屬導線層順利地電連接以形成一個 完整的電子裝置,在進行多重金屬化製程時,必須於這些 介電層内形成接觸插塞(contact plug),作為各M0S電晶 體與金屬導線層之間電連接的導線。 習知製作一半導體晶片表面上之接觸插塞的方法是先 於一介電層16上形成複數個插塞洞(plug hole),並通達 至欲對外電連接的導電區域表面,例如M0S電晶體的源極/ 汲極或其他下層之金屬導線的表面。然後於介電層16以及 各插塞洞底部之導電區域的表面沈積一黏著層(glue U y e r )以及一鎢金屬層並填滿各插塞洞。接著再進行一回 触刻(e t c h b a c k )製程,#刻該鶴金屬層至約略與介電層 i 6表面切齊,以形成接觸插塞1 8。4 6 335 4 V. Description of the invention (2) A layer of titanium nitride is formed on the surface of the metal layer 12 as a barrier layer 14 with a thickness of about 500 to 1500 angstroms. Generally speaking, the barrier layer 14 has two different manufacturing methods. One is to perform a Nitridation reaction on the titanium metal layer 12 to form a nitrided drink layer on the surface of the metal layer 12; the other is By reactive sputtering, a titaniumized layer is directly deposited on the surface of the titanium metal layer 12. After the structure of the metal wire layer is completed, a yellow light and etching process is then used to define the pattern of the metal wire. A dielectric layer is then formed between the MOS transistor and each metal wire layer to isolate and protect the components on the semiconductor wafer. In order for these MOS transistor elements to be electrically connected to each metal wire layer smoothly to form a complete electronic device, a contact plug must be formed in these dielectric layers during the multiple metallization process. As a wire electrically connected between each MOS transistor and the metal wire layer. The conventional method for making contact plugs on the surface of a semiconductor wafer is to first form a plurality of plug holes on a dielectric layer 16 and reach the surface of a conductive region that is to be electrically connected to the outside, such as a MOS transistor. The surface of the source / drain or other underlying metal wires. Then deposit a glue layer (glue U y r) and a tungsten metal layer on the surface of the dielectric layer 16 and the conductive area at the bottom of each plug hole and fill each plug hole. Then, a touch-etching (e t c h b a c k) process is performed again, and the crane metal layer is etched to be approximately aligned with the surface of the dielectric layer i 6 to form a contact plug 18.
第5頁 46335 4 五 '發明說明(3) 然而沉積鎢金屬層辟,高於4 0 0 °C的濺鍍溫度將會影 響先前利用習知方法所完成之金屬導線層結構,因為在製 作接觸插塞18製程的高溫影響下,鈦金屬層12非常容易與 鋁金屬1 0反應,形成一高電阻的鋁鈦化合物,進而使得金 屬導線的電阻值上升,嚴重影響電性表現。 發明概述 因此本發明之主要目的在提供一種降低一含鋁之金屬 導線阻值的方法,以解決上述習知技術之問題。 本發明方法是先於該含is之金屬導線表面生成一氧化 鋁層,然後於該氧化鋁層上形成一鈦金屬層以及一阻障 層,最後再於該阻障層上形成一鎢金屬插塞。其中該氧化 鋁層係用來避免製作該鎢金屬插塞時的高溫使該鈦金屬層 與該金屬導線發生反應而影響該含鋁金屬導線的阻值。 本發明之方法是於金屬導線表面生成一氧化鋁薄層, 故能有效利用防止鈦金屬層與鋁金屬於製作鎢金屬插塞的 高溫下反應,造成金屬導線阻值升高。 i 發明之詳細說明Page 5 46335 4 Five 'invention description (3) However, the deposition of tungsten metal layer, sputtering temperature higher than 400 ° C will affect the structure of the metal wire layer previously completed by conventional methods, because Under the influence of the high temperature of the plug 18 process, the titanium metal layer 12 easily reacts with the aluminum metal 10 to form a high-resistance aluminum-titanium compound, which further increases the resistance value of the metal wire and severely affects the electrical performance. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method for reducing the resistance value of an aluminum-containing metal wire so as to solve the problems of the conventional techniques. The method of the present invention first forms an aluminum oxide layer on the surface of the metal wire containing is, then forms a titanium metal layer and a barrier layer on the aluminum oxide layer, and finally forms a tungsten metal plug on the barrier layer. Stuffed. The aluminum oxide layer is used to prevent the high temperature during the manufacture of the tungsten metal plug from causing the titanium metal layer to react with the metal wire to affect the resistance value of the aluminum-containing metal wire. The method of the present invention generates a thin layer of aluminum oxide on the surface of the metal wire, so it can effectively utilize to prevent the titanium metal layer and aluminum metal from reacting at a high temperature for making a tungsten metal plug, causing the resistance of the metal wire to increase. i Detailed description of the invention
第6頁 五、發明說明(4) 請參考圖二,圖二為本發明製作一低阻值之金屬導線 的方法示意圖,該金屬導線可位於半導體晶片上的各金屬 氧化半導體元件之間、上方或各金屬内連線層之中。如圖 二所示,本發明是先利用一低壓減鍵(low pressure sputtering)製程來於半導體晶片之基底表面(未顯示)形 成一由鋁或鋁銅合金構成之金屬導線2 0,然後將含鋁之金 屬導線20表面暴露於一含氧之環境中,或是利用一含氧之 電漿與該含鋁之金屬導線20表面反應形成一氧化鋁層22。 其中氧化鋁層22的厚度約在50埃(angstrom)以内。隨後在 氧化鋁層2 2上形成一還原能力較鋁大之鈦金屬層2 4,最後 在鈦金屬層24上形成一由氮化鈦構成之阻障層26,以構成 一金屬導線層。 在完成金屬導線層之後,接著再於各金屬導線層周圍 形成一介電層,用來隔離並保護半導體晶片上的元件。為 了使這些金屬導線層能與各個M0S電晶體元件或其他的金 屬導線層順利地電連接以形成一個完整的電子裝置,因此 必須於這些介電層内形成接觸插塞,作為各Μ 0 S電晶體或 其他元件與金屬導線層之間電連接的導線。如圖二所示, 於該金屬導線層之氮化鈦層26上形成一介電層28,然後在 介電層2 8内形成一插塞洞,最後於各插塞洞内填入一鎢金 屬,形成一接觸插塞30。在填入鎢金屬的製程中,需要約 4 0 0 °C以上的高溫。5. Explanation of the invention on page 6 (4) Please refer to FIG. 2. FIG. 2 is a schematic diagram of a method for making a low-resistance metal wire according to the present invention. The metal wire can be located between and above each metal-oxide semiconductor element on a semiconductor wafer. Or in each metal interconnect layer. As shown in FIG. 2, the present invention first uses a low pressure sputtering process to form a metal wire 20 made of aluminum or an aluminum-copper alloy on a substrate surface (not shown) of a semiconductor wafer. The surface of the aluminum metal wire 20 is exposed to an oxygen-containing environment, or an oxygen-containing plasma is used to react with the surface of the aluminum-containing metal wire 20 to form an aluminum oxide layer 22. The thickness of the aluminum oxide layer 22 is within about 50 angstroms. Subsequently, a titanium metal layer 24 having a greater reduction ability than aluminum is formed on the alumina layer 22, and finally, a barrier layer 26 made of titanium nitride is formed on the titanium metal layer 24 to form a metal wire layer. After the metal wiring layer is completed, a dielectric layer is formed around each metal wiring layer to isolate and protect the components on the semiconductor wafer. In order for these metal wire layers to be smoothly and electrically connected to each MOS transistor element or other metal wire layers to form a complete electronic device, a contact plug must be formed in these dielectric layers as each M 0 S electrical A wire that is electrically connected between a crystal or other element and a metal wire layer. As shown in FIG. 2, a dielectric layer 28 is formed on the titanium nitride layer 26 of the metal wire layer, and then a plug hole is formed in the dielectric layer 28, and finally a tungsten is filled in each plug hole. Metal to form a contact plug 30. In the process of filling tungsten metal, a high temperature above about 400 ° C is required.
第7頁 4 633 5 4 五、發明說明(5) 由於利用本發明方法所製作的金屬導線層,在鋁銅合 金與鈦金屬層之間形成有一氧化鋁層,因此在製作鎢金屬 插塞時,可以避免鋁金屬與鈦金屬直接接觸,而在高溫下 反應形成鋁鈦化合物,造成金屬導線的電阻值升高。此 外,亦由於氧化鋁層2 2的厚度約僅為5 0埃,所以很容易被 還原能力較鋁大之鈦金屬層24反應消耗,幾乎不殘留於半 導體晶片之中。 相較於習知製作金屬導線的方法,本發明之方法能有 效避免鋁銅合金與鈦金屬反應形成化合物而增加金屬導線 之阻值,影響最後產品晶片的電性表現。 以上所述僅本發明之較佳實施例,凡依本發明申請專 利範圍所做之均等變化與修飾,皆應屬本發明專利之涵蓋 範圍。Page 7 4 633 5 4 V. Description of the invention (5) Because the metal wire layer produced by the method of the present invention has an aluminum oxide layer formed between the aluminum-copper alloy and the titanium metal layer, when manufacturing a tungsten metal plug It can avoid direct contact between aluminum metal and titanium metal, and react at high temperatures to form aluminum-titanium compounds, which causes the resistance value of metal wires to increase. In addition, since the thickness of the alumina layer 22 is only about 50 angstroms, it is easily consumed by the titanium metal layer 24 having a reduction ability greater than that of aluminum, and hardly remains in the semiconductor wafer. Compared with the conventional method for making metal wires, the method of the present invention can effectively avoid the reaction between aluminum-copper alloy and titanium metal to form compounds and increase the resistance value of the metal wires, affecting the electrical performance of the final product wafer. The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.
第8頁 463354 圖式簡單說明 圖示之簡單說明 圖一為習知製作一金屬導線層以及複數個接觸插塞的 結構示意圖。 圖二為本發明上製作一低阻值之金屬導線層以及複數 個接觸插塞的結構示意圖。 圖示之符號說明 10 鋁-銅金屬層 12 鈦金屬層 14 阻障層(氮化欽層) 16 介電層 18 接觸插塞 20 金屬導線 22 氧化鋁層 24 鈦金屬層 26 阻障層(氮化鈦層) 28 介電層 30 接觸插塞Page 8 463354 Brief description of the diagrams Brief description of the diagrams Figure 1 is a structure diagram of conventionally making a metal wire layer and a plurality of contact plugs. FIG. 2 is a schematic structural diagram of a low-resistance metal wire layer and a plurality of contact plugs according to the present invention. Explanation of symbols in the figure 10 Aluminum-copper metal layer 12 Titanium metal layer 14 Barrier layer (nitride layer) 16 Dielectric layer 18 Contact plug 20 Metal wire 22 Alumina layer 24 Titanium metal layer 26 Barrier layer (nitrogen Titanium layer) 28 Dielectric layer 30 Contact plug
第9頁Page 9
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