TW463314B - Forming method of borderless contact to avoid the loss of field oxide layer - Google Patents

Abstract

The present invention provides a forming method of borderless contact to avoid the loss of field oxide layer, which comprises the following steps: first, providing a semiconductor substrate which has a first gate and a second gate located on an active region, and which has an field oxide region; next, forming a nitride layer on the first gate, the second gate, field oxide region and semiconductor substrate; etching back the nitride layer to form a first spacer and a second spacer located on the sidewall of the first gate, the second gate, respectively, and retaining some nitride layer on part of the field oxide region; forming a silicide layer on the first gate and the second gate and the exposed semiconductor substrate; forming an inter-dielectric layer covering the filed oxide region, the first gate, the second gate, and the semiconductor substrate; and forming a contact on part of the silicide layer.

Description

463314 V. Description of the invention α) 5 -1 Field of the invention: The present invention relates to a method for forming a contact window, especially a method for forming a borderless contact window which avoids the loss of a field oxide layer. 5-2 Background of the Invention: A general integrated circuit is a type of electronic product that is reduced to a variety of electronic components and circuits required for a specific circuit in a size of only a few square centimeters or less. Because integrated circuits are widely used in various related industries, their demand has increased rapidly and in large quantities, especially in the information industry related to computer hardware. In addition, with the trend of light, thin, short, and fast electronics, information, and communication products, large integrated circuits (L S I), very large integrated circuits (VLSI), and very large integrated circuits (ULSI) have also been developed. In the ultra-large-scale integrated circuit (U LSI) process, the density of electronic components often reaches tens of millions to billions or more. This is the result of the minimum line width used being smaller and smaller. Undoubtedly, even in the next century, integrated circuits will still play a key role, and their demand will continue to increase. In terms of conventional techniques, please refer to the first diagrams A to F. The following description will explain a conventional method of forming a contact window structure.

463314 V. Description of the invention (2) As shown in the first A diagram, first, in the manufacturing process of the conventional contact window structure, a semiconductor substrate 10 is provided. 10 on the semiconductor substrate has a first gate electrode 12A on the surface of the semiconductor substrate 10, a field oxide layer 11 is located in the semiconductor substrate 10 and a surface of the field oxide layer 11 is exposed, a second The gate electrode 12B is located on the surface of the semiconductor substrate 10 and the surface of the exposed field oxide layer 11; a nitride layer 13 is located on the surface of the semiconductor substrate 10, and the semiconductor substrate 10 has a bonding area 1 5. Next, as shown in FIG. 1B, a portion of the nitride layer 23 is etched by dry etching (or wet etching) to form one of the first gate electrode 12A, the first gap wall 13A, and the second gate electrode 12B. The second partition wall 1 3 B. After the above-mentioned etching step is performed, the result formed is the first C picture. If the silicon nitride cover layer is under the inner dielectric oxide layer, when the borderless contact window is etched, if the process conditions are not carefully controlled, it cannot function as a stop layer, as marked 1 in Figure C. 0 0. Then, the field oxide layer region 11 will be dug deep, and the problem of contact short circuit will occur. Therefore, it is necessary to strengthen and improve the above-mentioned conventional technologies. As shown in the first figure D, a metal oxide layer 16 is covered on the top surface of the first gate electrode 12 A and the second gate electrode 12 B and the surface of the exposed semiconductor substrate, but the field oxide layer 2 is not covered. 1 surface to form a metal lithoxide region 16. As shown in the first E diagram, a layer of gasification stone layer 17 and metal sand layer 16 are covered.

Page 5 463314 V. Description of the invention (3) The top surface and the field oxide layer 21 are formed on the surface to form a metal sanding area 16 °. As shown in the first F diagram, an internal dielectric layer is formed evenly and uniformly. 8 Covering the surface of the nitride layer 17. Continuing as in the first F diagram, a contact window 19 is formed on the metal silicide region 16 of the semiconductor substrate 10, and the contact window 19 is adjacent to the field oxide layer region 11 and the first gap wall 13A. . Finally, as in the first F picture, a metal is filled in the contact window 19 to form a borderless contact window. At this time, in the conventional art, since the field oxide layer has no protection, the loss of the field oxide layer cannot be avoided, so that the filling of the town metal will cause a huge problem of junction leakage and other defects. Know-how can also cause a decrease in metal oxides (Poor

Salicide Formation) d. None of the above disadvantages are pleasing to the design and production of sub-micron components. | \ For the process of 0.1 8 or smaller, the contact window process is the key technology to reduce the design rule | inch (d e s i g n r u 1 e). However, it is quite difficult to control the process space, and especially in the process of forming the interlayer window. Therefore, the good lithography resolution (prevents misalignment) and the high-layer window etching selection ratio are the key factors for the contact window process. 4 6 3314 V. Description of the invention (4) 5-3 Purpose and summary of the invention: In view of the many shortcomings of the traditional process in the above background of the invention, the present invention provides a method for forming a contact window, which can obtain a larger Process space. The object of the present invention is to provide a process with contacts, which can be completely protected by a silicon nitride layer. The purpose of the present invention is to provide a manufacturing process which avoids the loss of the field oxide layer, so that the filling of crane metal does not cause the problem of joint leakage (J u n c t i ◦ η Leak) and the problem of no other defects. It also improves the problem of reduced metal silicide. In a preferred embodiment of the present invention, a method for forming a borderless contact window that avoids the loss of a field oxide layer is provided. The method includes the following steps: First, a semiconductor substrate is provided. And a second gate is in an active area and has a field oxidation area. A nitride layer is formed on the first gate, the second gate, the field oxide region, and the semiconductor substrate. Thus, a photoresist layer is formed to cover a part of the field oxidation region.

4 633 14 V. Description of the invention (5) Etching the nitride layer back to form a first gap wall and a second gap wall are located on one side wall of the first gate and the second gate, respectively, and the remaining nitride layer Part of the field oxidation area. Remove the photoresist layer. A metal silicide layer is formed on the first gate and the second gate and the exposed semiconductor substrate. An internal dielectric layer is formed to cover the field oxidation region, the first gate and the second gate, and the semiconductor substrate. Finally, a contact window is formed on a part of the metal silicide layer. In order to make the above description and other objects, features and advantages of the present invention more comprehensible, the preferred embodiments are listed below and described in detail with the accompanying drawings. 5-4 Detailed Description of the Invention The following is a description of the invention. The description of the present invention will first be made with reference to an exemplary structure. Some variations and advantages of the invention will be described later. The preferred method of manufacture will be discussed later. _ Furthermore, although the present invention is taught in several embodiments, these descriptions

Page 8 4 633 14 V. Description of the invention (6) Does not limit the scope or application of the invention. Also, although these examples use silicon oxide, it should be clear that the silicon oxide portion may be replaced. Therefore, the semiconductor element of the present invention does not limit the description of the structure. These elements include proof of the utility and applicability of the present invention and the preferred embodiments presented. And even though the present invention is described by way of example and a preferred embodiment, the present invention is not limited to the illustrated embodiment. In addition, all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention are included in the scope of patent application of the present invention. The scope of the invention should be construed in its broadest definition, so as to encompass all such modifications and similar structures. The method for forming a borderless contact window, which avoids field oxide layer loss (Loss) according to the present invention, includes the following steps: Referring to FIG. 2A, first, a semiconductor substrate 20 formed of a silicon wafer is provided. The substrate 20 has a first gate electrode 2 2 formed of polycrystalline silicon on the surface of the semiconductor substrate 20, and a field oxide layer 21 formed of silicon oxide is located in the semiconductor substrate 20 and the field oxide layer is exposed. On the surface of 21, a second gate electrode 22B formed of polycrystalline silicon is located on the surface of the semiconductor substrate 20 and the surface of the exposed field oxide layer 21, and a siliconized layer of silicon nitride 2 3 is located on the semiconductor bottom. On the material surface 20, and the semiconductor substrate 20 has a junction area (Junct i on) of 25 °. Continue, referring to the second: Figure B, forming a photoresist layer 6 0 on the nitride layer 2 3 by the traditional lithography process. On the surface and aligned above the field oxide layer 21. So available

4 633 1 4 V. Description of the invention (7) In the next step, the required protective layer is generated. Referring to the second figure C, the nitride layer 2 3 that is not covered by the photoresist layer 60 is etched by the conventional dry etching method through the photoresist layer 60 to form a protective field oxidation region 2 on the field oxide layer. 3 C, and a first partition wall 2 3 A of the first gate electrode 2 2 A and a second partition wall 2 3 B of the second gate electrode 2 2 B are formed. Obviously, the protective field oxide region 2 3 C can be covered and protected. The role of the protective field oxide layer 21 1 ^ Referring to the second figure D, the preferred embodiment of the present invention uses a conventional plasma dry etching method to remove light Resist layer 6 0. Referring to FIG. 2E, a metal chemical oxide layer 26 is formed and covered by a conventional chemical vapor deposition (CVD) method, such as Shi Xihua Di and Shi Xi Cobalt on the first gate 2 A and the second gate. The top surface of the electrode 2 2 B and the exposed surface of the semiconductor substrate 20 form a metal oxide region 26. Referring to the second F diagram, an inner dielectric layer 27 is formed flat and uniform, such as boron | phosphosilicate glass (BPSG) covering the surface of the protective field oxidation region 23C, and | covering the first inter-electrode 22A and the second The surface of the gate electrode 22B is on the surface of the semiconductor substrate 20. Compared with the conventional technique, there is no need to add nitrogen 丨 fossil evening stop layer.丨 Still referring to the second F diagram, a contact window 28 is formed on the metal silicide region 26 of the semiconductor substrate 20, and the formed contact window 28 is adjacent to the protection

Page 10 4 633 1 4 V. Description of the invention ¢ 8) Between the field oxidation zone 2 3 C and the first gate electrode 2 2 A. Finally, referring to the second F diagram, a metal, such as tungsten, is filled into the contact window 28 by a conventional chemical vapor deposition method. At this time, the field oxide layer is avoided due to the protection of the protective field oxide region 2 3 C. The loss of 21 makes the filling of tungsten metal not to cause the problem of missing joints (J uncti ο n Leak). Therefore, a borderless contact window can be formed without reducing the oxide layer.

Contact) 0 I

I Therefore, the present invention provides a method for forming a contact window, which has the advantages of: | It has a contact process, and can be protected by a complete silicon nitride layer, and avoids the loss of the field oxide layer, so that the filling of the crane metal will not Problems that cause junction leaks and problems that do not cause other defects. It also improves the reduction of metal silicide. Incidentally, with regard to the method for forming the oxide layer, the growth of the silicon dioxide layer is an indispensable step in the integrated circuit manufacturing process. According to whether the Shixi substrate is consumed or not, the method for forming an oxide insulating layer includes the growth of a thermal oxide layer and the non-consumable oxide layer deposition of the Shixi substrate. In the former, a hard substrate is placed in an oxygen-containing atmosphere and oxidized on the broken surface to form a layer of silicon dioxide. Since this layer of silicon dioxide consumes part of the silicon surface layer, we classify it as consumable oxidative growth. As for the latter, it is through reaction gas! Bulk deposition method, depositing an insulating layer on the surface of a silicon substrate. Because the formation of the absolute

463314 V. Description of the invention (9) The marginal layer does not consume the silicon surface layer, and we classify it as non-consumable oxide layer deposition. Therefore, the following two methods for forming the above-mentioned oxide layers are described separately. Because the silicon surface layer has a high affinity for oxygen molecules (affinity). When the surface of Shi Xi wafer is exposed to an oxygen-containing atmosphere, an oxide layer is easily formed. The silicon wafer is placed in a furnace tube, and then raised to a proper temperature, and an oxygen-containing gas such as oxygen or water vapor is passed into the silicon wafer to grow a layer of dioxide with good adhesion to the silicon material and good insulation. Silicon. Therefore, the surface of a silicon wafer is usually covered by a layer of SiO. In this layer, S i 0 2 formed naturally by oxygen in the air and water molecules is called " native ο X ide silicon dioxide (S i 0 2), where silicon atoms and oxygen atoms borrow a common price. Covalent bonds are formed electronically. During the oxidation process, the Si-Si 0 妁 interface moves from the silicon surface to the inside. Basically, the thermal oxygen oxidation of silicon is formed by three steps connected in series. They are: 1. The flow rate (F 1 u X) of the oxygen molecules in the gas phase to the surface of the intrinsic oxide layer. 2. The oxygen molecules on the surface of the intrinsic oxide layer pass through the Si through the diffusion effect. 0 2 and reach the interface between Si and SiO. 3. Oxygen molecules and silicon are reacted with SiO to generate Si-Si02 interface.

Page 12 4 633 彳 4 V. Description of the invention (10) should be 0 When the oxide layer has a considerable thickness, 'the diffusion constant of oxygen at si is relatively low' because of the insufficient oxygen diffusion capacity, the oxygen at the Si-SiO interface The molecular concentration will approach zero, and the oxygen content on the surface of S i 0 will therefore be comparable to the oxygen concentration in the gas phase. At this time, the rate of oxidation will be dominated by the rate of expansion of the oxygen molecules in the dioxide. Also called diffusion control case. On the contrary, when the thickness of the oxide layer is very thin, when the number of oxygen molecules in the Si 〇 fishing diffusion system is sufficiently large relative to Si 0, the oxidation rate at this time will be determined by the oxygen molecular wave length and the oxidation reaction in the atmosphere. Dominated by constants, also known as reaction control case ° j ί In very large integrated circuit (ULS I) technology, there are many methods for depositing oxide layers. Generally speaking, these methods can be classified into two different reaction mechanisms: chemical Chemical vapor deposition (CVD) and physical vapor deposition (PVD). These two technologies will be described later. Chemical Vapor Deposition (CVD): Chemical vapor deposition is defined as the opposite phase of the gas | The reactant 'forms a chemical reaction' to form a non-volatile solid j film on the substrate surface. This is the technology most commonly used in semiconductor processes. Usually chemical gas! The phase deposition method must include the following five steps: 1. The reactants are transferred to the substrate surface;

Page 13 4633 1 4 V. Description of the invention (11) 2. Adsorption or chemisorption onto the substrate surface; | 3. Catalyze a chemical reaction between the heterogeneous materials via the substrate surface; 4. The gas phase product detaches from the substrate surface; and 5. The product is transferred away from the substrate surface. In this continuous chemical vapor deposition step, in practical applications, the solid material generated after the chemical reaction not only occurs on the surface of the substrate (or very close to it) (the so-called heterogeneous reaction), but also reacts in the gas phase (ie So-called homogeneous reactions). Regarding the inter-heterogeneous reaction, because such a reaction can only be selected on a heated substrate, and can produce a good-quality film. In contrast, the homogeneous reaction will form gas-phase particles of the substance to be deposited, resulting in poor adhesion and a low density film with many defects. In addition, such a reaction will consume a lot of reactants and cause a reduction in the deposition rate. Therefore, in the application of chemical vapor deposition, an important factor is that heterogeneous reactions are far easier to occur than homogeneous reactions. ! The most commonly used chemical vapor deposition methods are Atmospheric-pressure CVD (APCVD), Low-pressure CVD (LPCVD), and Electric II-assisted chemical vapor deposition ( Plasma-enhanced CVD (PECVD). The advantages, disadvantages, and applications of these three chemical vapor deposition methods are shown in Table 8-2 (1 0). From the table j, it can be seen that the low pressure chemical vapor deposition method has very uniform step coverage, good composition and structure control, high deposition rate and output, and low process costs. Furthermore, low pressure chemical vapor deposition is not required.

Page 14 4 6 33 1 4 V. Description of the invention (12) The carrier gas greatly reduces the source of particulate pollution. Therefore, the low-pressure chemical vapor deposition method is widely used in the high-value-added semiconductor industry for thin film deposition. During the epitaxial growth of silicon, the purpose of using low voltage is to reduce the effect of auto-doping (impurities from the substrate itself), and this is the most important problem of atmospheric pressure chemical vapor phase epitaxial growth in future components When the size is getting smaller, the process temperature must be lowered, and the most serious problem of low pressure chemical vapor deposition is that its process temperature is slightly higher. Plasma-assisted chemical vapor deposition is a suitable method. Solving this problem will be discussed later. ‘!

I i

I About physical vapor deposition (PVD), physical vapor deposition and chemical | vapor deposition have different deposition mechanisms. The deposition rate of chemical vapor deposition | is proportional to the deposition temperature, but the physical vapor phase The deposition method happens to be phase 1 instead, that is, the higher the deposition temperature, the lower the deposition rate. Physical vapor deposition technology is usually used in the following three methods, which are described in the following: 1. Evaporation Technology: This is one of the earliest | phase coating methods. First, the material to be plated needs to be gasified. This is usually done with a thermal resistance wire, Electron-gun (E-gun) or laser, etc. in a vacuum cavity, and then these vaporized evaporation materials are transferred to the substrate to be coated, and then The process of coagulation is deposited on the substrate.

Page 15 4 633 1 4 V. Description of the invention (13) 2. Molecular beam epitaxy (MBE): This is a method for growing single crystal thin films through very fine trimming under extremely high vacuum. The most commonly applied and extensively studied is the growth of three or five semiconductors. • Layers or layers of worm crystal thin film 5 or growth of broken worm crystals on wonderful substrates. The evaporated material is Transfer to substrate surface (due to extremely high vacuum environment). Those low vapor pressure dopants and silicon can ensure that the desired film is condensed and deposited on the substrate surface at low temperature. t 3. Sputtering: This process involves impinging ions and momentum conversion of the atoms on the surface of the electrode. The material of the bond to be vaporized is ejected from the electrode surface and then deposited on the surface of the substrate. Unlike thermal evaporation technology, the sputtering process is very easy to control and suitable for any material, such as metals, insulators, i semiconductors, alloys, etc. The design and operation of chemical vapor deposition reactors will vary according to different requirements, so these reactors can be classified in different ways. One classification is based on the way the wafer is heated, and the other is based on the pressure in the reaction chamber (normal pressure or low pressure). The method of heating the wafer can be divided into the following four categories: i

I 1. Thermal resistance wire heating method; | 2. Radio frequency (RF) induction heating method;! 3. Plasma heating method 4. Light energy heating method

Page 16 4 633 1 4 V. Description of the invention (14)

The energy added by I may be converted into the reaction gas itself or on the substrate. When using the heating resistance wire coil heating method surrounding the reaction chamber, in addition to the wafer itself, the furnace wall of the reaction chamber will also be heated. Therefore, this design is called " hot-wall reactors " (hot-wall reactors) . In this system, the thin film of the chain j will not only be formed on the substrate, but also on the furnace wall. This means that in such a design, the furnace tube must be cleaned frequently to avoid contamination by dust particles. |

I On the other hand, the introduction of a heat source by radio frequency induction or the installation of infrared and ultraviolet heating lamps in the reactor will only increase the wafer and the carrier of the wafer! Heat without heating the furnace wall of the reaction chamber, such a design is called π cold-wall reactors (cold-wall reactors), however, in some cold-wall reactor systems, it still occurs The furnace wall is heated, so it must be reduced or avoided by cooling the furnace wall (through cooling water)

I react or deposit a film on the furnace wall. The geometry of the reactor tube is strictly limited by the reaction pressure and the heat supply mode, and this is an important factor affecting the throughput. Because the operation of the atmospheric reactor is in the "| mass transfer limit" (mass -1 rans ρ 〇 ΐ-Π mit, which will be discussed in the next section, the parameters of the Shen | product), the cavity design must be Make each piece of wafer have equal flow on the surface. So the wafers will never be placed vertically and very close to each other, but rather placed horizontally, but this design has a very serious The problem is that it is easy to be contaminated by falling dust particles = > The design of the furnace tube of the low pressure chemical vapor deposition method will not be limited by the reaction in the region of the π material transport limit " so its geometry j

Page 17 4 633 1 4 V. Description of the invention (15) It can be designed so that the number of wafers in each batch reaches a vertical position, and a quartz wafer is worn between the wafers. However, because of the low-pressure chemical vapor deposition (surface-reaction-1imited), its reactor design must have a good one meter to centimeters. However, there are only two pieces of crystals that are supercrystalline, so the value of the cocoa can be separated from the next one. Lamellar Λν AH Lamellar Inverse ^, > Discussing that the once-in-time atmospheric pressure chemical vapor deposition (APCVD) reactor, which is the limiting temperature region of the T-temperature operation product, is the first method to be microelectrically charged. The equipment used in the sub-industry. The chemical vapor deposition reactor at atmospheric pressure is easy to design and has a fast reaction rate, but it is sensitive to gas-phase reactions and it The thin film produced by the reaction has poor step coverage, and because the atmospheric pressure reactor is operated in the " substance transfer restriction M region, the reaction stream must be uniformly transmitted to each of all substrates. In part, the advantages of this process are deposited; the film is very uniform, but its disadvantage is that the by-products contain hydrogenated hydrogen, which will damage the grown thin film, such as polycrystalline silicon. |

Plasma-assisted chemical vapor deposition (PECVD)

The hot discharge generated by I, and the energy is converted to the reaction gas, so the substrate temperature of I is much lower than that of atmospheric pressure or low pressure chemical vapor deposition. Low temperature deposition is the main advantage of plasma-guided chemical vapor deposition. . In fact, plasma-assisted chemical vapor deposition provides a method for coating films on substrates without the problems of thermal stability during coating. In addition, the plasma-assisted chemical vapor deposition method can increase the rate of coating, which is higher than using only thermal reaction.

Page 18 4 ό 33 t 4 V. Description of the invention (16) is faster and can provide films with unique composition and characteristics, but production capacity, productivity limitations (especially large size wafers), and loose adhesion Contamination by dust is still the biggest problem. In the first place, an energy body such as silicon is produced by the region and the ions attached to this film are also attached to the weight of the countertron and the rate is changed from owning. In addition, we introduce radio frequency to generate free electricity. When charged with alkane (SiH4 These by-products are easy to excite when there are very good by-products of the substrate and the reaction after the reaction of the new array package. The by-products with low temperature are noted. The plasma-assisted chemical vapor deposition method will be discussed. (RF-fie 1 d) enters the low-pressure gas, discharges electrons, and forms a plasma. The electrons, ie, the electrons that get energy from the electric field, collide with the gas molecules. The reacting gas, laugh gas (N 20), oxygen, nitrogen, etc. will decompose, and the reactants filled with energy will attract atomic groups to each other on the substrate surface. After being absorbed, there are high adhesion coefficients and migration on the substrate surface. These two factors make the plating uniform. These excited primary electrons attracted to the substrate surface collide, rearrange, and form new bonds with other attracted atoms, and a thin film is formed. Originally included the diffusion of the adsorbed atoms to a stable position, and the by-products (waste) detached from the surface of the substrate, and the degree of this detachment determines that the higher the temperature of the substrate, the borrowed film (these by-products will Causing defects). It is necessary to avoid homogeneous gas-phase nucleation > because this will cause pollution of fine dust. Compared with the RF base forging system, the biggest difference between the plasma-assisted chemical vapor deposition system is the design of the reaction cavity and the appearance of the electrode.

Page 19 463314 V. Description of the invention (17) In the assisted chemical vapor deposition system, the potential difference between the ground and high voltage electrodes must be almost equal to the plasma. In the furnace wall of the parallel plate type reactor, it is necessary to use stainless steel coated with quartz, ceramic or alumina so that they have a floating voltage (f 1 〇ating ρ 〇tentia 1) with respect to the plasma, for the purpose of doing so, The purpose is to reduce the impact and sputtering of the reactor furnace wall, and to reduce the pollution of fine dust during the coating process. The temperature of a process is uniform, so it does not maintain the solid rate. Therefore, the surface reaction between wafers and chemical gases is a deposition rate. This is very far from the limit of the distance rate of phase deposition. When it is a very important rate in the table, it needs to be anywhere. In this important, because of the design of the reactant system, etc., The parameters can be reflected in a small mode, one can't be their flow in either case. For deposition, it is necessary to maintain a fixed deposition rate throughout the reactor. The surface temperature on the wafer is maintained at a constant deposition rate. The concentration of the reactants on the wafer does not limit the deposition. So it must be designed so that the wafer can swing vertically. Because this system is operating, the deposition must have a very high degree of surface rate. In each reactor at low pressure, the reactor pressure is about 1 Torr. Under this pressure, the diffusion coefficient of the reactant gas is about one thousand times under normal pressure, and this is partly due to the adjustment of the square root of the pressure reduction, so the net effect is that the rate of the reactant transport to the substrate surface increases by more than ten Times, so the rate limiting step is a surface reaction. Usually the surface reaction rate varies with

Page 20 4 6 331 4 V. Description of the invention (18) The surface reactant concentration increases and the gas phase concentration distribution increases unevenly. This uneven gas phase concentration is caused by the emptying of the reactants somewhere. Take an example to illustrate this effect. When the wafer is placed near the gas outlet of the reactants, it is exposed to a lower concentration of reactants. It is much lower than the inlet end, which causes the thickness of the front and rear ends of the flower furnace tube to be uneven. Therefore, in order to uniformly deposit the thin film, the deposition temperature must be adjusted correctly at the front and back ends of the reaction furnace tube. . When the deposition process falls within the limits of material transport, precise control of the process temperature is not necessary. The relationship between the deposition rate limit and the temperature | is not so relevant. On the other hand, in controlling the reaction It is most important to have equal gas flow at the set points, because the surface velocity of the reactants reaching the wafer is directly proportional to the concentration gradient in the reaction chamber, so it is necessary to ensure that there is the same film thickness at each position on the same sheet. Design

I It is necessary to make each point of all the wafers have equal flow of reactants. The atmospheric pressure reactor for depositing silicon dioxide has an operating temperature of about 400 ° C, which falls in the area of material | transmission restrictions, so the most Widely used reactor design is horizontal 丨

I The way of placing the wafers to provide a uniform gas supply ^ | ί The impact parameters of the plasma-assisted chemical vapor deposition system include reaction 丨

I should be based on gas flow, substrate heating temperature, radio frequency energy, etc. Two examples are given below. Plasma-assisted chemical vapor deposition is used to deposit silicon nitride. Effect of parameters on silicon dioxide. In fact, the proton radicals or atomic groups produced by plasma discharge are highly active and often cause thin deposits |

Page 463314

V. Description of the invention (19) I Whether the membrane has stoichiometric problems. Because these reactions are very variable and complex, and by-products or incident reactants are often incorporated into the deposited film, especially hydrogen, nitrogen, and oxygen atoms. Excessive merging of these atoms will cause the critical voltage shift of gold-fluorine semi-electric crystals. The refractive index of silicon nitride deposited by plasma-assisted chemical vapor deposition has a very wide range, from 1. 8 to 2.6 are possible. The chlorosis and collapse electric field of this film vary greatly with different deposition conditions j. i «As far as the above-mentioned preferred embodiments are concerned, the present invention is a method for forming a borderless contact window to avoid the loss of the field oxide layer. In brief, it includes the following steps: 1 ti First, a semiconductor substrate is provided. Material, the semiconductor substrate has a first gate i pole position and a second intermediate pole in an active area, and has a field oxidation area.丨 i j further forms a nitride layer on the first gate, the second gate, the field oxide region, and the semiconductor substrate. Therefore, a photoresist layer is formed to cover a part of the field oxidation i region. |! Etching the nitride layer back to form a first spacer wall and a second spacer wall on one of the first gate and the second gate, respectively, and the remaining nitride layer is on the partial field oxidation region. ί

Page 22 463314 V. Description of the invention (20) Gate and No. removing photoresist layer. A metal silicide layer is formed on the first gate electrode and the exposed semiconductor substrate. An internal dielectric layer is formed to cover the field oxidation region, the first gate and the second gate, and the semiconductor substrate. Finally, a contact window is formed on a part of the metal oxide layer. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

Page 23 4633 1 4 Schematic illustrations Figures A through F are schematic diagrams of the traditional process for forming a contact window; and Figures A through F are drawings of an embodiment of forming a borderless contact window according to the present invention. Representative symbols of the main part of the present invention: I 0: semiconductor substrate II: field oxide layer 1 2 A: first gate electrode 1 2 B: second gate electrode 13: nitride layer 1 3 A: gap wall 1 3 B : Spacer wall 15: Junction area 16: Metal oxide 17: Nitride layer 1 8: Internal dielectric layer 1 9: Contact window 20: Semiconductor substrate 2i: Field oxide layer 2 2 A: First gate Pole 2 2 B: Second inter electrode 2 3: Nitrided layer 463314 Brief description of the drawing 2 3 A: Spacer wall 2 3 B: Spacer wall 2 3C: Protective field oxide layer 2 5: Junction area 2 6: Metal stone Compound 27: Inner dielectric layer 2 8: Contact window 6 0: Photoresist

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Claims (1)

463314 VI. Scope of patent application | 1. A method for forming a borderless contact window that avoids field oxidation loss, at least i includes: j Provide a semiconductor substrate having a first gate electrode and a first gate electrode The two gates are in an active region and have a field oxidation region; | forming a nitride layer on the first gate, the second gate, the field oxidation region, and the semiconductor substrate, and covering it with a mask Part of the oxidized area of the field, and back to the nitride layer to form a first spacer and a second spacer are located on one side wall of the first gate and the second gate, respectively, and the nitride layer remains On a part of the field oxidation region i; 丨 forming a metal breakdown layer on the first gate and the second gate and the semiconductor substrate exposed by I; 丨 forming an internal dielectric layer covering the field On the oxidized region, on the first gate electrode and on the second gate electrode, and on the semiconductor substrate; and forming a contact window on a portion of the metal silicide layer. i SA; I 2. The method according to item 1 of the scope of patent application, wherein the first gate comprises at least polycrystalline silicon. j 3. The method as described in item 1 of the scope of the patent application, wherein the field oxidation region: includes at least dioxide fragments. : I 4. The method as described in item 1 of the scope of patent application, wherein the second gate contains at least polycrystalline silicon. ! Page 26 4 6 3 3 1 4 VI. Patent Application Range 5. The method described in item 1 of the patent application range, wherein the nitrided layer comprises at least silicon nitride. 6. The method according to item 1 of the scope of patent application, wherein the inner dielectric layer contains at least borophosphosilicate glass (B P S G). The materialized sand belongs to the item of the legal method of the metal: ": the first. The enclosing normalization specifically includes Baoshen Shaoru to 7 layers of materialized sand belongs to the item 1 of the method of the legal method in Jinhai = °. The encyclopedia Fanhuali silicon specially includes Bao Shen Shaoru to the 8th floor to the French-formed window contact boundary without loss of chemical oxygen field avoidance: a type containing a pack of 9 chemical fields in the first region and a chemical field The bottom body is provided with a guide half, and the bottom body of the domain material area is dominated by one pole for the second gate and the polarized oxygen field Hai--D, the second gate and the second pole; the upper gate Nitrogen conductance of the layered layer is half into the shape and the second between the inter-regional wall gaps; a field and the inter-regional interstitial oxygen field; the first part is formed into a cover to cover the layer; and the nitrogen light is etched into the etching Tong Huiqi should remain the pole gate 2 of the left and the pretty one; the polarization of the domain and region is the first; the oxygen layer of the gate blocks the light and the part should be located in the other layer. Page 27 463314 VI. The patent application park forms a metal silicide layer on the first gate and the second gate and the exposed semiconductor substrate; an inner dielectric layer is formed to cover the field oxidation area, The first gate electrode, the second interrogator electrode and the semiconductor substrate; and a contact window is formed on a part of the metal silicide layer. 10. The method according to item 9 of the scope of the patent application, wherein the first gate comprises at least polycrystalline silicon. Page 28 4 633 1 4 VI. Patent Application Range | 1 6. The method as described in item 9 of the patent application range, wherein the metal silicide | layer contains at least titanium petrified. I Page 29 I