TW457712B - Flash memory cell structure for improving the data preservation problem and the programming speed and the formation method thereof - Google Patents

Abstract

A flash memory cell structure for improving the data preservation problem and the programming speed and the formation method thereof is disclosed, the feature of the flash memory cell structure of the present invention is: the silicon nitride passivation layer covers the oxide layer on the source region and the sidewall of its neighboring floating gate structure containing part of the floating gate, therefore, the smiling effect that the gate oxide layer on the edge of the floating gate becomes thicker can be prevented in the formation process of the oxide layer (especially the formation of inter-poly oxide layer), furthermore, since the control gate (word line) and silicon nitride layer covers the oxide layer on the whole upper layer of the floating gate, the problem of unstable control gate resistance resulted from the photolithography overlay process during the source ion implantation, and the problem of oxide layer damage on the floating gate resulted from the ion layer-mixing step of control gate before the formation of silicide can also can be prevented.

Description

457 712 Five 'Description of the Invention (1) Field of the Invention: A modified structure and the present invention are related to the non-volatile memory element, especially the problem of data loss of flash memory cells, and the improvement of oxidation. The smile effect is not conducive to stylized speed flash memory cell formation methods. Background of the Invention: Built-in Cameras When Cameras to Computers When digital cameras first entered the market, they were made into memory systems, allowing you to take about thirty photos at a time. When the memory is full, the user must download the photo images before taking more images. Today, the use of a new type of storage system with low power consumption, high access speeds, and shock-resistant, mobile-resistant, high-stability, and other secure data access conditions has solved the above problems. Flash memory requires very little power. Information can be recorded (or erased) in a more efficient memory segment. () Method, instead of being slower in chronological order than bytes. In addition, once the data has been stored on the disk, the source is no longer needed to hold the data. Generally speaking, current technology can retain stored data for at least ten years even after the power is turned off. This is overshadowing other portable storage systems, so compared to other storage, flash memory is extremely competitive. Tomorrow is dynamic and systematic, that is, the memory is only recorded in blocks, so any power source is in the media star

& After removing the photoresist pattern, using a defined silicon nitride layer as a mask, Dan Shi made a high temperature thermal oxidation process to make the upper surface of the first polycrystalline silicon layer 10 grow by one.

Page 6 4¾ 7 712 V. Description of the invention (3) The center of the oxidized region 25 and the vaporized region 25 is about 120 nm. The values are thin on both sides. This result will make the first polycrystalline silicon layer 1 The upper surface of 〇 shows a structure in which both terminals point upward. Then 'remove the remaining silicon nitride layer mask with a hot phosphate solution, and then use plasma etchant to remove the first polycrystalline stone layer 10 which is not covered by the oxidized area 25'. This is sandwiched by the gate oxide The first polycrystalline silicon layer 10 of the layer 8 and the oxidized region 25 is used as a floating gate. Please refer to FIG. 2 'and form another oxide layer 30 by thermal oxidation. In order to reduce the smile effect which is not conducive to the stylization speed, the formation step includes: firstly thermally oxidizing and then growing an oxide layer of 40 angstroms, and then depositing an HTO oxide layer of about 130 angstroms under a higher temperature f5 environment. In order to reduce the light-to-light ratio of the suspended gate to the control gate, the purpose of growing an oxide layer of 70 angstroms by the thermal oxidation method to make the oxide layer 30 thicker than the gate oxide layer 8 is to reduce the light gate ratio of the floating gate to the control gate. However, the above-oxidation step has caused a certain degree of smile effect at the bottom edge of the suspended gate, as shown by the reference numeral 35 in FIG. 'Next', please refer to FIG. 3, and then form a second polycrystalline silicon layer 40. The thickness of this second polycrystalline layer 40 is about 150-25 nm, and the typical value is about 200 angstroms. Then use the photoresist pattern and engraving technology to define the word line (word 1 ine). After the photoresist pattern is stripped, another photoresist pattern 70 that exposes the source region and part of the oxidized region 25 is formed in all regions. After the β source is implanted, the photoresist pattern is stripped 50 and then annealed in an oxygen-containing atmosphere to expand the source region 60 and increase the coupling ratio of the source region 60 to the floating gate 10. However, the above annealing will worsen the smile effect phenomenon again and make the programming speed worse (because part of the gate oxide layer changes

Lin

Page 7 «57712 V. Description of the invention (4) Thick). Please refer to FIG. 4A, and then form the spacers 65, 68 on the sidewalls of the word line. (The steps include depositing a silicon nitride layer of about 150 angstroms, and then anisotropically etching the gate (control The gate electrode 40 and the floating gate electrode 10) are respectively formed with gap walls 65 and 68. Finally, for the implantation of the drain region, a photoresist pattern 70 is formed on the memory cell to prevent the cloth The implanted ions damage the suspended gate structure (especially the oxide layer 2 5 above the suspended gate). However, due to the overlap error 2 limitation, the ions implanted into the word line have a certain degree of non-uniformity, which makes the strands The resistance value becomes unstable. The top view of Figure 4B also shows the asymmetry due to the stacking error of the photoresist pattern. Please refer to the energy surface of all areas to produce a broken metal pattern. The gold plate was reacted, and then removed, and finally converted into a titanium metal layer having a thickness of about 300 angstroms in the whole figure, and then the ion mixing layer was implanted. This technique is about to adjust Amorphous to the polycrystalline silicon layer or silicon semiconductor substrate and titanium (Amorphous silicon) can improve the quality of the chemical layer. Please note that in this step, photoresist should be avoided. In the step of photoresist removal, titanium will degrade the silicon due to oxidation. Finally, the first comparison The rapid thermal annealing at low temperature forms a low-temperature metal silicide 80 such as C49 Ti Si 2 with the metal layer and the second polycrystalline silicon layer and the semiconductor base of the source and drain regions. Then, a reactive metal layer, such as a spacer, is isolated. The metal layer on the region is subjected to a second annealing to promote the low-temperature metal silicide layer 80 and the lower-resistance metal silicide layer such as C 5 4 T i S i 2.

Page 8

5 'Explanation of the invention (5) Purpose and summary of the invention One object of the present invention is to provide a flash memory which can improve the storage problem and programming speed 2: the method of manufacturing flash memory data. Another object of the present invention is to provide a method for improving the flash memory cell structure of the flash memory data storage gate for opening and closing, and the speed of programming and programming. Another object of the present invention is to provide a fast-breaking siliconized silicon coating layer that closes the source region to the suspended JS memory cell structure. During the formation of the oxide layer, "specially, the electrode is covered by the edge. The interstitial complex spar oxygen * is caused by this call to oxidize from 1 high temperature to cause suspension: not to mention the formation of metasilicon silicon with a wide range of oxygen values) In addition, it is also due to the problem of controlling the leisure time of the oxide layer. The oxide layer on the upper layer is covered with light. The lithography and photolithography are limited, and the control of the gate is blocked by the control of the gate. The blue pole is damaged by the planting before the formation of metal compounds. τ Integrity: The limitation of the micro-traveling limit leads to the blocking of the control gate. It is not clear how to open the fog. A flash memory cell structure and method of forming the flash gate. Use this flash memory field to save data and program speed. In order to improve 1 cell must contain • Suspended gate structure 'formed on a semiconductor substrate' with a polar oxide layer / first polycrystalline spar crystal layer / Earth-Earth stage flash structure ^ 457712 • · *-«

V.V V. Description of the invention (6) A source region is formed in the semiconductor substrate, and the suspended gate extends to the semiconductor substrate outside the suspended gate structure. 'A control gate is formed on the semiconductor substrate.' Above the sidewall of the electrode structure and a portion of the first oxide layer, a drain region is formed in the semiconductor substrate, extending from the edge of the control gate to the semiconductor substrate leaving the suspended gate structure, so that the drain, control gate, and suspension The gate and source regions are sequentially presented in one direction, and a second oxide layer is formed on the semiconductor substrate and the floating gate structure. The flash memory cell structure of the present invention is characterized in that a nitrogen silicon oxide coating is formed on the second oxide layer, the nitrogen silicon oxide coating covers the source region and covers the side wall of the suspended gate structure, and then covers the first A portion of the upper surface of the oxide layer 'so' the first oxide layer above the suspended gate is completely covered by the control gate and the nitrogen-silicon oxide cover layer, and the control gate is adjacently connected via a portion of the second oxide layer The semiconductor substrate and the floating gate. The method for forming the nitrogen-silicon oxide coating layer is to deposit a silicon nitride layer, and then define a position with a photoresist pattern. Finally, the annealing step after the implantation of source impurity ions is performed in an oxygen-containing atmosphere to convert the silicon nitride layer Oxide layer, of course this. Nitrogen silicon oxide layer can also be deposited directly to control the ratio of oxygen and nitrogen. Because of the existence of this nitrogen silicon oxide coating, it can prevent the first oxide layer from being damaged during ion implantation and cause the first oxide layer. Trap electrons so that the stored data is unstable.

V. Description of the invention (7) and d: In addition to providing a structure of a single-opening * flash memory cell, a method for forming a nor-type flash memory cell array. Detailed description of the invention: In the flash memory cell manufacturing process of the following methods, the traditional method described in the background of the invention needs to be overcome:

Above 1) As a result of the oxide layer formation process, #other than the A-gate flash memory gate oxide layer of the mesomorphic dream oxide layer, the sraiHng effect of the thickened gate oxide layer due to oxidation is generated due to oxidation. , Which is not conducive to the coupling ratio of the source to the floating gate, and makes the stylization speed worse. 0 (2) When ion implantation in the light pole region, a photomask is usually added to the memory cell to prevent the implantation. The ions hurt the suspended gate structure (especially the oxide layer above the suspended gate). However, this will cause the resistance of the gate to be unstable due to uneven distribution of the conductive impurities in the control gate due to stacking errors. (3) In addition, when forming a self-aligned titanium silicide layer of a source electrode and a gate electrode, an i on mixi ng is usually performed after the titanium metal is deposited to improve the quality of the titanium silicide layer. (Ion implantation at the interface between the polycrystalline silicon layer and the titanium metal to produce an amorphous silicon. It is best not to form a photoresist pattern in this ion mixing step, so as not to adversely affect titanium.

Page 11 45 >? 71 2 V. Description of the invention (8) '--Quality of metal oxides' and the result of not using a photoresist pattern will expose the oxide layer above the levitation gate and cause ion damage Including the electron trapping ('electron trapping') makes the data retention ability worse, a. Therefore, this step in the traditional method will cause a dilemma. In order to solve the above-mentioned problems, the present invention will provide a partitioned flash memory cell structure. The source region is covered with a silicon nitride oxide coating layer, and the side wall adjacent to the suspended gate structure is covered, and then covered above the first oxide layer. A part of the surface 'so that the nitrided cover layer and the crystalline silicon layer controlling the gate can completely cover the oxide layer above the suspended gate', so the ion region of the drain region can be fully implanted without the need for a photoresist pattern 'And the problem of ion mixing layer after titanium metal deposition can be solved.' Another benefit is that not only the inter-crystalline silicon oxide layer can prevent the occurrence of smiles, but also the annealing of the source area after the source is implanted can prevent smiles. Reappear β. The details of the following invention can be described in detail with reference to the drawings and describe the method of making the flash memory element of the present invention. Figures 6A and B respectively show the gate oxide layer. The floating gate stack structure of the gate oxide layer 1/10 / first oxide layer 1 10 / first oxide layer 25 is formed on the active area of a semiconductor substrate 105. Cross-section schematic and top view on 104. The method of forming the floating gate stack structure is as follows: First, the shallow trench isolation region 2 and the active region 104 are defined on the semiconductor substrate 105 by the conventional method, and then the temperature is about 80 0-9 50 ° C by the thermal oxidation method. Forming a gate oxide layer 108 on a < 100 > crystal

Page 12 15771 2 V. Description of the invention (9) The thickness of the single-crystal semiconductor substrate i 05 gate oxide layer i 〇8 in the bulk direction is approximately 7.0-10.0 ⑽, with a typical value of 80 nffi. A low-pressure chemical vapor deposition (LPCVD) method is then used to deposit a first polycrystalline silicon layer 110 at a deposition temperature of about 550-650. C, the thickness of this first polycrystalline silicon 11 0 is about 8 〇 _ i 2 〇 ηη, the typical value is 100 nme

P Then, a low-pressure chemical vapor deposition method is used to fully deposit a silicon nitride layer (not shown) with a thickness of about 8 Onm. Subsequently, a photoresist pattern (not shown) is formed on the nitride breakdown layer (not shown). (Shown) to define the position of the floating gate. Next, an anisotropic etching method is used to etch the silicon nitride layer (not shown) to transfer the photoresist pattern onto the silicon nitride layer. After removing the photoresist pattern, a high temperature thermal emulsification process is performed to make the first The first oxide layer 125 is grown on the top surface of the polycrystalline stone layer 110. The thickness of the first oxide layer 125 is about 120 nm, but both sides are very thin. This result will make the first polycrystalline silicon layer 11 The upper surface shows a structure with the two terminals pointing upward. Then, the remaining silicon nitride mask is removed with a hot phosphate solution. Then, plasma etching is used to remove the first polycrystalline silicon layer 110 that is not covered by the first oxide layer 12 5 'and finally wetting with a diluted hydrofluoric acid or B 0 E solution to remove the gate on the semiconductor substrate 105 Polar oxide layer 1 0 8 »Subsequently, please refer to the schematic cross-sectional view shown in FIG. 7 to form a second oxide layer 130 after the suspension gate stack structure is formed. The method for forming the second oxide layer 130 is as follows: 'First, a two-temperature thermal oxidation process is performed to form a thin oxide layer, which is about 40 angstroms.' This step can also be omitted to prevent the gate oxide layer edge during the oxidation process. Thickening smile phenomenon. LPCVD

Page 13 457712 V. Description of the invention (ίο) A high-temperature oxide layer (hereinafter referred to as HTO oxide layer) is deposited on the side surface of the floating gate structure and the rest of the semiconductor substrate 105. In a preferred embodiment, the 'ΗT0 oxide layer 1 30 is in the range of 800-900. C deposited to 10--20 nm

About 650 by LPCVD. C deposit a silicon nitride cover layer 140 on all surfaces, the thickness of the silicon nitride layer is about 10-40 nm (typically about 200 angstroms), and then a photoresist pattern 1 4 5 is formed on the silicon nitride layer, and then The photoresist pattern 1 4 5 is used as a mask, and a silver engraving technique is applied to form a nitride stone cover layer 14. In the preferred embodiment, the source region adjacent to the floating gate and the first oxide layer 12 5 on the floating gate need to be covered with a continuous nitride coating layer 140. In addition, the coverage of the nitride coating layer 140 must be at least partially overlapped with the control gate formed later to completely cover the first oxide layer 1 2 5. The silicon nitride covering layer 140 can avoid the occurrence of the smile effect, thereby indirectly increasing the coupling ratio of the source region to the floating gate, and thus increasing the programming speed. Therefore, after the formation of the nitrided stone overcoat layer 140, the high temperature thermal oxidation process can be continued to form an oxide layer with a thickness of about 70 Angstroms. Please note that only the side close to the drain region is shown in this step as shown in the figure. As shown in the medium index 14 8, there will be a smile effect phenomenon. The side relying on the source region is not shown as the index 1 4 9. Therefore, the coupling ratio of the source to the floating gate will not decrease. Please note that at this time The silicon nitride coating 1 40 will thus be converted to an oxyni tride 140.

Page 14 J57T1 2 .. V. Description of the invention (11) Next, please refer to the schematic diagram of the cross section in Fig. 8 to form the second polycrystalline stone layer. The thickness of this second multicrystalline fragment is about 15 0-2 5 0 n m, with a typical value of about 2 0 0 0 Angstroms. Then use the photoresist pattern (not shown) and etching technology to define the word line (w 〇rd 1 ine) 1 5 0 'Please note that the word line must be able to cover at least part of the nitrogen silicon oxide coating 1 4 0 to prevent the floating gate The first oxide layer 1 2 5 (or the second oxide layer 1 3 0) is exposed. After the photoresist pattern is peeled off, another photoresist pattern 160, which exposes the silicon nitride oxide overcoat layer 140, is formed in all regions for the ion implantation of 170 in the source region. Next, the photoresist pattern 16 is stripped and then annealed in an oxygen-containing atmosphere to expand the source region 170 and increase the ratio of the source region 170 to the floating gate 1 110. In a preferred embodiment, the implanted ionic n-type conductive impurities, such as scales, have an energy and dose of approximately 2 0-6 0 ke V and 1 X 1 0 14-1x 1 0 16 / cm2. Because it is covered by the nitrogen-silicon oxide cover layer 1 40, the annealing will not cause a smile effect, so the coupling area of the source region to the floating gate will not be reduced, which can naturally increase the programming speed. Please refer to Figure 9 A, a low-pressure chemical vapor deposition method is used to fully deposit a silicon nitride layer of about 1 500 angstroms in all areas, and then an anisotropic method is used to form large and small gaps, respectively. 1 6 8 on the side wall of the word line and the side wall of the floating gate stack structure (large and small gaps 1 6 5 and 1 6 are due to the aspect ratio), due to the previously deposited nitrided oxide coating layer has been oxidized The silicon nitride oxide cover layer 1 40. The silicon nitride layer and the silicon nitride oxide layer have an etching option.

Page 15 457 71 2 V. Description of the invention (12) Select ratio, so the non-isotropic residual silicon oxide cover layer 14Γ will not be removed when the formation of the drain electrode 175 at this time. When the source / non-polar area is planted and the seed is planted, the first and the gas-breaking oxidation cover layer 140 are not covered, and the photoresist pattern is not needed. Therefore, the i-layer causes damage. In addition, Due to the different parts of 150), the sons are simultaneously implanted in the word line (the second polycrystalline stone layer has a problem of uneven resistance. The word line 150 does not generate ions that are clearly drained as in the traditional method: ^ shows a top view, Please compare with Figure 4B for the error problem. I don't need a photoresist pattern. "There is no lithography. Please refer to Figure 10." Fully form a titanium metal layer with a thickness of about 300 angstroms and perform Shi Xi ion in all areas. Ion mixing is implanted. The energy of this technology can be adjusted to the interface between the polycrystalline silicon layer or the silicon semiconductor substrate and the titanium metal to generate an amorphous hair (amorph〇us si 1 i con). In order to improve the quality of the titanium metal dream, in a preferred embodiment, the energy and dose of implantation They are 3 0-50 keV and 5x 10 u-3x l0i5 / cm2. Because the nitrogen-silicon oxide coating 14 0 is covered with ion implantation, it will not cause damage to the first oxide layer. Please note that this The steps are still the same as those described in the background of the invention. The use of photoresist patterns should be avoided. Otherwise, in the step of removing photoresist, the catalyst will be oxidized and the characteristics of the metal fragments will be deteriorated. Finally, the first low temperature rapid thermal annealing is performed. In order to promote the reaction of the metal layer with the second polycrystalline silicon layer 150 and the semiconductor substrate of the source and drain regions to form a low temperature metal silicide 19 0 such as C49 TiSi2, then,

Page 16 457712 V. Description of the invention (13) Unreacted metal layers, such as those on the barrier wall, isolation zone, etc. are removed by wet etching, and then a second annealing is performed to promote low temperature The metal silicide layer is converted into a metal silicide layer with a lower resistance 190 such as C 5 4 T i S i 2. In a preferred embodiment, the annealing temperature of the first lower temperature rapid thermal annealing is about 650-750 t, and the annealing temperature of the second higher temperature rapid thermal annealing is about 750-900 °. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention = patent application; all other equivalent changes or modifications that do not depart from the spirit disclosed by the present invention should be included in the following Within the scope of the patent application.

Page 17 4 5 7 71 g_ Schematic illustration of the preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following graphics: Figure 1 shows the traditional method of making the flash memory opening and closing A cross-sectional view of a floating gate stack structure with a gate oxide layer / first polycrystalline silicon layer / first oxide layer formed on a semiconductor substrate. FIG. 2 is a schematic cross-sectional view of a conventional method for forming a second oxide layer on a floating gate stack structure and a semiconductor substrate. Figure 3 shows that it is not the intention to make the flash memory cell by the conventional method to complete the ion implantation in the source region and to expand the cross section of the source region after annealing. Figures 4A and 4β are schematic cross-sections and top views of forming a photoresist pattern on the control gate for plant-source region implantation but with overlapping errors. Figure 5 shows a schematic cross-sectional view of a conventional method for fabricating an open flash memory cell to perform ion mixing and form a metal silicide layer. FIG. 6A and FIG. 6B respectively show that the gate flash memory cell is manufactured by the method of the present invention to form a gate oxide layer / the first polycrystalline silicon layer / the first oxide layer and the suspended gate stack structure is formed in a A cross-section and a schematic plan view on a semiconductor substrate. FIG. 7 shows a schematic cross-sectional view of forming a second oxide layer and a silicon nitride capping layer by the method of the present invention. Figure 8 shows the cross-section of the flash memory cell manufactured by the method of the present invention to completion (source implantation in the source region and annealing to expand the source region. Figures 9A and 9B respectively show the use of the present invention. Method, forming a cross-section wall and applying ion implantation to form a schematic cross-sectional view and a top view of an electrodeless region.

1 ^ =.

P.18 4STT1 c Simple description of the circular type. Figure 10 shows a cross-sectional view of the method of the present invention for manufacturing branch ion-mixed layers and forming a metal silicide layer: a comparison table: 5, 105 semiconductor substrates 8, 108 anode oxide layers 10, 110 first polycrystalline silicon layers, 25 Oxidation area 30 Oxidation layer 35 Smile effect phenomenon 40 Second polycrystalline silicon layer, 50 '70, 145, 160 Photoresist pattern 60, 170 Source area 65> 68' 165 '168 Size gap 80' 190 Metal silicide 102 Isolation area 104 Active area 125 First oxide layer 130 Second oxide layer 140. Silicon nitride cover layer, 148 Smile effect phenomenon 149 No smile effect phenomenon 150 Word line (word 1 i η 1 175 Drain region floating gate electrode system Gate silicon oxide coating

Claims (1)

4 5 7 71 VI. Applying for a patent Fanyuan-i. The flash memory cell structure between the suspected seed modification / data saving problem and the stylized speed, the flash memory opening: the memory cell structure has a gate oxide layer / A floating gate stack structure of two polycrystalline silicon layers / first oxide layers is formed on a semiconductor substrate, and a source region is formed in the semiconductor substrate on one side of the floating gate stack structure, and A control open electrode is formed below the floating gate stack and is formed on the semiconductor substrate. “Partial suspension interfacial system 2”: A drain region is formed on the semiconductor substrate β, away from the control m to the The source region extends in the direction, and the second oxide-controlling layer is formed on the semiconductor substrate. The direction is presented in sequence, and the structure of the flash memory cell is characterized by "." The cover layer is formed on the second oxide layer and the second oxide layer of the suspension ^ ^ = covered by the control gate, so as to make the suspension; the rest of the structure and the nitrogen and silicon oxide cover layer Wrapped. The stack structure is completely the control room. 2. If the control section of the patent application scope item 1 covers the nitrogen-silicon oxide coating, the structure of the nitrogen-oxide oxidation coating can be completely covered to ensure the control. The inter-electrode and the stack structure of the suspended ocean gate. Among them, 3. The flash memory cell in item 1 of the scope of the patent application is oxidized in the ceremony. The thickness of the cover layer is about 100 ~ 4〇ο #. Formation 4 · The memory cell structure of the flash seal, such as item 1 of the scope of patent application, further includes 4577t. 6. The gap between the side wall of the control closed pole and the oxidized coating layer of the scope of the patent application to the above source. Extremely extended partition wall. · 5 · The flash memory cell structure according to item 1 of the scope of the patent application ', wherein the above control gate includes at least a metal dream and a second polymorphite layer. 6. —A split flash memory cell structure that improves the problem of data retention and stylization speed. The flash memory cell structure includes at least: a gate oxide layer / first polycrystalline silicon layer / first oxide layer structure A floating gate structure is formed on a semiconductor substrate; a source region is formed in the semiconductor substrate on one side of the floating gate stack structure, and extends to a part of the area below the floating gate stack structure; a second oxidation A layer is formed on the semiconductor substrate and the floating gate structure; a control gate is formed on the semiconductor substrate and the second oxide layer on a part of the floating gate stack structure; A a drain region is formed on the semiconductor Within the substrate, extending from the edge of the control gate to a direction extending away from the source region, the source electrode, the control gate, the suspension gate, and the source region are sequentially presented in a direction; and A gas oxide coating is formed on the second oxide layer in the source region and the second oxide layer in the rest of the floating gate stack structure that is not covered by the control gate to make the suspension The gate stack structure is completely covered by the control gate and the oxynitride coating. 45771 VI. Scope of patent application 7. For the flash memory cell structure in the scope of patent application item 6, the control gate part covers the nitrogen-silicon-oxide covering layer to ensure that the control gate and the nitrogen-silicon-oxide covering layer are in common. The floating gate electrode stack structure is completely covered. 8. For the flash memory cell structure in the sixth item of the patent application, wherein the thickness of the nitrogen-silicon oxide coating is about 100-400 angstroms. 9. If the flash memory cell structure of item 6 of the patent application scope further includes a spacer formed on the side wall of the control gate and a spacer on the side wall of the floating gate stack structure. 10. According to the flash memory cell structure in the sixth aspect of the patent application, wherein the control gate includes at least a metal silicide and a second polycrystalline silicon layer. 11. A method for forming a flash memory cell that improves data storage problems and programming speed, the method includes at least the following steps: providing a semiconductor substrate, the substrate has formed a gate oxide layer / first polycrystalline silicon layer / A suspended gate with a first oxide layer structure; forming a second oxide layer on the suspended gate and the semiconductor substrate; forming a continuous silicon nitride coating layer covering the source region and about half the suspended gate region; using a thermal oxidation method Forming a third oxide layer; depositing a second polycrystalline silicon layer on the third oxide layer; Page 22 5771 2 VI. Scope of the patent application The lithography and etching technology is used to define the second polycrystalline silicon layer to form a word line. The source region is ion-implanted with conductive impurities. A high-temperature oxygen-containing environment is applied. Annealing process to promote the further lateral diffusion of conductive impurities in the source region into the semiconductor substrate under the floating gate region; forming a silicon nitride sidewall layer on the side of the word line and the floating gate region near the source region The sidewalls are used as silicon nitride spacers; ion implantation is performed in full on the source region, the word line and the drain region, and the spacers and the silicon nitride cover layer are used as a mask; and A metal silicide layer is formed on the word line and the source and drain regions. 1 2. The method according to item 11 of the scope of patent application, wherein the method for forming the above-mentioned gate oxide layer / first polycrystalline spar crystal layer / suspended gate structure of the first oxide layer includes at least: forming a gate electrode An oxide layer on a semiconductor substrate; forming a first polycrystalline silicon layer on the gate oxide layer; forming a first silicon nitride layer on the first polycrystalline silicon layer; defined by lithography and etching technology The first silicon nitride layer defines the position of the suspended gate; applying a thermal oxidation method to form the first oxide layer on the first polycrystalline silicon layer; removing the first silicon nitride layer; and applying a surname Engraved to remove the first polycrystalline stone Page 23 4S7712 VI. Applying for a patent scope layer to form the suspension gate "1 3. The method according to item 11 of the patent scope, wherein the above-mentioned step of forming a second oxide layer on the suspension gate and the semiconductor substrate is at least Contains deposited ΗTO oxide. 14. The method according to item 13 of the scope of patent application, further comprising forming a thin oxide layer having a thickness of about 100 to 2000 angstroms by a high-temperature thermal oxidation process before depositing the ITO oxide layer. 15. The method according to item 11 of the scope of patent application, wherein the method for forming a silicon nitride cover layer includes at least the following steps: forming a silicon nitride layer on the second oxide layer; and lithography and etching The technology defines the silicon nitride layer to form a continuous silicon nitride layer covering the source region and about half the suspended gate region on the second oxide layer. 16. The method according to item 11 of the scope of patent application, wherein the above-mentioned step of ion implanting the source region with conductive impurities at least includes: forming a photoresist pattern exposing the source region on the second polycrystalline silicon Layer; applying ion implantation technology to implant n-type conductive impurities; and removing the photoresist pattern. 17. The method according to item 11 of the scope of patent application, wherein the above-mentioned annealing process applying a high-temperature oxygen-containing environment will simultaneously form a thin oxide layer on the suspension gate. Page 24 1S771 2 VI. Scope of patent application The exposed surface of the semiconductor substrate and the silicon nitride coating layer are oxidized to form a silicon nitride oxide coating layer. '18. The method according to item 11 of the scope of patent application, wherein the above-mentioned method for forming a silicon nitride spacer comprises at least: forming a silicon nitride layer on the nitrogen-silicon oxide cover layer; and applying an anisotropy The etching method is used to form the silicon nitride spacer on the side wall of the word line and the side wall of the floating gate region near the source region. 19. The method according to item 11 of the scope of patent application, wherein the step of forming a metal [化 物 silicide layer on the word line and the source and drain regions at least comprises: depositing a metal layer on the silicon nitride barrier wall as described above] After the structure; performing ion implantation, implanting ions at the interface between the metal layer and the second polycrystalline silicon layer, and the interface between the metal layer, the source, the drain region, and the metal layer; The first annealing is used to promote the metal layer to react with the second polycrystalline silicon layer and the semiconductor substrate of the source and drain regions to form a low-temperature metal silicide; remove the unreacted metal layer; and perform a second annealing To promote the conversion of the low-temperature metal silicide layer into a metal silicide layer having lower resistance than the low-temperature metal silicide layer. -20. If the method of the scope of patent application No. 19, wherein the first annealing temperature is about 650-750 ° C, and the second annealing temperature is about 75 0-900 ° C. Page 25