TW514913B - Manufacturing method of flash memory cell with improving programming and erase speed - Google Patents

Abstract

A split-gate flash memory formation method consists of implanting dual carriers into a first poly-silicon layer, sequentially defining a floating gate, high temperature thermal oxidation process for forming gate oxide on the floating gate, and forming inter-polysilicon oxide layer and control gate. Because the arsenic ion diffuses slowly, it almost stops at the floating gate adjacent to the channel. The higher impurity concentration reduces the depletion region, so the programming speed increases. On the other hand, only phosphorus ion diffuses to the poly-silicon tips near the control gate, so the floating gate impurity increasing and depletion region reducing don't let the inter-polysilicon oxide layer near the tips become thicker and then increase the erase speed.

Description

514913 V. Description of the invention (1) Field of the invention: The present invention relates to non-volatile memory elements, in particular to a kind of flash memory that uses regional heavy ion implantation to improve the programming and erasing speed of open flash memory cells. Cell formation method. Background of the Invention: When digital cameras first entered the market, they were made into a system with a built-in memory, allowing you to take about thirty photos at a time. When the camera's memory is full, the user must download the photo image to the computer before taking more images. A kind of low power consumption, high data access has made the information available today. High stability and other safety data. The use of flash memory cards requires very little power. ) Way to record (or slow. In addition, the data source is used to retain data. It can still be stored after being turned off. Compared with other portable storage, flash memory posture. Not just digital erasure) Once you save the general resources The system has a camera, and the problem of access speed conditions is more serious than the magnetic disk language. It is expected that the at least eclipsed note-taking degree and the full-blown and efficient image are in place. Over ten years, so competitive computer, shockproof, new storage. Fast memory area tuples are no longer technical. This and others. Full palm-type, mobile-resistant, memory-based, flash memory is only a block (sequence records, so any electricity is needed, the power is in a kind of advantage, the storage medium has been used, the star of tomorrow, the electronic memo

Page 5 514913 V. Description of the invention (2) Thin, mobile phones and other electronic products, the demand for flash memory is even more inseparable. Fast because of floating space. Gates and suspensions are favored to use memory and Qingliji to protect the body, so the flash material memory industry can quickly record the number of gates flashing is the fastest stack of poems. The sum of shorthand is to record the coupling of the fast pole material gate in addition to the flash point and the flash point. The gate capital can be divided and floated in this way. The suspension factor method is used again and again. The flash body control terminal and quick recall has a sharp memory. Flashover Flash »The following will first introduce the traditional method of manufacturing flashover flash memory, then analyze its problems and the motivation of presenting the present invention. Please refer to Table 1 in the table. First, a gate oxide layer 8 (thickness about .7. 0-1 0. 0 nm, typical value) is formed on the upper surface of a semiconductor substrate (such as a silicon wafer) 5 by a high-temperature thermal oxidation process. 8.5 nm) over the semiconductor substrate 5, and then another first polycrystalline silicon region 10 (thickness about 80-150 nm, typically about 100 nm) is deposited on the gate by chemical vapor deposition Above the polar oxide layer 8. Next, a silicon nitride layer 15 is formed, and the nitride nitride layer 15 is about 8 O nm thick. A photoresist pattern 20 is then formed on the silicon nitride layer 15 to define a floating gate region. Next, the exposed nitride layer 15 is etched by dry etching, and the photoresist pattern 20 is used as a mask. Phosphorus ions are used as n-type conductive impurities and implanted in the first polycrystalline silicon layer 10 by ion implantation (the phosphorous ions are shown by dashed lines in the figure). In a typical embodiment, ion implantation Energy and dose points

Page 6 514913 V. Description of the invention (3) It is about 20 k e V and 2 E 1 4 / c m 2 respectively. Next, a second ion implantation is performed, and a P-type conductive impurity such as B + is implanted in the channel (channe 1) of the semiconductor substrate 5 below the first polycrystalline silicon layer 10 (gate oxide layer 8 or less in the figure). The dashed line indicates the shed ion), which is used to adjust the initial voltage of the flash memory cell channel. The energy and dose of ion implantation are about 65keV and 7E12 / cm2. Next, as shown in FIG. 2, after the photoresist pattern 20 is removed, the nitrided chip layer 15 having been defined is used as a mask to perform a thermal oxidation process at South temperature to make the top of the first polycrystalline silicon layer 10 0 A first silicon oxide layer 25 is grown on the surface, and the first oxidized stone layer 25 bulges above the gap of the nitrided stone pattern layer 15 A. At the same time, the polycrystalline stone layer 1 sinks due to consumption, making the center thick. Approx. 120 nm. In addition, both sides of the first oxidized stone layer 25 have lateral diffusion (as shown by the arrow) due to the heating of the plate ions, which has the property of promoting the oxidation rate. A polycrystalline silicon layer 10 forms an interesting shape with a wide semicircle and a narrow upper semicircle as shown in the figure, and also forms a sharp corner 18 of the polycrystalline silicon layer. Next, please refer to FIG. 3, first remove the remaining silicon nitride layer mask with a hot phosphate solution, and then remove the first polycrystalline silicon layer 10 which is not covered by the oxidized area 25 with a plasma etchant. The gate oxide layer 8 and the first polycrystalline silicon layer 10 in the oxidized region 25 are used as suspended gates. Finally, it is wetted with diluted hydrofluoric acid or BOE solution to remove the gate oxide layer 8. ^ Still referring to FIG. 3, after the suspension gate structure is formed, a second oxide layer 30 is formed on the side wall of the suspension gate structure and the semiconductor substrate 5. Second oxygen 514913 V. Description of the invention (4) The method for forming the chemical layer 30 is to use a high-temperature thermal oxidation process to form an oxide layer with a thickness of about 180 angstroms, and then deposit a second compound by a low-pressure chemical vapor deposition method. Crystal silicon layer. The thickness of the second polycrystalline silicon layer is about 2000 angstroms. Then, a photoresist pattern (not shown) and #etch technique are used to define the word line (w 〇 r d 1 i n e) 50. Next, please refer to FIG. 4. After the photoresist pattern is stripped, another photoresist pattern exposing the source region is formed in all regions for the implantation of 70 ions in the source region. In a preferred embodiment, the implanted conductive impurities are phosphorus ions, and the energy and dose of the ion implantation are 40 keV and 5E 15 / cm 2 respectively. After the photoresist pattern is stripped, annealing in an oxygen-containing atmosphere is performed to expand the source region 70 and increase the coupling ratio of the source region 70 to the floating gate 10. Then, the photoresist pattern is peeled off, and then another photoresist pattern exposing the drain region is formed to cover all the regions, and is used for implanting the drain region 75 ion. In a preferred embodiment, the implanted conductive impurities are arsenic ions, and the energy and dose of the ion implantation are about 40 k e V and 5 E 1 5 / cm 2, respectively. OBJECTS AND SUMMARY OF THE INVENTION The object of the present invention is to improve the problem of the empty area of the floating gate so as to improve the programming speed of the opening flash memory. At the same time, the concentration of impurities in the side wall of the floating gate should be small to increase the programming speed. , The erasing speed can also take into account the flash memory manufacturing method.

Page 8 514913 V. Description of the invention (5) The present invention discloses a method for forming flash memory cells that is opened and closed. In this method, phosphorus and arsenic are used as the two carriers implanted in a defined suspension gate. In the first polycrystalline silicon layer under the silicon layer, a high-temperature thermal oxidation process is sequentially performed to form an oxide layer on the suspended gate, a multi-crystalline silicon inter-layer oxide layer is formed, and a gate flash memory is formed to control the gate. Method, in which the arsenic ions in the double carrier diffuse slowly, so they almost stop at the floating gate adjacent to the channel, the impurity concentration is high and the empty region is reduced, so the programming speed is increased, but it is close to the control gate The sharp corners of the polycrystalline silicon are only diffused by phosphorus ions. Therefore, the impurity concentration of the suspended gate will not increase, and the decrease in the empty region will lead to the thickening of the oxide layer near the sharp corners of the polycrystalline silicon, which also improves the data. Erase speed. Detailed description of the invention: In the flash memory cell manufacturing process of the traditional method described in the background of the invention above, the following problems need to be overcome: the floating pole temperature of the internal oxygen-coupled thermal gate is high, and the floating suspension is connected to the channel. The isolated pole fills the adjacent source, so the area is lacking, so the side wall of the pole with a large wall is changed, and the gate is floating and suspended, and it is changed from scattered to the lowest. The reduction ratio (lower this factor) is used to reduce the acceleration and increase the speed of the electric circuit. The gate system g control 8 and the head pole arrow gate are floating as shown in the figure.

Page 9 514913 V. Description of the invention (6) (2) As the empty area of the floating gate increases, the F N tunneling energy barrier from the floating gate to the control gate increases, which will reduce the erasing speed. In addition, after erasing, when reading the data, the variability of the starting voltage V t of the floating gate will increase due to the large empty area of the floating gate, which will further increase the variability when reading the current. Also increase in sync. (3) In addition, if the problem of the empty area of the suspended gate is solved by increasing the phosphorus ion concentration of the suspended gate, the oxidation rate of the oxide layer on the side wall of the suspended gate will increase due to the increase of the concentration of phosphorus ions, which will cause the erasing speed of the side wall. Slow down. In order to solve the above-mentioned problems, the present invention will provide a method for manufacturing a flash memory cell that can be opened and erased at a slower speed than the background of the invention. The drawings are used to explain in detail and depict the method for manufacturing the open flash memory device of the present invention. Please refer to FIG. 5. First, the conventional method is used to define shallow semiconductor substrate 105 in the conventional method> the trench isolation region 1 02 and the active region 104, and then the temperature of the thermal oxidation method is about 8 0 0 _ 9 5 0 ° C. A gate oxide layer 108 is formed on a < 1 0 0 > single crystal semiconductor substrate in a crystal direction. The thickness of the gate oxide layer 108 is approximately 7.0 to 1.0 nm, typically The value is 80 nm. Low pressure chemical vapor deposition (LPCVD)

Page 10 514913 V. Description of the invention (7) —----——-____ Full deposition of a first polycrystalline silicon layer The thickness of the first polycrystalline silicon 110 is about 550450. (: Then, the low-pressure chemical vapor phase is used to fen nm, with a typical value of 100 nm. A silicon nitride layer of 80 nm is then coated with a thickness of about 115 and above. Defining the position of the floating gate = arranging a photoresist pattern 120 on the silicon nitride layer, please refer to FIG. 6, and then,-the stone layer 1 1 5 to transfer the photoresist pattern to The first ion implantation was performed, and the phosphorus and the gasified fossil layer u 5 were implanted three times tightly, and a layer 11 0 was applied. A preferred embodiment was applied to the first amount of polycrystalline silicon in the exposed path. Phosphorus ions are about the heart: the energy of the zirconium and the agent lE14-8E14 / cm2 (typical value is about 2 e (eight = value is about 20 keV) and about ^ 50 keV (typically for the ion (As +) and the type value is about 3E14 / J), the spoon is the test) and 1E14-8E14 butterfly, and then apply the first: secondary ion implantation, planting type: such as, B + in the first, Shi Ximen 10 times … The conductor substrate is used for this flash, the initial voltage adjustment of the memory cell channel, the energy and dose of ion implantation, for boron ions are about 30_80 keV (typically about 65 keV) and 3E12- 9E12 / Cm2 (typical value is about 7E12 / cm2). For planting, the energy and dose of ion implantation are about 90-180keV (typical value is about 7E12 / cm2). LlOkeV) and 3E12-9E12 / cm2 (typical value 514913). 5. Description of the invention (8) The resistive element is connected. The master & M ^ process uses the first -nitride to examine Figure VII and applies high temperature thermal oxidation. ^, ^ The silicon oxide layer 125 and the first silicon oxide layer 125 are not shown in the figure. The gap between the ratified silicon pattern layer 115A bulges, and at the same time, the polycrystalline silicon; n5 layers! The two sides of the 25 'are special because of the scale ions that promote the oxidation rate. (Shown) Consumption ^ J 石 石 夕 层 U. And the formation of a semicircle width as shown below * = interesting shape, while also forming a polycrystalline silicon layer sharp corner 118. 牛 ® 奇 Cha 的 重 彳 ί 于, / Arsenic ions (represented by circles in the figure) are much heavier than phosphorus ions (atomic order 65 to 31), so in this step, only the sub-system, ,,, and oxidation time, and temperature can cause the stone to leave the k field. Control = the first oxygenated layer scattered below the nitrogen-cut layer 115 is disposed in the crystalline silicon layer 110. In a preferred embodiment, the following _ brother-thermal oxidation system The temperature is about 8 0 0-1 0 0 0 ° C. The temperature of Υ β is next, please refer to Figure 8, and then use hot phosphate solution to remove 昤 Α | > = layer 115 mask. Then engraved with electricity Removal is not left = the mouse pole junction i removes the interrogation oxide layer 1G8, and the suspension gate is formed as shown in the figure. Please refer to FIG. 8. Then, the suspension gate structure is formed again.

Page 12 M4913 V. Description of the invention (9) The second oxide layer 130 is on the side wall of the floating gate structure and the semiconductor substrate. The oxide layer 130 can be formed by a high-temperature thermal oxidation process to form an oxide layer with a thickness of about 12-25 nm (typically about 18 angstroms). Or another method is to first use a high-temperature thermal oxidation process to form a long thin oxide layer with a thickness of 3 to 10 nm. Then, a high-temperature oxide layer (hereinafter referred to as HTO oxide layer) is deposited by LPCVD. In a preferred embodiment, the HTO oxide layer is deposited at 800-1000 (TC to about 120 nm. Please note that the process of growing the second oxide layer 130 on the side wall of the suspended gate structure However, the growth rate of the second silicon oxide layer will not be affected by this effect. This is a characteristic of the extremely slow diffusion rate of heavy ions in a high-temperature thermal oxidation process. Next, please refer to the cross-sectional schematic diagram in FIG. A low-pressure chemical vapor deposition method is used to deposit a second polycrystalline stone layer. The thickness of the second polycrystalline stone layer is about 15 0-2 50 nm, and the typical value is about 2 0 0 angstrom. (Pictured) and etching technology to define a word line 150. Next, please refer to FIG. 10, after the photoresist pattern is stripped, a photoresist pattern 1 6 of another source region 1 5 is formed in all Area for ion source implantation in the source region. In a preferred embodiment, the conductive impurities are phosphorus ions, and the energy and dose of the ion implantation are 20-60 keV, respectively. And 2E15-9E15 / cm2 (typical values are about 40 keV, and 5E15 / cm2). After the photoresist pattern is stripped off, the stripping is performed in an oxygen-containing atmosphere. Fire to expand the source region 170 'to increase the coupling ratio of the source region 170 to the floating gate π.

Page 13 514913 V. Description of the invention (ίο) Then the photoresist pattern 1 60 is peeled off to form another photoresist pattern 1 8 0 which exposes the drain region, covering all regions for the drain region 1 7 5 Ion implantation. In a preferred embodiment, the implanted conductive impurities are kun ions, and the energy and dose of the ion implantation are 20-60 ke V and 2E15-9E15 / cm1 2 (typically about 40 keV, And 5E15 / cm2). The invention has the following advantages:

I. The coupling ratio of the source to the floating gate is increased (because the empty area of the floating gate is reduced). Therefore, the electric field between the floating gate and the control gate is increased (for injecting electrons), as shown in arrow 10 of Figure 10. This will increase the programming speed by 0

1 I. Another advantage of the reduction of the empty area of the floating gate is that the F N tunneling energy barrier from the floating gate to the control gate is low, so that the erasing speed can be increased. In addition, the read test is performed after erasing. The small empty area of the floating gate will make the variability of the starting voltage V t of the floating gate small, which will reduce the variability when reading the current. Please compare the difference in Vt between the flash memory cell manufactured by the method of the present invention and the flash memory cell of the standard traditional process. Please refer to the eleventh figure. In the figure, reference numeral 2 0 is the average value of V t of three memory cells of the wafer of the flash memory cell manufactured by the method of the present invention implanted with heavy ion arsenic and implanted in the suspended gate, including 0.5 2 2, 0.5 2 1 and 2 0.5 0 0 and standard deviation 0. 0 1 6, 0 · 0 1 1 0 0 0 1 9 (length of each bar). The result of the standard process is that the standard deviations of the five memory cells are 0. 0 4 6, 514913. 5. Description of the invention (11) 0. 063, 0. 400. 052 and 0. 041 and the average Vt is 0.528 to 0. 5 9 1. Obviously, the traditional process shows that the average value of V t is quite unstable. I II. The thickness of the meso-crystalline silicon oxide layer (ie, the second oxide layer 130) will not increase, because the conductive impurity concentration of the floating gate increases, so the problem of slower erasing speed will not occur. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application. 514913 9L 5. January 01 π iii JXj Schematic description Schematic description Schematic description 0 The preferred embodiment of the present invention will be supplemented by the following description in the following explanatory text. Applying PT and quasi i to Riyi shows the cross-section view after rt B ion implantation after the position of the floating gate is defined by the traditional method. -Figure 2 of the Qin Institute shows a schematic cross-sectional view of the first oxidized stone layer formed by the first method using the traditional method of thermal oxidation process of Nanwen to swell the upper surface of the first compound layer. Figure 3 shows the cross-section schematic diagram of the control gate defined by the traditional method. Figure 4 shows the traditional method of manufacturing the flash memory cell to open the gate to complete the ion implantation of the source region and annealing to expand the source region, and then pair; and A schematic cross-sectional view of the planting. Figure 5 shows a schematic cross-sectional view of the position of the floating gate with a photoresist pattern. Figure 6 shows a position of the floating gate defined by the method of the present invention, and then P +, As and B are applied. + Cross-sectional view of three carrier ion implants. Fig. 7 shows that the first surface of the first compound 'factory 2 3¾ ¾ layer is raised above the first surface by applying a high-temperature thermal oxidation process using the method of the present invention. A schematic cross-sectional view that oxidizes the hair layer and diffuses lighter vegetative growth. Figure 8 shows a schematic cross-section view of the method for removing the nitrided layer by the method of the present invention.) Figure 9 shows the flash memory that is opened by the method of the present invention. Cell to control gate: formed A schematic view of the carrier surface. FIG. 10 is a schematic cross-sectional view of source implantation, annealing, and drain ion implantation in this order by the method of the present invention.

Page 16 514913 m Brief Description of Drawings Figure 11 shows the comparison of the start voltage and variability between the flash memory cell of the present invention and the traditional standard process. 8 gate oxide layer 1 5 silicon nitride layer, 15 A silicon nitride pattern layer gap 2 0 photoresist pattern 5 0 word line 1 0 5 semiconductor substrate 1 10 first polycrystalline silicon layer 1 15A silicon nitride pattern layer Gap chart number comparison table: 5 semiconductor substrate 1 0 first polycrystalline silicon layer 1 8 polycrystalline silicon layer sharp corner 2 5 first silicon oxide layer 7 0 source region 7 5 drain region 1 0 8 gate oxide layer 1 1 5 silicon nitride layer 1 2 0 photoresist pattern 1 1 8 polycrystalline silicon layer sharp corner 13 0 second oxide layer 1 6 0 photoresist pattern 1 7 0 source region 2 0 0 initial voltage distribution (invention 1 2 5 First silicon oxide layer 150 Word line 1 7 5 > and polar region 18 0 photoresist pattern 2 1 0 start voltage distribution (standard process

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Claims (1)

514913 VI. Application Patent Scope 1. A method for forming a flash memory cell to improve stylization and erasing speed, the method includes at least the following steps: Provide a semiconductor substrate, and the substrate has formed a gate oxide layer / first Polycrystalline silicon layer / first silicon nitride layer; coating a photoresist pattern on the first silicon nitride layer to define a floating gate; etching the first silicon nitride layer, using the photoresist pattern as a mask For exposing the first polycrystalline silicon layer; applying the first ion implantation, implanting n-type conductive impurities of light weight and weight to the exposed first polycrystalline silicon layer; applying the second time Ion implantation, implanting p-type conductive impurities into the semiconductor substrate for adjusting the initial voltage of the flash memory cell; removing the photoresist pattern; applying a high-temperature thermal oxidation process to oxidize the first A polycrystalline silicon layer using the first nitride layer as a mask for growing a first silicon oxide layer on the first compound silicon layer; removing the first silicon nitride layer; removing the first A polycrystalline silicon layer using the first silicon oxide layer as a mask for forming Floating gate structure; forming a second silicon oxide layer on a sidewall of the semiconductor substrate and the first polycrystalline silicon layer by a thermal oxidation method; depositing a second polycrystalline silicon layer on the second silicon oxide layer; lithography And etching technology to define the second polycrystalline silicon layer to form a word line; ion implantation of the source region with conductive impurities; Page 18 514913 6. The scope of the patent application is to apply an annealing process at a high temperature and oxygen-containing environment to promote the further lateral diffusion of conductive impurities in the source region into the semiconductor substrate under the suspended gate structure: The polar regions are ion implanted. 2. The method according to item 1 of the scope of patent application, wherein the implanted n-type conductive impurities of light weight and heavy weight are phosphorus ions and arsenic ions, respectively. 3. The method as described in the second item of the patent application, wherein the energy and dose when implanting ions in the first ion implantation mentioned above are about 10-5 0 ke V and .1E14-8E14 / cm2 04 For example, the method of the second item of the patent application, wherein the energy and dose of the arsenic ion implanted in the first ion implantation are about 10-50keV and lE14-8E14 / cm2, respectively. The method according to item 1, wherein the energy and dose to the P-type conductive ions in the second ion implantation described above are about 30 to 80 keV and 3E12 to 9E12 / cm2, respectively. 6. The method according to item 1 of the patent application, wherein the step of performing ion implantation on the source region with conductive impurities at least includes: forming a photoresist pattern exposing the source region on the second polycrystalline silicon layer The application of ion implantation technology to implant n-type conductive impurities; and Page 19 514913 6. Scope of patent application Remove the photoresist pattern. 7. The method according to item 1 of the scope of patent application, wherein the above-mentioned step of ion implanting the electrodeless region with conductive impurities at least includes: forming a photoresist pattern exposing the drain region on the second polycrystalline silicon layer Above; applying ion implantation technology to implant n-type conductive impurities; and removing the photoresist pattern. 8. For example, the method of item 1 of the scope of the patent application, wherein the above-mentioned thermal oxidation process is performed at South temperature to control the temperature when the first silicon oxide layer is grown at 800-100 000C. 9. The method according to item 1 of the scope of patent application, wherein the light-weight and heavy-type η-type conductive impurities implanted above are phosphorus ions and arsenic ions, respectively. 10. The method according to item 8 of the scope of patent application, wherein the above-mentioned high-temperature thermal oxidation process causes the phosphorus ions implanted into the polycrystalline silicon to laterally diffuse below the first silicon nitride layer pattern layer, and the arsenic ions There is almost no lateral expansion relative to phosphorus ions. 11. The method according to item 9 of the scope of patent application, wherein the above-mentioned arsenic ion non-lateral diffusion is to increase the concentration of the suspended gate so that the empty regions near the source region are reduced, and the thermal oxidation method can be prevented from forming a second region. The oxidation rate of the first polycrystalline silicon layer is oxidized into the second silicon oxide layer. Page 20 514913 6. Scope of patent application Fast 0 1 2. — Improved program The gate flash memory cell has conductive impurities that are characteristic of the body substrate. Opening gate of floating and erasing speed—suspended gate. One control is flash memory cells in the suspended gate at the same time. The divided gate is formed in half of the conductor and has two different qualities. Different amounts of conductive impurity species. 14. The memory cell of item n in the scope of the patent application, in which the above-mentioned heavy conductive impurities are denser in the center of the suspended gate than the lighter-weight conductive impurity f, which has a lighter-weight conductive property. The impurities are distributed on the suspended gate, so that the n-type conductive impurity concentration in the center of the suspended gate is higher than the edge of the suspended gate. 1 5 · A kind of flash memory cell with improved stylization and erasing speed. The flash memory cell has a floating gate and a control gate is formed on a semiconductor substrate. It is characterized by the floating gate There are two kinds of conductive impurities with different masses in the pole. Among them, the heavier conductive impurities are denser in the suspension = the center of the pole is significantly higher than the lighter conductive impurities, and the lighter conductive Impurities are distributed approximately evenly on the suspension gate, so that the concentration of the η-type conductive impurities trapped in the center of the suspension gate is higher than the suspension gate jHa ~~~~~~~~~~~~~~~~ ~~ ______ ___— _ Page 21 514913 6. The extreme edge of the scope of patent application is much higher. 16. The memory cell according to item 14 of the scope of patent application, wherein the above two kinds of conductive impurities having different qualities include at least one of phosphorus and arsenic or arsenic and antimony. Page 22