TW454249B - Manufacturing method to form lightly doped region and heavily doped region of source/drain on transistor simultaneously - Google Patents

Abstract

The present invention provides a manufacturing method to form a lightly doped region and a heavily doped region of source/drain on transistor simultaneously, which comprises the following steps: providing a semiconductor substrate, and forming a gate on the semiconductor substrate; forming a photoresist layer to cover the gate and the semiconductor substrate; proceeding exposure and developing process on part of the photoresist layer to form a photoresist layer with a specific thickness on the top and sidewall of the gate; and then implanting ions to the semiconductor substrate on both sides of the gate, so as to form a lightly doped region of source/drain on the semiconductor substrate under the photoresist layer, and forming a heavily doped region of source/drain on the semiconductor substrate without being covered by the photoresist layer.

Description

454g; 49 7 V. Description of the invention (1) Method '= species = doped volume circuit element manufacturing method doping = 卩 slight doping; ^ The number of thin parts is increasing, the development of circuits, the daily The smaller the element is, the longer the size of the MOS transistor will increase with the increase of the accumulation degree. The smaller the channel is, the smaller the channel is. When the transistor is : Faster operation of the transistor. However, the length of the household 6 in the channel is shortened. If the magnitude of the applied voltage is not Α β & & & only the σ electric field will increase ', which will cause the electrons in the channel to generate heat due to electricity. The number of carrier effects (hOt carrier * (eCt), with the example of a tritium crystal, the number of carrier arriers in the channel close to the drain region) will rise, and some of the electricity generated by the increase in the number of carriers will be trapped (trap ) The gate oxide layer (which is inside gate 〇xide and destroys it, thus affecting the performance of the device (perfommance). In order to suppress the thermal carrier effect due to the shortening of the channel, there is currently a widely used solution ', that is, Adding a set of domains with a lower level of doping than the original source / drain extremely near the source and dead pole of the original Mos transistor is called "lightly doped" "Drain" is abbreviated as LDD. Under the design with LDD, the size of the electric field will be lower than that of the M0S transistor without LDD δ and §1 *, thus reducing the hot carrier effect. However, because of this source containing LDD The fabrication of the drain / drain must go through two ion implantation steps' Therefore, the process of the transistor is complicated, and it takes more time to complete its manufacture, which affects its production rate.

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V. Description of the invention (2) The method is: the production of a conventional CMOS transistor with a source / drain containing LDD: stone ... to solve the problem "jin; please refer to Figure 18 for the Several field oxide layers F0x are formed on the P-plate 10 to isolate the active

Some active-area ions in the Shixi substrate 10 isolated by the oxidized layer FOX are formed in the “N well area 12”, and on the 10 area of the plate 12 of the well area and the P㈣ substrate i 〇 The surfaces are respectively shaped, which are all made of a closed oxide layer, such as stone dioxide ..., the free electrode P

Is: ^ metal broken compounds used to reduce the intermetallic pole resistance value, such as the following I, for example, please refer to the first, is formed in the gate structure GP, Gn two i L plate 1G, such as The one shown in the figure is in the N well area

A p-type lightly doped region p- is formed, and a p] I doped region N-. And an N-type light is formed in the P-type Shixi substrate 10

= 'According to the diagram in the first figure, the insulating sidewall layers i6p, i 6n are formed on the two interrogation structures GP and GK soil, and then the gate structures P, Gn and the insulating sidewall layers 6p v 6n For the mask, p-type and N-type ions are implanted into the N-well region 12 and the P-type stone substrate 10 respectively to form the inflammatory region Π as shown in Fig. 1) and the concentrated region. CMOS transistor with source / drain in P + and N + regions. However, the conventional CM0S transistor process with LDD as described above requires more time in its process steps due to the two-stage ion implantation; and in order to suppress the hot carrier effect, the formation of LDD is important. And indispensable. In view of this, the main object of the present invention is to provide a simultaneous formation

4 5 4 ^ 4 9 V. Description of the invention (3) The method of the extremely resistive / doped region and the doped region, which is blocked by the first resistance layer, and Wan Ling has the wrong reason. The lightly doped region of the thick transistor and the concentrated step η are used to form ions at the same time, which can further reduce the process steps, and can suppress the hot carrier effect. The source of the transistor / 极 极 之 淡 # is provided one by one-a method for simultaneously forming, including forming a H + ¥ bulk substrate on a manufacturing substrate of a + region (LDD) and a heavily doped region, and on the semiconductor substrate . Then cover this photoresist layer with this free electrode and semiconductor, so as to do it in between! Light and developing sound; 4 *, the wall forms a photoresistor with a special thickness ^ the bottom of the barrier = ions into the semiconductor substrate on both sides of the gate, in (LDd /, 廿 之 'conductor substrate A lightly doped region 1 / of the source / drain is formed, and a heavily doped region of the source / drain is formed in a semiconductor substrate that is not covered by the photoresist layer. The main purpose is to provide another method for simultaneously forming a & crystal source / drain lightly doped region (LDD) and a heavily doped region = 2 method, including the following steps: provide-a semiconductor substrate 'and A gate is formed on the earth guide plate; a photoresist layer is formed so as to cover the gate and the half-body substrate. Then a part of this photoresist layer is exposed to form a light with a specific thickness on the gate and the sidewall. Finally, ions are implanted into the semiconductor substrate on both sides of the gate to form a lightly doped region (LDD) of the source / drain in the semiconductor substrate below the photoresist layer, and the photoresist is not exposed to the photoresist. A heavily doped region of the source / drain is formed in the semiconductor substrate covered by the layer. The above object of the present invention, features, and advantages can be more easily

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': Such as; Wen Teju-preferred embodiment, 1 with the attached drawings' for a brief description of the drawings in detail: Figures 1A to 1D show a cross-sectional view of a conventional CMOS transistor with an ldd structure And FIGS. 2A to 2J show cross-sectional views of a process for simultaneously forming a lightly doped region (LDD) and a heavily doped region of a source / drain in accordance with the present invention. Explanation of symbols 1 〇 silicon substrate 1 3 silicon dioxide 1 5 tungsten silicide F 〇 X-field oxide layer 16ρ, 16η insulating sidewall layer 20 silicon substrate ^ 2 2 silicon dioxide 24 tungsten silicide

El, Ε2 Electron beam (E-beam) 29a, 29b opening Ml, M2 metal inspection Example 12 N-type well area

Gp, Gn gate structure P-, N- lightly doped region (LDD) P +, N + heavily doped region 21 N-type well region 2 3 polycrystalline broken 25, 25a, 27, 27a photoresist layer 2 6, 2 8 Notch 29, 30BPSG layer

Refer to the figure: a semiconductor substrate is provided, for example, a P-type element is formed on the soft substrate = a field gasification layer F0X for isolation is formed to protrude the substrate in the active areas a and B of the silicon substrate 20; Well process to form complementary metal-oxide semiconductors

Page 7 V. Description of the invention (5)-(Complementary Metal Oxide Semiconductor Transistor) 'referred to as CMOS transistor, so first in the p-type; a well region is formed in part of the active area B of the substrate 20', for example N Type well region 21, and a gate oxide layer such as a silicon dioxide layer 22, a gate electrode such as a polycrystalline silicon layer 23, and a gate oxide layer are sequentially formed on the surfaces of the P-type silicon substrate 20 and the N-type well region 21. Metallic oxide layers used to reduce gate resistance, such as Shixi Chemical Crane Layer 2 4. After that, a gate structure is to be formed on the surface of the semiconductor substrate; for example, according to the diagram in FIG. 2B, a pattern of the interelectrode structure is defined by using photolithography and etching; In this embodiment, the ^ (pole structure number is located above the N-type well region 21 is Gp 'and the gate structure number is located on the surface of the p-type silicon substrate 20 is Gn. ° The next step is Forming a photoresist layer to cover the free electrode and the semiconductor substrate; here, please refer to FIG. 2C first, coating—a layer of photoresist 25 on the surface of the silicon substrate 20, and its thickness About 10,000 ~ 12000 angstroms; next, the part of the photoresist layer is exposed and developed to form on the top side wall of the gate structure)-a photoresist layer with a specific thickness; 2: Figure (; = It uses the electron beam (E-beam) with intensity E2 in month b to scan the gate Gn and the photoresist layer 25 in the surrounding area, and the electron beam with an energy intensity of £ 1 to scan the gate ^ Gn and the photoresist layer 25 on the active area A other than the surrounding area to expose it, and light in the n-well area ^ The resist layer is not exposed; two points should be noted here. One is: the method of exposing the photoresist layer 25 can still be made by laser or X-ray scanning; the other 3 points Attention must be paid to all A § 44 3 Description of the invention ⑹ '^ " It is pill on E 2 5 ′ and E 2 is exposed to the thunder potential: which structure is the photoresist layer and range of A in the active area of ^ Due to the difference in intensity, the photoresist layer 25 is formed on the top and sides of the closed electrode structure after exposure and development processes to form a photoresist layer pR1 and a notch 26 as shown in FIG. 2D. Its thickness is between 300 and 400 angstroms; or its energy intensity is strengthened, so it exposes more on the top of the gate structure Gn and its sides, so it is formed after passing through the shirt. The photoresist layer shown in Fig. 2E? 1 ^ 2 and a notch 26 'have a thickness of about 100 ~ 500 Angstroms. Then, please refer to Figs. 2D and 2 £ at the same time: Use the photoresist layer 25a and PR1 (or PR2) are used as the curtain, and the ion concentration is implanted between! Xl015 and x1015 at 0ms / cm2 (the ion concentration is implanted into the silicon substrate 20, for example, arsenic ions; because Secco controls the thickness of the photoresist layer PR1 (or PR2), so it can be used when implanting ions. The photoresist layer PR1 (or PR2) will block the implanted ions. Therefore, the gate structure Gn In the p-type silicon substrates on the lower sides, a pair of lightly doped (ie, region N-) is formed under the photoresist layer PR1 (or 疋 PR2), and the photoresist layer PR1 (or A pair of heavily doped regions is formed in the silicon substrate 20 covered by pR2) to complete the source / drain structure. — = After that, apply another photoresist layer 27, as shown in FIG. 2F; then, perform the same steps as before, for example, refer to FIG. 2F, and first use two different energies E1 and E2 (eg (E-beam) irradiate a part of the photoresist above the N-type well area 21 to expose it, and then as shown in Figure 2G, after the development, a notch 28 is formed, and a photoresist layer that is not developed is developed. pR3 and the photoresist layer 27a located above the active area A, and then using the photoresist layer 27a and PR3 as a mask, an ion concentration between 1 X 1〇15 ~ 5 X i〇i5 atoms / cni2 is implanted from 4S4 ^ 4 9 V. Description of the invention (7) ^ ^ "The element" is, for example, boron ions into the silicon substrate 20, and a pair of lightly doped (ie, LDD) regions p- are formed below the photoresist layer pR3, and A pair of heavily doped regions p are formed in the notch M in the silicon substrate 20 not covered by the photoresist layer PR3 as the source / inverted regions. As in the aforementioned 'Figure 2G, the result of this photoresist layer 27 after exposure and development can form a photoresist layer PR4 with different conditions due to the difference in intensity of E1 and E2' as shown in Figure 2H 'if the energy intensity of E2 Higher, there is more exposure on the top and sides of the idle electrode structure Gp, so after development, PR4 is formed as shown in the figure. Finally, 'an insulating layer must be formed on the surface of these gates before the completion of the production of a CMOS transistor; in addition, if you want to make electrical contact with other components', the following steps are required; for example, please refer to Section 2 first [Figure, removing the photoresist layer 27a and PR3 to expose the gate structure Gp, Gn and the surface of the silicon substrate 20 (not shown); and then using a deposition and etching process on the silicon substrate 20 and the A first insulating layer ′ having two openings 29 a and 29 b is formed on the gate structures Gp and Gn. For example, the first insulating layer is a side phosphosilicate glass (BPSG) layer 29. The openings 29a and 29b are formed in the BPSG layer 29, and the surfaces of the silicon substrate 20, one of the source / inverter of the transistor to which Gp and Gn belong, are exposed, respectively. Next, please refer to FIG. 2j, deposit and etch back a metal layer, such as a polycrystalline stone layer (not labeled) on the surface of the BPSG layer 29, so as to form metal plugs and stations in the openings (29a, 29b). 2. Finally, a second insulating layer, such as a BPSG layer 30, is formed on the surface of the core% layer 29 to complete the manufacture of a semiconductor device. The present invention utilizes controlling the thickness of the photoresist layer to form a transistor source / Draw

Page 10: Show 9 _ ^ __ 5. Description of the invention (8) The combination of extremely lightly doped regions and heavily doped regions is completed in one step, which not only improves the two-stage ion implantation in the past to form LDD, It simplifies its manufacturing steps and reduces the time it takes to make components, which is in line with economic effects. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

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Claims (1)

4 5 4 or 4 9 ---_-_ ''. ~ Y Politics. ----- 1-88111583 As the April, the shirt and the moon win the year > 丨 Total sixteen, the scope of patent application " 1: | 简 允 1 · A method for simultaneously forming a lightly doped region and a heavily doped region of a source / drain of a transistor, including the following steps: A semiconductor substrate is provided, and a gate is formed on the semiconductor substrate Forming a photoresist layer to cover the gate and the semiconductor substrate; performing an exposure and development process on a part of the photoresist layer, wherein the exposure energy of the gate and the periphery is smaller than the exposure of the gate and surroundings Energy to form a photoresist layer with a specific thickness on the top and side walls of the gate; and implant ions into the semiconductor substrate on both sides of the gate to form in the semiconductor substrate below the photoresist layer A lightly doped region of the source / drain and a heavily doped region of the source / drain are formed in the semiconductor substrate not covered by the photoresist layer. 2. The method according to item 1 of the scope of patent application, wherein before forming the gate electrode, it further comprises forming a gate oxide layer on the surface of the semiconductor substrate. 3. The method according to item 1 of the scope of patent application, wherein the semiconductor substrate is a dream substrate. 4. The method according to item 2 of the scope of patent application, wherein the semiconductor substrate is a silicon substrate. 5. The method as described in item 1 of the scope of the patent application, wherein '' uses an electron beam of two energies to scan the layer and expose it. 6. The method according to item 1 of the scope of patent application, wherein the photoresist layer is scanned by using laser light of two energies to expose it. 4 5 4 ^ 4 9 Case No. 8811585 __ Amendment VI. Patent Application Range 7. The method described in item 1 of the patent application range, wherein X-rays of two energies are used to scan the photoresist layer so that Exposure. ', 8. The method according to item 1 of the scope of patent application, wherein the thickness of the photoresist layer is between about 10,000 and 20,000 angstroms. 9. The method according to item 1 of the scope of patent application, wherein the thickness of the photoresist layer having a specific thickness today is between about 3000 and 4000 angstroms. " '1 0. According to the method described in item 1 of the scope of patent application, the source / j: and the ion implantation energy in the semi-selective impurity region of the semiconductor substrate formed below the two sides of the electrode are approximately It is between 15 ~ 80KeV, and the concentration of ion implantation 3 is about 1 X 1015 ~ 5 X 105 atom / cm2. 'Another 11. A method for simultaneously forming a lightly doped region and a heavily doped region of a source / drain of a transistor, comprising the following steps: providing a semiconductor substrate, and forming a free electrode on the semiconductor substrate; forming a The photoresist layer covers the gate and the semiconductor substrate; and a part of the photoresist layer is exposed and developed. In the meaning, the light energy of the intermediate electrode and its surroundings is less than the exposure energy of the gate and its surroundings ^ ', Forming a photoresist layer with a specific thickness on the side wall of the gate; and implanting ions into the semiconductor substrate on both sides of the gate to form a source in the semiconductor substrate below the photoresist layer A lightly doped region of the / drain electrode, and a heavily doped region of the source / electrode in the semiconductor substrate not covered by the photoresist layer. 12. The method according to item 11 of the scope of patent application, wherein before forming the gate electrode, it further comprises forming a gate oxide layer on the semiconductor substrate. 4 b 4 Cook 4 y _Case No. 88115183_ Year Month Day Amend __ Sixth, the scope of patent application The surface of the board. 1 3. The method according to item 11 of the scope of patent application, wherein the semiconductor substrate is a dream substrate. 14. The method according to item 12 of the scope of patent application, wherein the semiconductor substrate is a chopped substrate. 15. The method according to item 11 of the scope of patent application, wherein the photoresist layer is scanned by an electron beam of two energies to expose it. 16. The method according to item 11 of the scope of patent application, wherein the photoresist layer is scanned with laser light of two energies to expose it. 1 7. The method according to item 11 of the scope of patent application, wherein the photoresist layer is scanned by X-rays of two energies to expose it. 1 8. The method according to item 11 of the scope of patent application, wherein the thickness of the photoresist layer is between about 100 and 200 angstroms. 19. The method according to item 11 of the scope of patent application, wherein the thickness of the photoresist layer with a specific thickness is about 100 to 50 angstroms. 20. The method according to item 11 of the scope of patent application, wherein the ion implantation energy of the lightly doped regions of the source / drain formed in the semiconductor substrate below the sides of the gate is about 15 ~ 80KeV. The ion implantation concentration is about 1 X 1 015 to 5 X 1 O15 a toms / cm2. 0503-4359TWF repair l.ptc Page 14