TW451301B - Method for forming under bump metal - Google Patents
Method for forming under bump metal Download PDFInfo
- Publication number
- TW451301B TW451301B TW89119756A TW89119756A TW451301B TW 451301 B TW451301 B TW 451301B TW 89119756 A TW89119756 A TW 89119756A TW 89119756 A TW89119756 A TW 89119756A TW 451301 B TW451301 B TW 451301B
- Authority
- TW
- Taiwan
- Prior art keywords
- photoresist
- forming
- patent application
- metal
- bump
- Prior art date
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 71
- 239000002184 metal Substances 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 56
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 66
- 239000004642 Polyimide Substances 0.000 claims abstract description 14
- 229920001721 polyimide Polymers 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910000679 solder Inorganic materials 0.000 claims abstract description 8
- 238000004544 sputter deposition Methods 0.000 claims abstract description 4
- 239000011248 coating agent Substances 0.000 claims abstract 3
- 238000000576 coating method Methods 0.000 claims abstract 3
- 239000010410 layer Substances 0.000 claims description 50
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 11
- 239000011241 protective layer Substances 0.000 claims description 10
- 238000005406 washing Methods 0.000 claims description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 238000001465 metallisation Methods 0.000 claims description 6
- 238000005507 spraying Methods 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 239000010408 film Substances 0.000 description 16
- 238000005516 engineering process Methods 0.000 description 7
- 239000000203 mixture Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002905 metal composite material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
4 5 13 0 V. 五、發明說明(1) 發明領域: 本發明與一種積體電路製程有關’特別是有關於一種 應用於形成凸塊製程(bumping process)中’凸塊下金屬 (under bump metal)圖案化之方法。 發明背景: 基於積體電路技術之快速進展,積體電路之線寬已經 可以達到次.微米之程度,在進入線寬小於0. 1 8微米之世代 時,各種製程之條件較以往更為嚴格。因此,在次微米技 術中製作有效之元件是一項充滿挑戰性之工作。在極大型 積體電路(ULSI)趨勢中’半導體元件的尺寸不斷地縮小, 用以不斷地提昇晶圓上元件之積集度。此外,隨著半導體 技術之快速演進’電子產品在輕薄短小、多功能速度快之 趨勢的推動下’1C半導體的輸入輸出(丨/0)數目不但越來 越多密度亦越來越南’使得封裝元件的引腳數亦隨之越來 越多’速度的要求亦越來越快,導致元件耗功率越來越 大’所以增進封裝之散熱效果,則曰趨重要。目前,封裝 也越做越小以符合目前之趨勢,而高數量ί/0之封裝也伴 隨球矩陣排列封裝技術之發展而有所突破,負責丨/0的引 腳為球狀’ sK號傳遞距離短且不易受損變形,其封裝元件 之電性的傳輸距離短速度快,可符合目前及未來數位系統 速度的需求。4 5 13 0 V. V. Description of the invention (1) Field of the invention: The present invention relates to an integrated circuit manufacturing process, and particularly relates to an under bump applied to a bumping process. metal) patterning method. Background of the Invention: Based on the rapid progress of integrated circuit technology, the line width of integrated circuits has reached the level of sub-micron. When entering the generation with line width less than 0.8 micron, the conditions of various processes are more stringent than in the past. . Therefore, making effective components in sub-micron technology is a challenging task. In the ultra-large-scale integrated circuit (ULSI) trend, the size of semiconductor components is continuously shrinking to continuously increase the accumulation of components on the wafer. In addition, with the rapid evolution of semiconductor technology, 'electronic products are driven by the trend of light, thin, short, and multi-functional speeds.' The number of input and output (丨 / 0) of 1C semiconductor is not only more and more dense but also more and more south. ' As the number of component pins increases, the speed requirements are getting faster and faster, which causes the components to consume more and more power. Therefore, it is important to improve the heat dissipation effect of the package. At present, the package is getting smaller and smaller to meet the current trend, and the high-quantity ί / 0 package has also made a breakthrough with the development of the ball matrix array packaging technology. The pin responsible for the 丨 0 is a ball'sK number. The distance is short and it is not easy to be damaged and deformed. The electrical transmission distance of the packaged components is short and fast, which can meet the current and future digital system speed requirements.
第6頁Page 6
此外 此技術是 凸塊的製 程姓刻護 組合層於 用微影製 墊上具有 接觸’然 凸塊作為 形成錫ώ ’覆晶封 利用導體 程中,通 層以暴露 其上,一 裎塗佈光 一開窗。 後去除光 蝕刻罩幕 塊製程。 裝(Hip ChiP)為新一代之封裝技術, ^作為輸人/輸出。對於形成導體锡 ^铭金屬焊塾(Pad)上,利用姓刻製 ¥塾再刀別形成阻障層與導電層之 般的组成包含c"cu、Tl/cu:m 阻且形成®#,形成的光阻圖案在銘焊 利用電鍵法形成錫於開窗之中與導電層 阻圖案形成錫凸塊。下一步驟為利用錫 去除未被遮住之阻障層與導電層,完成 屬,::^:技術為利用濺鍍及電鍍法製作凸塊下金 下金個各種不同…刻完成凸塊 屬,例如,對於刻溶液以利於钮刻不同之金 合溶液,&必須使用,,㉟刻配方使用硫酸銅、氣水之混 前技術之缺點 鼠酸溶液…,複雜之製程為先 發明目的及概述: 本發明之目的也 屬圖案化的方供一種在長&塊製程中’凸魂下金In addition, this technology is a process of engraving and engraving the combined layer on the bump. The contact has been formed on the lithographic pad. Then the bump is used to form a tin. Open the window. After removing the photo-etching mask block process. Hip ChiP is a new generation of packaging technology, which is used as input / output. For the formation of a conductive tin solder pad (Pad), the last name is engraved with the last name and then the barrier layer and the conductive layer are formed. The composition includes c " cu, Tl / cu: m resistance and formation ® #, The formed photoresist pattern forms tin bumps in the window opening with the conductive layer resist pattern in the soldering process by electric bonding method. The next step is to use tin to remove the unobstructed barrier layer and conductive layer, and complete the metallization :: ^: The technology is to use sputtering and electroplating to make a variety of gold and gold under the bumps. For example, for the engraving solution to facilitate the engraving of different metal solutions, & must be used, the engraving formula uses the disadvantages of the pre-mixed technology of copper sulfate, gas and water ... Summary: The purpose of the present invention is also a patterned square for a 'convex soul under gold in the long & block process.
第7頁 5 13 01 五、發明說明(3) 本發明之目的為控制顯影之參數,以形成具有底切結 構之乾式光阻溥膜(dry film resistor ;DFR),俾使在後 續沈硪金屬層過程中造成斷線。之後,藉由剝離乾式薄膜 光阻而定義凸塊下金屬層圖案。 本發明之方法包含提供一具有焊墊之基板,之後形成 一保護層以及聚醯亞胺於該保護層上,上述之聚醯亞胺具 有一開口,暴露出該焊墊。接著,形成一具有第一穿孔之 第一光阻,例如乾式薄膜光阻。上述之第一光阻包含底切 結構形成於第一穿孔之底侧。金屬層接著濺鍍於第一光阻 表面、焊墊表面以及被暴露之上述聚醯亞胺表面,其中上 述之底切結構造成該金屬沈積斷線。接著,剝離第一光阻 且一併去除其上之金屬層,因而定義出凸塊下金屬層圖 案。下一步驟為塗佈第二光阻,例如乾式薄膜光阻,且曝 光顯影第二光阻以形成一第二穿孔對應於凸塊下金屬層圖 案。之後,形成導電凸塊於第二穿孔之中,位於該凸塊下 金屬層圖案之上。去除第二光阻及熱流該導電凸塊。 發明詳細說明: 本發明提出在長凸塊製程(bumping process)中之凸 塊下金屬之形成方法,本方法之特徵為包含控制顯影技術Page 7 5 13 01 V. Description of the invention (3) The purpose of the present invention is to control the development parameters to form a dry film resistor (DFR) with an undercut structure, so that the metal will be deposited in the subsequent process. Broken wires during layering. Then, the pattern of the metal layer under the bump is defined by peeling off the dry film photoresist. The method of the present invention includes providing a substrate with a solder pad, and then forming a protective layer and polyimide on the protective layer. The aforementioned polyimide has an opening to expose the solder pad. Next, a first photoresist having a first perforation, such as a dry film photoresist, is formed. The above-mentioned first photoresist includes an undercut structure formed on the bottom side of the first perforation. The metal layer is then sputtered on the first photoresist surface, the pad surface, and the exposed polyimide surface, wherein the undercut structure described above causes the metal deposition to break. Then, the first photoresist is peeled off and the metal layer is removed therefrom, thereby defining the pattern of the metal layer under the bump. The next step is to apply a second photoresist, such as a dry film photoresist, and develop the second photoresist by exposure to form a second perforation corresponding to the pattern of the metal layer under the bump. Then, a conductive bump is formed in the second through hole, and is located on the pattern of the metal layer under the bump. Remove the second photoresist and heat flow the conductive bump. Detailed description of the invention: The present invention proposes a method for forming a metal under bumps in a long bumping process. The method is characterized in that it includes controlled development technology.
4 5 13 0 1 五、發明說明(4) 之參數,用以調變光阻之剖面形狀’俾使光阻材質具有底 切(under cut)形成。詳細說明如下’所述之較佳實施例 只做一說明非用以限定本發明。參閱圖一’在基板2上形 成金屬焊墊(pad) 4 ’ 一般利用含鋁材質做為上述之金屬 焊墊4。一護層6形成於基板2以及金屬焊墊4之上,上述之 護層6之組成可以包含P I或氮化矽。利用蝕刻製程蝕刻護 層6以暴露出導電焊墊4。再分別沈積沈積一聚醯亞胺 (polyimide)層8於所述之護層6之上,所述之聚酿亞胺 (po 1 y i m i de)層8經曝光顯影以形成穿孔用以暴露出導電焊 墊4,如圖一所示。之後,塗佈一乾式薄膜光阻(dry resistor ; DFR) 10 ’再利用光罩曝光顯影形成一穿孔12於 乾式薄膜光阻1 0之中。可以使用負或正光阻或特性相似之 材質,利用曝光與顯影步驟形成穿孔12 β本發明之特徵之 一為顯影之後,乾式薄膜光阻1〇之穿孔12底側具有底切 (under cut)之結構14。 光阻利之參數’以調變顯影後 圖,在不同揉办昧^閱圖七,其為顯影時間與線寬之關係 由圖令可見顧拄0所對應之顯影後剖面示之於圖七A, _ τ』見顯影時間D可以拟士、十Α ^ 與乾式薄琪光阻只做f 3 =同:本發明實施例之顯影時間 至圖九D為本發明利田/尤ώ明’非用以限定本發明。圖九A SEM圖,正g . 旱度為2· 1微米之負光阻實驗所得之 負先阻之物理化學機制為互補現象,以上雖以4 5 13 0 1 V. The parameter of the description of the invention (4) is used to adjust the cross-sectional shape of the photoresist ', so that the photoresist material has an under cut. The detailed description of the preferred embodiments described below is only for illustration and is not intended to limit the present invention. Referring to FIG. 1 ', a metal pad 4 is formed on the substrate 2. Generally, an aluminum-containing material is used as the metal pad 4 described above. A protective layer 6 is formed on the substrate 2 and the metal pad 4. The composition of the protective layer 6 may include PI or silicon nitride. The protective layer 6 is etched by an etching process to expose the conductive pads 4. Then, a polyimide layer 8 is deposited on top of the protective layer 6 respectively. The po 1 yimi de layer 8 is exposed and developed to form a perforation to expose the electrical conductivity. Welding pad 4, as shown in Figure 1. After that, a dry film photoresist (DFR) 10 ′ is applied and then exposed and developed with a photomask to form a perforation 12 in the dry film photoresist 10. You can use negative or positive photoresist or materials with similar characteristics to form perforations 12 using exposure and development steps. One of the features of the present invention is that after development, the perforations 12 of the dry film photoresist 10 have undercuts on the bottom side Structure 14. The parameter of the photoresistance is adjusted according to the development picture. Please refer to Fig. 7 for the difference between the development time and the line width. It can be seen from the drawing that the post-development section corresponding to Gu 拄 0 is shown in Fig. 7A. , _ Τ ”see development time D can be made up, ten A ^ and dry thin Qi photoresistor to do only f 3 = the same: the development time of the embodiment of the present invention to FIG. this invention. Figure IX A SEM image, positive g. The physicochemical mechanism of negative first resistance obtained from the negative photoresistance experiment with a dryness of 2.1 micrometers is a complementary phenomenon.
4 5 13 0 ti 五、發明說明(5) 標準顯影時間 11 0 %標準顯影時間 90 % 標準顯影時間 70 % 標準顯影時間 負光阻做一例子,然可應用於正光阻而得到相同之結果。 所使用之顯影時間與對應形成之底切如下: 底切深度3, 7微米 底切深度3. 7微米 底切深度3. 0微米 底切深度1 · 6 2微米 其物理機制可能為光子通過光罩之穿孔,基於光學效 應或底層表面反射,造成光阻邊緣底部之受光子照射(或 不又光子射依正負光阻而不同)所吸收不同之光子能 量,在邊緣底部吸收較多(或較少)之光子數目。因而產生 .與其它區域不同程度之化學變化。 另外可以利用控制曝光顯影製程中洗滌(rinse)參數 來調變光阻剖面之形狀或外觀。圖八所示為利用不同之洗 滌方法經過顯影後所得到之光阻剖面。剖面丨所示為利 用rubbing方法所得到之剖面結構,其對應之SEM示之於圖 八A。剖面2所示為利用高壓喷灑(high pressure⑼厂叼) 方法所得到之剖面結構’其對應之SEM示之於圖八b。剖面 3所示為利用shower(低壓喷灑)方法所得到之剖面結構, 其對應之SEM示之於圖八c。基於上述之結果明顯可知,利 用鬲壓噴灑(high pressure spray )方法之洗滌步驟,經 過顯影之後可以得到底切之光阻剖面。4 5 13 0 ti V. Description of the invention (5) Standard development time 110% Standard development time 90% Standard development time 70% Standard development time Negative photoresist is taken as an example, but it can be applied to positive photoresist to obtain the same result. The development time used and the corresponding undercuts are as follows: Undercut depth 3, 7 microns Undercut depth 3. 7 microns Undercut depth 3.0 microns Undercut depth 1 · 6 2 microns The physical mechanism may be that photons pass through the light The perforation of the cover is based on the optical effect or the surface reflection of the bottom layer, which causes the photon energy at the bottom of the photoresist edge (or the photon emission varies depending on the positive and negative photoresistances) to absorb different photon energy and absorb more (or Number of photons. As a result, different degrees of chemical changes than other areas. In addition, the shape or appearance of the photoresist profile can be adjusted by controlling the rinse parameters in the exposure and development process. Figure 8 shows the photoresist profile obtained after development using different washing methods. Section 丨 shows the section structure obtained by the rubbing method, and the corresponding SEM is shown in Figure 8A. Section 2 shows the cross-sectional structure 'obtained by the high pressure spraying method. The corresponding SEM is shown in Figure 8b. Section 3 shows the section structure obtained by the shower (low-pressure spraying) method, and the corresponding SEM is shown in Figure 8c. Based on the above results, it is clear that the undercut photoresistive profile can be obtained after developing using the washing step of the high pressure spray method.
第10頁 4 5 1 3 0 t 五、發明說明(6) 參閱圖二,然後以濺鍍方式沈積鈦、銅以及鎳材質之 複合層於上述顯影後光阻10之結構表面,做為凸塊下金屬 膜層16,上述之金屬層將做為凸塊下金屬,其組成亦可以 為其它適合之組成。上述之焊墊4以及被暴露之聚醯亞胺 (polyimide)層8表面也具有上述金屬複合層之沈積《值得 注意的是’由於乾式薄膜光阻10具有底切結構14,因此形 成一凸出部做為一阻障’造成在其投影下之聚醯亞胺 (polyimide)層8表面不具有凸塊下金屬膜層16之沈積。上 述之結果將凸塊下金屬膜層1 6造成斷線,以利於後續之製 程,亦是本發明之特徵。 參閱圖三’將上述之乾式薄膜光阻10去除,此舉將一 併去除位於乾式薄膜光阻10上之金屬層16,只殘留金屬層 16於焊墊之上4。因此,本發明不必利用調變各種不同之 蝕刻溶液去除凸塊下金屬,而將製程簡化。因此,凸塊下 金屬16沿著焊塾4以及聚醯亞胺(polyimide)層8穿孔之表 面。 接著,塗佈一光阻,例如乾式薄膜光阻1 8於上述結構 之上’再將其曝光顯影形成一穿孔對準於上述之凸塊下金 屬層18。在以網板印刷導電凸塊如錫凸塊20於上述之乾式 薄膜光阻18之穿孔中,如圖四所示。下一步驟,再將乾式 薄膜光阻18去除,留下錫凸塊2 0於凸塊下金屬層18之上。 接著’以錫凸塊20經過預烤(pre-bake)、以及熱流Page 10 4 5 1 3 0 t V. Description of the invention (6) Refer to Figure 2, and then deposit a composite layer of titanium, copper and nickel on the surface of the structure of the photoresist 10 after development by sputtering as a bump The lower metal film layer 16, the above metal layer will be used as the under bump metal, and its composition may also be other suitable composition. The above-mentioned pad 4 and the exposed polyimide layer 8 also have the above-mentioned metal composite layer deposited. "It is worth noting that because the dry film photoresist 10 has an undercut structure 14, it forms a protrusion. The part acts as a barrier, so that the surface of the polyimide layer 8 under its projection does not have the deposition of the metal film layer 16 under the bump. The above-mentioned result causes the metal film layer 16 under the bump to be disconnected to facilitate subsequent processes, which is also a feature of the present invention. Referring to FIG. 3 ', the above dry film photoresist 10 is removed. This will remove the metal layer 16 on the dry film photoresist 10 together, leaving only the metal layer 16 on the pad 4. Therefore, the present invention simplifies the manufacturing process by eliminating the need to use various etching solutions to remove the metal under the bump. Therefore, the under bump metal 16 is perforated along the welding pad 4 and the polyimide layer 8. Next, a photoresist is applied, such as a dry film photoresist 18 on the above structure, and then exposed and developed to form a perforation aligned with the metal layer 18 under the bump. In the screen printing of conductive vias, such as tin bumps 20, through the perforations of the dry film photoresistor 18 described above, as shown in FIG. In the next step, the dry film photoresist 18 is removed, leaving the tin bump 20 on the metal layer 18 under the bump. Then ’pre-bake the tin bump 20 and heat flow
;51301I; 51301I
狀結構完成錫 (ref low),將錫凸塊因内聚力等因素形成球 球22,如圖六所示。 本發明可以省卻調變各種不同之濕蝕刻溶液之步驟’ 利用底切結構造成金屬薄膜之斷線,只利用光阻剝離步驟 即可定義凸塊下金屬,簡化製程並節省製程之成本。 本發明以較佳實施例說明如上,而熟悉此領域技藝 者’在不脫離本發明之精神範圍内,當可作些許更動潤 掷’例如’依據本案之精神’可以提供—種形成金屬圖案 之方法’該方法包含提供一基板,該基板包含一底層形成 於其上,之後,形成一具有穿孔之光阻,光阻包含底切结 構形成於該穿扎之底側。接著’濺鍍金屬層於該光阻表面 以及被暴露之上述底層表面,其中上述之底切結構造成該 金屬沈積斷線。下一步為剝離光阻且一併去除其上之金屬X 層’因而定義出金屬圖案。其中上述之底切結構係利用控 制顯影該光阻之時間形成或以高壓喷灑之洗滌步驟完成。 其專利保護範圍更當視後附之申請專利範圍及其等同領域 而定。The fin-like structure completes the tin (ref low), and the tin bumps form a ball 22 due to factors such as cohesion, as shown in FIG. The present invention can omit the step of adjusting various wet etching solutions. The undercut structure is used to break the metal thin film. Only the photoresist stripping step can be used to define the metal under the bump, simplifying the process and saving the cost of the process. The present invention has been described above with reference to the preferred embodiments, and those skilled in the art can make some changes without departing from the scope of the spirit of the present invention. Method 'The method includes providing a substrate, the substrate including a bottom layer formed thereon, and then forming a photoresist having a perforation, the photoresist including an undercut structure formed on the punctured bottom side. Next, a metal layer is sputtered on the photoresist surface and the exposed bottom surface, wherein the undercut structure causes the metal deposition to be disconnected. The next step is to peel off the photoresist and also remove the metal X layer 'thereon to define a metal pattern. The undercut structure mentioned above is formed by controlling the time for developing the photoresist, or the washing step of spraying with high pressure is completed. The scope of patent protection depends on the scope of patent application and its equivalent fields.
第12頁Page 12
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW89119756A TW451301B (en) | 2000-09-25 | 2000-09-25 | Method for forming under bump metal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW89119756A TW451301B (en) | 2000-09-25 | 2000-09-25 | Method for forming under bump metal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW451301B true TW451301B (en) | 2001-08-21 |
Family
ID=21661307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW89119756A TW451301B (en) | 2000-09-25 | 2000-09-25 | Method for forming under bump metal |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TW451301B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8563336B2 (en) | 2008-12-23 | 2013-10-22 | International Business Machines Corporation | Method for forming thin film resistor and terminal bond pad simultaneously |
-
2000
- 2000-09-25 TW TW89119756A patent/TW451301B/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8563336B2 (en) | 2008-12-23 | 2013-10-22 | International Business Machines Corporation | Method for forming thin film resistor and terminal bond pad simultaneously |
| US9287345B2 (en) | 2008-12-23 | 2016-03-15 | Globalfoundries Inc. | Semiconductor structure with thin film resistor and terminal bond pad |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW445554B (en) | Flip chip bump bonding | |
| TWI345281B (en) | Methods and systems for advanced solder bumping | |
| TWI284947B (en) | Method of wafer level package using elastomeric electroplating mask | |
| US5492863A (en) | Method for forming conductive bumps on a semiconductor device | |
| CN101981655B (en) | Method for making line/space wiring between C4 pads | |
| JP3096061B2 (en) | Manufacturing method of microbump for flip chip mounting | |
| JPH05218043A (en) | Formation method of metal contact pad and formation method of metal contact terminal | |
| CN101882596B (en) | Method for etching metal layer | |
| JP2006245289A (en) | Semiconductor device and packaging structure | |
| US6808643B2 (en) | Hybrid interconnect substrate and method of manufacture thereof | |
| TW451301B (en) | Method for forming under bump metal | |
| KR100925669B1 (en) | Solder-on-Pad Manufacturing Method by Coreless Package Substrate Manufacturing Method | |
| TW577158B (en) | Method for forming UBM pads and bumps on wafer | |
| TW591782B (en) | Formation method for conductive bump | |
| CN113811091A (en) | Through-hole metallization method of fine ceramic circuit board | |
| TW200809994A (en) | Wafer level semiconductor chip packages and methods of making the same | |
| JP5101074B2 (en) | How to make electronic interconnects | |
| TWI247369B (en) | Forming method of conductive bump | |
| JP2004103605A (en) | Method of forming fine wiring | |
| TW444258B (en) | Manufacturing method of printed bump on semiconductor wafer or substrate | |
| TW464962B (en) | Method of planarization in bumping process | |
| TW493223B (en) | Solder bump rework manufacture method of flip chip package | |
| CN101894767A (en) | Manufacturing method of under bump metallization layer | |
| KR100417126B1 (en) | Fabrication method of interconnection bump with high density and high aspect ratio | |
| JP2005129665A (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MK4A | Expiration of patent term of an invention patent |