4 經濟部智慧財產局員工消黄合作社印製 §t295 A7 ___B7 五、發明説明（丨） 技術領域： 本發明係關於一種在積體電路(1C)之微影製程中對準標 記(Alignment Mark)的製作及校準方式，特別是解決嗓光機 台之系統校準的問題。 發明背景： 微影(Photolithography)在整個積體電路(IC)製程中是相 當關鍵的步驟之一，凡積體電路元件的結構，如各層薄膜之 圖案(Pattern)及雜質(Dopants)的區域，係由微影這個步驟來 決定的。其利用微影的技術將所設計之電路佈局圖案透過光 罩(Mask) ’ 經曝光(Expose)而傳遞(Transfer)到晶元(Wafer) 上。關於微影製程的步驟’其主要由光阻覆蓋(Coating)，曝 光及顯影(Development)三個基本步驟所構成的。首先在晶片 表面上覆上一層感光材料(Photo-Sensitive Material)，即光阻 (Photo Resist) ’來自光源的平行光經過光罩之後，便打在光 阻上。因為光罩上有路金屬形成之電路圖案，使得通過羌罩 之光束也具相同之圖形，而光源得以對光阻進行選擇性 (Selective)感光，因此光罩上的圖案便完整的傳遞到光阻上。 曝光之後再經過顯影，光阻上就會得到與光罩上完全相同的 電路佈局圖案。 由於不良的爆光解析度(Resolution)會使製程的精密程 度受限，為了提昇曝光的解析度，新一代的曝光技術都採用 重複且步進(Repeat and Step)或掃描且步進(Scan and Step)的 方式進行。其方法皆是使用投射(Projection)的方式來做對準 (Alignment)。其中採取掃描且步進投射方式的機台係在光罩 本紙張尺度遑用中困困家揉準（CNS ) A4规格（210X297公釐） {請先閲讀背面之注項再填寫本頁〕4 Printed by the Yellow Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs §t295 A7 ___B7 V. Description of the Invention (丨) Technical Field: The present invention relates to an alignment mark in the lithography process of integrated circuit (1C). Production and calibration methods, especially to solve the problem of system calibration of the voice machine. Background of the Invention: Photolithography is one of the most critical steps in the entire integrated circuit (IC) manufacturing process. For the structure of integrated circuit components, such as the pattern of various layers of films and regions of impurities, It is determined by this step of lithography. It uses lithography technology to transfer the designed circuit layout pattern to the wafer through the mask ′ and expose it. Regarding the steps of the lithography process, it is mainly composed of three basic steps: photoresist coating (coating), exposure and development (development). First, the surface of the wafer is covered with a layer of Photo-Sensitive Material, that is, Photo Resist. After the parallel light from the light source passes through the mask, it hits the photoresist. Because the mask has a circuit pattern made of metal on the mask, the beam passing through the mask also has the same pattern, and the light source can selectively select the photoresist, so the pattern on the mask is completely transmitted to the light. Resist. After exposure and development, the photoresist will have the same circuit layout pattern as the photomask. Due to poor exposure resolution (Resolution), the precision of the process is limited. In order to improve the exposure resolution, the new generation of exposure technology uses Repeat and Step or Scan and Step ). The methods are to use Projection for alignment. Among them, the machine adopting scanning and step projection method is attached to the photomask. This paper is difficult to use in the standard paper (CNS) A4 specification (210X297 mm) {Please read the note on the back before filling this page]
-、5J .9. 451295 A7 ---------- —____B7 五、發明説明（V) (請先閱讀背面之注意事項再填寫本頁) 及晶片之間加入一鏡面之組合，利用鏡面反射將光罩上之圖 案轉移到晶片上。執行此動作之機台即稱作夕掃瞄機 (Scanner广。另一採取重複且步進投射方式之機台係將光罩 上的圖案放大’利用透鏡(Lens)圖罩上的圖案依適當的比 例縮小(通常為10 ·· 1或5 :再投射，遂採取分區曝光之 方式，分為數十次來曝光，才能將整片晶片的曝光步驟執行 完成’而執行此動作的曝光機就稱為、步進機(Stepper)，。 由於在電路佈局中有許多不同的層次(Layer)，每一層次皆有 其代表物理及電性上的意義，在複數次曝光的過程中，普遍 係利用對準標記(Alignment Mark)將不同層次的電路囷案校 準連接起來’才使得每一層的電路佈局圊案都能準確無誤地 曝光在所設計的位置上’亦即晶片之產生過程是以層層疊對 (Overlay)的方式來完成的。為了使製程的精密程度能夠達到 品質要求標準，因此在疊對的過程中必須確保當層次與前層 次的對準值是在一可允許的規格内，如此才能確保產品&高 品質。 經濟部智慧財產局員工消費合作社印製 而在以對準標記為依據，定義出各層次的電路圖案之 前’曝光機機台亦需對準標記本身做校準的動作，才能確保 對準標記的準轉度。在爆光時因需求而使用不同之曝光機， 為確保步進機(或掃描機)的準確度良好及透鏡之使用達到最 大之效果’曝光機間遂利用晶片上之對準標記做校準，再對 機台之系統作適當的調整《•微影技術中曝光機進行對準標記 之校準步驟的流程，係先在晶片的表面上覆上一廣厚度適當 之光阻’經過一道軟烤(Soft Bake)的程序，主要係將光阻内 本紙張纽逋用中鬮國家橾準（CNS )八4胁d〇X2937公釐） ~ ' —-- 451295 A7 B7 五、發明説明（> ) 經濟部智慧財產局興工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) ,ΤΓ 殘餘的溶劑加熱蒸發以去除；接著進行曝光的步驟，來自光 源的平行光經過光罩上放大的第零層對準標記圖案，再經過 透鏡的縮小，第零層的對準標記圖案即傳遞到光阻上；待傳 送完畢後，進行曝光後烘烤(Post Exposure Bake，PEB);接 著進行顯影，以將軟化之光阻去除；再以硬烤(Hard Bake)移 除殘餘的顯影液(Developer)或清洗液；最後進行蝕刻 (Etching) ’去除在顯影後沒有被光阻覆蓋及保護的部份基板 (Substrate) ’去除光阻之後，就在晶片上得到第零層之對準 標記。接著再寫入第一層的對準標記，步驟與第零層同；光 阻覆蓋，使用第一層對準標記圖案之專屬光罩，位置確定之 後，進行曝光、曝光後烘烤、顯影、硬烤、蝕刻及去光阻等 步驟，在晶片上完成第一層之對準標記。接著以另一機台(子 機台)製作第二層之對準圖案’請參相―，制知微I 術中進行第二層對準標記之製作及校準步驟的流程囷。^始 與前述製程相同，覆蓋一層光阻100、軟烤、曝上第二^ ° 準標記110、曝光後烘烤及顯影120但不進行蝕刻，^二對 對準標記只製作在光阻上。最後量測第一層:層 記的位置uo，做較準度之計算，其誤差公奴義如T標 疊對誤差(Overlay Error)=(2m - 2e)〜(1 m 一 丨 e) · =(2m-lm)-(2r-ir) 2m :所測得第二層對準標記的位置 :所測得第一層對準標記的位置 2e ••所預測第二層對準標記的位置 le :所預測第一層對準標記的位置-、 5J .9. 451295 A7 ---------- —____ B7 V. Description of Invention (V) (Please read the notes on the back before filling this page) and add a mirror combination between the chip, The pattern on the photomask is transferred to the wafer using specular reflection. The machine that performs this action is called a night scanner (Scanner wide. Another machine that uses a repeating and step projection method is to enlarge the pattern on the photomask. 'Use the pattern on the lens (Lens) mask as appropriate. The ratio is reduced (usually 10 ·· 1 or 5: re-projection, then divided exposure method, divided into dozens of exposures, in order to complete the exposure step of the entire wafer ', and the exposure machine that performs this action It is called Stepper. As there are many different layers in the circuit layout, each layer has its physical and electrical significance. In the process of multiple exposures, it is generally related to Alignment marks are used to connect the calibration of circuit schemes at different levels, so that the circuit layout project of each layer can be accurately and accurately exposed at the designed position. That is, the generation process of the chip is layer by layer. Overlay is done in order to ensure that the precision of the process can meet the quality requirements. Therefore, in the process of overlapping, it must be ensured that the alignment value of the level and the previous level is within an allowable rule. In order to ensure the high quality of the product, it is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and before the alignment mark is used to define the circuit pattern of each level, the exposure machine must also be aligned with the mark itself. The calibration action can ensure the accurate rotation of the alignment mark. When exposure is required, different exposure machines are used. To ensure the accuracy of the stepper (or scanner) and the use of the lens to achieve the maximum effect 'exposure The machine room then uses the alignment marks on the wafer for calibration, and then makes appropriate adjustments to the system of the machine. “• The process of the alignment steps for the exposure marks in the lithography technology by the exposure machine is first covered on the surface of the wafer. A wide thickness of appropriate photoresist 'After a soft bake process, the main use of the photoresist is to use the paper in the photoresist of the National Standards of China (CNS) (4 × 2937 mm) ~' — -451295 A7 B7 V. Description of the invention (>) Printed by the Industrial and Commercial Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page), the residual solvent will be evaporated by heating to remove; In the exposure step, the parallel light from the light source passes through the zero-level alignment mark pattern enlarged on the reticle, and then is reduced by the lens, and the zero-level alignment mark pattern is transferred to the photoresist. Post Exposure Bake (PEB) is performed; then development is performed to remove the softened photoresist; hard Bake is used to remove the remaining developer or cleaning solution; and finally etching ( Etching) 'Remove part of the substrate that is not covered and protected by photoresist after development' After removing the photoresist, an alignment mark of the zeroth layer is obtained on the wafer. Then write the alignment mark of the first layer, the steps are the same as the zero layer; photoresist cover, use the exclusive mask of the first layer alignment mark pattern, after the position is determined, perform exposure, post-exposure baking, development, The steps of hard baking, etching and photoresist removal complete the first layer of alignment marks on the wafer. Then use another machine (slave machine) to make the second layer of alignment pattern ', please refer to the process of making the second layer of alignment marks in the micro I operation. ^ It is the same as the previous process, covering a layer of photoresist 100, soft baking, and exposure to the second ^ ° quasi mark 110, post-exposure baking and development 120 but without etching, ^ two pairs of alignment marks are only made on the photoresist . Finally, measure the first layer: the position of the layer record, and calculate the accuracy. The error publicity is like the T label overlay error (Overlay Error) = (2m-2e) ~ (1m-丨 e) · = (2m-lm)-(2r-ir) 2m: Measured position of the second layer alignment mark: Measured position of the first layer alignment mark 2e •• Predicted position of the second layer alignment mark le: the predicted position of the first layer alignment mark
U'· 4 i 2 9g 五、發明説明（ A7 B7 經濟部智慧財废局員工消費合作社印製 2r:第二層對準標記的資料 lr:第一層對準標記的資料 依所計算出的養對誤差，對步進機(或掃描 統及透鏡裝置做必紅適當_整14G。縣齡統就2 後，接著才以對準標記為依據，定義出各層次的電路佈 案，微影之步驟於焉完成。 對準檢查實是執行曝光步驟相當重要的關鍵步辣，所以 對準記號對準之準確度就格外重要。而料校準的因素除了 包括-些機纟與機纟間的轉性及機纟本㈣精準度問題之 外’另-影響之因素即為光阻’光阻的種類與厚度亦會造成 誤差。在製作第二層之對準標記時，係以第零廣及第一層之 對準標記為對準依據’錢過第二層對準標記專屬光罩之光 源，通過光阻而到達晶片上的第零層及第一層對準標記進行 對準時’因雜_素，會料確度產生料，並未測得第 零層及第-層對準標記之確實位置，而餅第三層對準標記 沒有製作在所設計的位置上，造成誤差。 發明概述： 本發明之主要目的為提供一種解決微影製程中曝光機之 校準誤差問題的方法，定義出對準標記之正確位置。 本發明係揭露一種解決微影製程中曝光機之校準問題的 方法。本發明中之曝光機進行對準標記校準步琢的流程，開 始時舆習知微影技綱，係先在半賴以表面上旋塗上— 層光阻’進行一道軟烤的手續；接著曝光機台(母機台)之先 源經過光罩上放大的第零層對準標記，再經過透鏡的縮小而 衣纸承ΛΑ適用tHH家樑準（CNS )八4祕（210X2^7公釐 (請先W讀背面之注項再填寫本頁} -、π •V· .m βϋ 451295 A7 B7 五、發明説明（/) (請先W讀背面之注意事項再填寫本頁) 傳遞到光阻上’之後做曝光後烘烤；而後再作顯影、硬烤及 蚀刻等步驟；接著亦在母機台製作第一層之對準標記，其步 称完全與製作第零層之對準標記相同。待定義完第零層及第 一廣之對準標記層後’開始於另一曝光機(子機台)製作第二 層之對準標記;在覆蓋上適當之光阻後，另利用一特製光罩， 於上述之光阻曝光’再顯影去除第零層對準標記及第一層對 準標記上方之光阻’但不做硬烤之處理；接下才進行習知之 技術’利用第二層對準標記之專屬光罩，以前兩層之對準標 記為依據進行對準，而進行曝光、曝光後烘烤，而後進行顯 影、硬烤等步驟，在晶片上定義出第二層之對準標記。之後 再量測第一層及第二層對準標記的位置，計算出疊對誤差 度，接著再對子曝光機台之對準系統及透鏡裝置作調整至與 母機台之狀態相同。 經濟部智慧財產局員工消費合作社印製 本發明與習知技藝不同的是，在定義出第一層對準標記 之後’再覆蓋上曝光第二層所需之光阻，直接利用一特叙光 罩進行曝光’再顯影去除因曝光軟化之光阻，之後再定義第 二層的對準標記》以特製光罩對第二層光阻先做一道曝光、 顯影的目的在於去除第零層對準標記及第一層對準標記上方 的光阻’使得之後在做第二層對準標記時，光源便可直接對 到晶片表面之第零層及第一層對準標記而進行對準，而計算 出疊對結果之誤差’鹿不會因光阻的存在或光阻厚度的改變 等因素，而造成對準之誤差，在此步琢中先對第二層光阻顯 影之後’並不接續做硬烤的原因’是為了還要接著做第二層 對準標記曝光之用。 ,-:--6----- 一 s /- α X. 3 \ * < λ 雉濟部智慧財產局員工消费合作社印製 4 5 1 29 5 a? 説明 u) ~ ~~ ~~~ 簡要的圖示說明： 圖一係習知微影技術中進行第二層對準標記之製作及校準 驟的流程圖。 ^ 圖二係本發明中進行第二層對準標記之製作及校準步驟的流 程圖。 作 圖三係本發明中以特製 '光罩進行微影後之立體示意圖。 圖號說明： 10-半導體晶片 15-光阻 20-第零層對準標記 25-第一層對準標記 30-無光阻覆蓋之區域 發明之詳細說明： 在製作積體電路元件時，每一晶片從開始的設計製作到 最後的晶背研磨之成品，需經過十幾道至二十幾道的微影製 程步驟’其中需經過數十次的重複曝光手績，才能完成会個 晶片所需之曝光。曝光時係將具有不同電路與物性之各個層 次的電路圖案’以層層要對的方式連接起來。如此在任一層 级之對準過程令，皆需確保當層次與前層次之精密度良好， 方能控制產品的品質的良率與可靠性。於是在進行電路圖案 之佈局設計時，係加入複數個對準標記(Alignment Mark)作 為依據，以利進行各層級電路圖案之校準。 本發明係揭露一種解決微影製程中曝光機系統之校準問 題的方法，使步進機(或掃描機)在做對準標記之校正時，可 減少對準結果之誤差《本發明除適用於各形式之步進機外， 本紙張尺度適用令國國家標準（CNS ) A4规格（2丨0X297公釐） (請先聞讀背面之注#tlh項再填寫本頁〕 . -9. 45 1295 A7 _ B7 五、發明説明（7) :— 亦適用於各種積體電路產品之微影製程β 本發明的趋是德織程巾定料—層對準標記及第 二層對準標記之間，歸用—特製光罩進行祕、顯影—的步 —’使其能齡®紐的存在或光阻厚度⑽變所造成的對 準誤差。本發财之曝光機進行鮮觀餅及校準步驟的 流程’開始與習知微影製程相同，先旋塗—層適當之光阻於 半導艘晶片表面上’進行一道軟烤；接著在曝光機台(母機 台)上曝光，光源經過光罩上的第零層對準標記之圖案，再 傳遞到光阻上，之後做曝光後供烤；而後再作顯影、硬烤、 蝕刻及去光阻的步驟；接著再以相同之步驟在母機台上定義 出第一層對準標記。而在第零層及第一層對準標記皆製作完 之後’接著在另一曝光機台(子機台)定義第二層對準標記。 請參考圖二及圖三，圖二係本發明中進行第二層對準標記之 製作及校準步驟的流程圖，而圖三係本發明中以特製光單進 行微影後之立體示意圖β本發明的重點在於在晶片10丄覆 蓋一層適當厚度之光阻15，進行軟烤，另以一特製光罩， 進行微影批’肚紅細15断姑_，再顯影去 除軟化的光阻l〇〇b，即移除第零層對準標記2〇 (圖三中的 十字符號)及第一層對準標記25 (圖三中的十字符號)上方的 光阻;但不接續做硬烤之處理，因還要製作第二層對準標記； 接下才進行習知之技掛，利用第二層對準標記之專屬光單， 以第零層對準標記20及第一層對準標記25為依據進行對 準’曝光上第二層對準標記圖案110，而後進行曝光後烘烤' 顯影120、硬烤的步驟’在晶片上定義出第二層之對準標記。 尽紙根人及通用〒网两冢揉準（CNS ) A4规格（210x297公羡) (請先閎積背面之注意事項再填寫本頁) 訂 經濟部智慧財產局貝工消費合作社印製 451295 Α7 Β7 五、發明説明（t 經濟部智慧财產局ιβ;工消費合作社印製 之後再量測第一層及第二層對準標記的位置13〇，利用公式 計算出疊對誤差。再根據所計算出之誤差，將子機红之對準 系統及透鏡裝置做適當且必要的調整140，直至操作狀態盘 母機台系統相同。本發明所述微影製程中曝光機之斜車糸 校正及透鏡功能之充分利用於焉完成。 ' 在還未做第一層對準標記的曝光之前，以特製光罩對已 曝上第二層之光阻先做一道曝光、顯影的目的，在於去除第 零層對準標記及第一層對準標記上方的光阻。使得之後在定 義第二層對準標記時’可直接對晶片表面無光阻覆蓋之區域 30的第零層對準標記及第一層對準標記進行對準，而計算 出疊對結果之誤差，不會有受光阻之種類與厚度的影馨，而 考虚盘芽·之誤差；而在此步驟中先對上述之光阻顯影之後， 並不接著做硬烤的原因，是為了還要接著做第二層對準標記 之曝光。 利用本發明的對準標記校正方法，可獲得最佳之對_結 果，再依a十算出之誤差，對曝光機系統作適當之調整’便可 使機台處於最佳之狀態。也因此提供之後每次曝光之電路佈 局囷案的準確位置，而得到最好曝光結果之晶片品質。 以上所述係利用較佳之實施例來詳細說明本發明，而本 發明涵蓋之範圍並不限於其所示之實施例，而且熟知半導體 技藝的人士皆能明瞭，適當而作些微之改變及調整，仍將不 失本發明之要義所在，亦不脫離本發明之精神與範圍β 本紙張尺度通用宁躅國家揉準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意ί項再填寫未頁) 9. I I nU '· 4 i 2 9g V. Description of the invention (A7 B7 Printed by the Consumer Cooperatives of the Ministry of Economic Affairs, Smart Finance and Waste Bureau 2r: Information on the second layer of alignment marks lr: Information on the first layer of alignment marks calculated To support the error, the stepper (or the scanning system and the lens device must be red and appropriate _ whole 14G. After the county age system is 2, then the alignment mark is used as the basis to define the circuit layout of each level, lithography The steps are completed in 焉. Alignment check is a very important key step in performing the exposure step, so the accuracy of the alignment mark alignment is particularly important. The factors of material calibration include- In addition to the problem of conversion and machine accuracy, the 'other-influencing factor is the photoresist'. The type and thickness of the photoresist will also cause errors. When making the alignment mark of the second layer, The alignment mark of the first layer and the alignment mark of the first layer are based on 'the light source of the exclusive mask of the second layer of alignment marks passes through the photoresist to reach the zeroth layer of the wafer and the first layer of alignment marks are aligned' due to Miscellaneous elements, which can produce materials with certainty, and have not measured the zeroth layer and the first layer pair The exact position of the quasi-marker, and the third-layer alignment mark of the cake is not made at the designed position, causing errors. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a method for solving the problem of the calibration error of the exposure machine in the lithography process. The correct position of the alignment mark is defined. The present invention discloses a method for solving the problem of the alignment of the exposure machine in the lithography process. The exposure machine in the present invention performs the process of the alignment mark calibration step. The film technology outline is to first spin-coat a layer of photoresist on the semi-reliable surface to perform a soft baking process; then the source of the exposure machine (master machine) passes the enlarged zero-level alignment mark on the photomask. , And then through the reduction of the lens, the paper and paper bearing ΛΑ is suitable for tHH Jialiang Zhun (CNS) 8 4 secrets (210X2 ^ 7 mm (please read the note on the back before filling out this page})-, π • V · .m βϋ 451295 A7 B7 V. Description of the invention (/) (Please read the precautions on the back before filling in this page) Pass it on the photoresist and then bake after exposure; then perform the steps of development, hard baking and etching; Then also made the first layer on the master machine. The quasi-marker is exactly the same as the alignment mark of the zero layer. After defining the alignment mark layer of the zero layer and the first wide, 'start to produce the second layer with another exposure machine (sub-machine)' After the appropriate photoresist is covered, a special photomask is used to expose the photoresist as described above. 'Re-development removes the zero layer alignment mark and the photoresist above the first layer alignment mark'. No hard roasting is performed; the conventional technique is used next. 'Using the exclusive mask of the second layer of alignment marks, the alignment marks of the previous two layers are used for alignment, and exposure, post-exposure baking, and then Perform development, hard baking and other steps to define the alignment marks of the second layer on the wafer. Then measure the positions of the alignment marks of the first layer and the second layer, calculate the stacking error, and then expose the sub. The alignment system and lens device of the machine are adjusted to the same state as the mother machine. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the present invention is different from the conventional technique. After the first layer of alignment marks are defined, the photoresist required to expose the second layer is covered, and a special light is used directly. The mask is exposed, and then developed to remove the photoresist due to exposure softening, and then the second layer of alignment marks is defined. "A special mask is used to make an exposure to the second layer of photoresist. The purpose of development is to remove the zero layer alignment. The photoresist above the mark and the first layer of alignment marks allows the light source to directly align the zeroth layer and the first layer of alignment marks on the wafer surface when making the second layer of alignment marks, and Calculate the error of the overlapping result 'The deer will not cause the alignment error due to the existence of the photoresist or the change in the thickness of the photoresist, etc. In this step, the second layer of photoresist is developed first' and is not continued. The reason for the hard roast is to use it for the second layer of alignment mark exposure. ,-:-6 ----- One s /-α X. 3 \ * < λ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 5 1 29 5 a? Description u) ~ ~~ ~~ ~ Brief illustration: Figure 1 is a flowchart of the steps of making and aligning the second layer of alignment marks in the conventional lithography technology. ^ Figure 2 is a flowchart of the steps of making and aligning the second layer of alignment marks in the present invention. Drawing 3 is a three-dimensional schematic diagram of the present invention after lithography using a special mask. Description of drawing number: 10-semiconductor wafer 15-photoresist 20-zero-layer alignment mark 25-first layer alignment mark 30-area without photoresist coverage Detailed description of the invention: When manufacturing integrated circuit components, each From the beginning of the design and production of a wafer to the final polishing of the back of the wafer, it needs to go through more than ten to two dozen lithography process steps. Among them, it takes dozens of repeated exposures to complete the wafer. Required exposure. At the time of the exposure, the circuit patterns' of each layer having different circuits and physical properties are connected in a layer-by-layer manner. In this way, the alignment process at any level must ensure that the precision of the current level and the previous level is good, so as to control the yield and reliability of product quality. Therefore, when designing the layout of the circuit pattern, a plurality of alignment marks are added as a basis to facilitate the calibration of the circuit pattern at each level. The invention discloses a method for solving the calibration problem of the exposure machine system in the lithography process, so that the stepper (or scanner) can reduce the error of the alignment result when the alignment mark is calibrated. In addition to stepping machines of various forms, this paper size applies the national standard (CNS) A4 specification (2 丨 0X297 mm) (please read the note #tlh on the back before filling this page]. -9. 45 1295 A7 _ B7 V. Description of the invention (7):-It is also applicable to the lithography process of various integrated circuit products β The trend of the present invention is the weaving of tissue towels-between the layer alignment mark and the second layer alignment mark , Using a special mask to perform the secret and development steps—'alignment errors caused by the presence of its energy age ® button or the change in thickness of the photoresist. This rich exposure machine performs fresh viewing cake and calibration steps The process of 'beginning with the conventional lithography process is the same, first spin coating-a layer of appropriate photoresist on the surface of the semiconductor wafer' for a soft baking; then exposure on the exposure machine (mother machine), the light source passes through the mask The pattern of the zero-level alignment mark on the layer is transferred to the photoresist, and then done Bake after exposure; then develop, hard bake, etch and remove photoresist steps; then use the same steps to define the first layer of alignment marks on the master machine. After the quasi-marks are all made, then define the second layer of alignment marks on another exposure machine (sub-machine). Please refer to Figure 2 and Figure 3. Figure 2 is the production of the second layer of alignment marks in the present invention. And the calibration flow chart. Figure 3 is a three-dimensional schematic diagram of the present invention after lithography with a special light sheet. The focus of the present invention is to cover the wafer 10 with a layer of photoresist 15 with an appropriate thickness, and perform soft baking. A special reticle was subjected to lithography batch “Ban Hong 15 15”, and then developed to remove the softened photoresist 100b, that is, to remove the zero-level alignment mark 20 (cross symbol in FIG. 3) and Photoresistor above the first layer of alignment mark 25 (cross symbol in Figure 3); but do not continue to do the hard roasting process, because the second layer of alignment mark is also required to be produced; Exclusive light sheet for the second layer of alignment marks, with the zeroth layer of alignment marks 20 and the first layer pair The mark 25 is based on the alignment 'expose the second layer of alignment mark pattern 110 on the exposure, and then perform post-exposure baking' development 120, the step of hard baking 'to define the alignment mark of the second layer on the wafer. Rensong and General Electric Nets (CNS) A4 size (210x297 public envy) (please note the precautions on the back of the product before filling out this page) Order printed by the Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 451295 Α7 Β7 Description of the Invention (t Intellectual Property Bureau of the Ministry of Economic Affairs β); After printing by the industrial and consumer cooperatives, measure the position of the alignment marks on the first and second layers 13o, and use the formula to calculate the stacking error. Error, make appropriate and necessary adjustments 140 of the red alignment system and lens device of the handset until the operating status of the master disk system is the same. In the lithography process of the present invention, the tilting car of the exposure machine and the full use of the lens function are completed in the process. '' Before the exposure of the first layer of alignment marks is made, a special mask is used to expose and develop the photoresist that has been exposed to the second layer. The purpose is to remove the zero layer of alignment marks and the first layer. Align the photoresist above the mark. This makes it possible to directly align the zero-level alignment mark and the first-level alignment mark of the area 30 without photoresist coverage on the wafer surface when defining the second-level alignment mark, and calculate the error of the overlapping result. There will be no shadow of the type and thickness of the photoresist, but the error of the virtual disk bud is tested; and in this step, after the above photoresist is developed, the reason for not baking hard is to continue. Then the second layer of alignment marks are exposed. By using the alignment mark correction method of the present invention, the best pair _ result can be obtained, and then the exposure machine system can be adjusted appropriately according to the error calculated by a ten, so that the machine can be in an optimal state. Therefore, the exact position of the circuit layout for each subsequent exposure is provided, and the quality of the wafer with the best exposure result is obtained. The above is a detailed description of the present invention using the preferred embodiments, and the scope of the present invention is not limited to the embodiments shown in it, and those who are familiar with semiconductor technology will be able to understand and make slight changes and adjustments appropriately, The essence of the present invention will not be lost, nor will it deviate from the spirit and scope of the present invention. Β This paper size is generally Ning Ning National Standard (CNS) A4 specification (210X297 mm) (Please read the note on the back before filling in. (Not page) 9. II n