4508 73 A7 B7 五、發明說明（） 5-1發明領域： (請先Μ讀背面之注意事項再填寫本頁》 本發明是有關一種化學機械研磨製程的製程方法，特別 有關於一種化學機械研磨製程之研磨時間的預估方法。 5-2發明背景： 現行的積體電路設計，已從大型積體電路設計進步到 超大型積體電路，而積體電路的圖案尺寸，從四分之一微 米縮小到小於四分之一微米，整個積體電路的設計朝向於 高積集度與小尺寸的方向，而整個積體電路的製程整合’ 也同樣需要不斷的更新，以應付整個積體電路設計的需求。 經濟部智慧財產局員工消费合作社印製 在積體電路的先前製程為定義積體電路的主動區域，決 定在半導體晶圓上的主動區域，而每一個主動區域為一個 積體電路的製造區域，在一半導體晶圓之上，同時製作許 多個主動區，而且同時形成許多個積體電路。一般而言， 定義主動區的方法有數種，包括形成場氧化層將整個主動 去圍繞起來，或者形成淺渠溝隔離圍繞各個主動區，或者 是在二氧化矽層上製造元件，而二氧化矽層成為最好的絕 緣層。 以現有的積體電路製造技術而言，形成場氧化層來定義 主動區的方式，會浪費太多的面積，使得積體電路的積集 度無法提高，而在二氧化矽材料上形成元件的製程，尚未 完全成熟，使得淺渠溝隔離製程成為一種現行製程最成熟 3 本紙張尺度適用中困國家標準（CNS)A4規+fr(210 X 297公* ) 4508 73 A7 B7 經濟部智慧財產局貝工消费合作社印製 五、發明說明（ 的隔離技術。 淺渠溝隔離技術（shallow trench isolation; STI)是先在 半導艘晶圓之上形成淺渠溝，然後回填二氧化矽材料至渠 溝之中’作為絕緣材料，然後去除在半導體晶圓表面的二 氧化矽材料，也就是在主動區表面的二氧化矽材料，形成 一個平坦的淺渠溝填入。以下將參考圖式說明一般淺渠溝 隔離技術。 請參閱第一圖，在半導艎基材100的表面覆蓋一層氮化 碎層110，作為一研磨製程或蚀刻製程的停止層，防止在淺 渠溝隔離製程之中’傷害到積體電路之製造區域的半導體 基材100 »然後，利用微影技術，在半導體基材100上定義 積體電路的區域。接著利用蝕刻技術，對半導逋基材1〇〇 進行蝕刻反應，在半導體基材100上形成數個淺渠溝。 請參閱第二圖，沈積二氧化矽層120回填到半導體基材 10〇的淺渠溝之中，並覆蓋在氮化矽層110之上，利用二氧 化矽材料的絕緣性，形成良好的淺渠溝隔離。在沈積二氧 化矽層120之後，整個二氧化矽層120的表面形態是凹凸 不平，在淺渠溝區域為凹下的，而在氮化矽層110上方的 二氧化矽層是凸起的。這是由於二氧化矽材料的形成方法 通常為化學氣相沈積製程，具有良好的階梯覆蓋性，二氧 化矽材料在沈積時，會隨著底層圖案的高低起伏做變化， 形成凹凸不平的表面形態（topography)。 在沈積二氧化矽層120之後，必須去除在氮化矽層110 之上的二氧化矽層120,以形成平坦的渠溝填入，方便後面 — — — — — — —— — — — ——— — — — II ^ — — — — — — — (請先閱讀背面之注意事3*再填寫本頁) 4508 73 A7 B7 五、發明說明（） (請先閱讀背面之注意事項再填寫本頁) 的積體電路製程。通常平坦化二氧化矽層120的方法，通 常是使用化學機械研磨製程，或者是化學機械研磨製程與 蝕刻製程的混合使用，達到整個表面平坦化的目的。 現今最常使用的全面性平坦化製程為化學機械研磨製 程，但是進行此種製程可以有效磨平二氧化矽層120,但是 製程的進行時間很難控制，也就是半導體晶圓的研磨時間 很難控制。當研磨時間不夠長時，在氮化矽層110的表面 會殘留二氧化矽層120,無法進行後續的製程，必須再對半 導體晶圓100進行化學機械研磨製程，直到在氮化矽層110 表面的二氧化矽層120完全去除；當研磨時間過長時，會 在渠溝區域的二氧化矽層Π0的表面形成凹陷，使得在渠 溝區域的絕緣效果變差，進而產生漏電的結果。請參閱第 三圖，顯示出當研磨時間過短時，在氮化矽層110的表面 會殘留二氧化矽層120;請參閱第四圖，顯示出當研磨時間 過長時，在渠溝區域產生二氧化矽層120的凹陷。 經濟部智慧財產局員工消费合作社印製 以上所述的淺渠溝隔離製程，必須在將二氧化矽材料填 入渠溝之後，準確控制化學機械研磨製程的研磨時間，在 淺渠溝之中形成一個平坦的二氧化矽填入。但是，根據化 學機械研磨製程的特性，對越大面積的待磨層，其研磨速 率越小，使得研磨速率與底層圖案會有關連。根據這種製 程特性，設計一種配合蝕刻製程的化學機械研磨製程，在 二氧化矽材料填入淺渠溝之後，進行一蝕刻製程，先去除 部份主動區域的二氧化矽材料，然後再進行化學機械研磨 製程，以下將配合圊式第五圖至第七圖做一詳細說明。 5 本ϋ尺度適用争國國家揉準（CNS)A4規格（210 X 297公釐) 4508 73 經濟部智慧財產局貝工消f合作社印製 A7 B7 五、發明說明（） 請參閱第五圈，在半導體晶圓100上覆蓋氮化矽層 110 ’接著形成數個淺渠溝，然後覆蓋二氧化矽層120至淺 渠溝之中，並覆蓋在氮化矽層110的表面，由於底層圖案 為凹凸不平的表面，所以二氧化矽層120具有凹凸不平的 表面形態。請參閲第六圖，利用一罩幕在二氧化矽層120 上定義圖案’然後蝕刻在氮化矽層11〇之上的二氧化矽層 120,露出氮化矽層11〇的表面，使用這到蝕刻製程的優點’ 在於預先清除在氮化矽層U0表面的二氧化矽層120,在後 續的研磨製程時’更容易去除在氮化矽層110表面的二氧 化梦層120。請參閱第七圖’進行化學機械研磨製程，去除 在氮化矽層110之上的二氧化矽層12〇，形成一個平坦的淺 渠溝填入。 使用蝕刻製程來配合化學機械研磨製程，是能夠有效的 去除氮化矽層110表面的二氧化矽層12〇，但是，在進行二 氧化矽層120的化學機械研磨製程時，半導體晶圓的研磨 時間會影響到研磨效果，研磨時間過短將會需要再進行一 次研磨製程；研磨時間過常將會導致淺渠溝的絕緣效果不 良β因此，事先預估化學機械研磨製程的研磨時間，將會 有效加快半導體晶圓的研磨製程，提高生產線的產量。 5-3發明目的及概述： 本發明揭露-贼渠親離化學機械研磨製㈣研磨時 間的預估方法’計算在半導髋“切體電路主動區域的面 6 本紙張尺度4財W a家料（CNS)A4规_格⑽χ撕公$ ------------裝i ~ 一 (請先閱讀背面之注意事項再填寫本頁) 450873 A7 B7 經濟部智慧財產局負工消费合作社印製 五、發明說明（） 積比例’作為第一面積比例；計算二氧化矽區域佔半導體晶 圓的第二面積比例；將第一面積比例與第二面積比例相乘， 得到半導體晶圓的總體圖案密度’為此半導體晶圓的特性 值；然後，對半導體晶圓進行化學機械研磨製程，計算出半 導體晶圓的研磨時間；經由半導體晶圓的研磨時間，計算出 在空白圊案晶圓上的相對應磨除厚度，決定半導體晶圓的總 體圊案密度’對於空白圖案晶圓的相對應磨除厚度關係圖； 對關係圖決定一線性逼近直線；決定一待研磨半導體晶圓的 總體圖案密度；經由線性逼近直線，在此直線上找出與總體 圖案密度相關的空白圈案晶圓的相對應磨除厚度；經由空白 圖案晶圓的研磨速率，利用相對應磨除厚度，決定磨除此相 對應磨除厚度的研磨時間。 本發明的一項優點是利用不同總體圖案密度的半導體晶 圓，對空白圖案晶圊的相對應磨除厚度的關係，決定一待研 磨半導體晶圓在空白圖案晶圓的相對應磨除厚度，決定待研 磨半導體晶圓的研磨時間。 本發明的另一項優點是利用計算半導體晶圓的總體圖案 密度，決定半導體的研磨時間，減少製程試轉的時間，增加 生產線的產量。 本發明的又一項優點是是找出半導體晶圓的圖案密度， 與空白圈案晶圓的研磨時間的線性關係，並以一線性逼近直 線來表示兩者的關係，在進行半導體晶圓的化學機械研磨製 程之前，先計算半導體晶圓的圖案密度，即可換算得知半導 體晶圓的研磨時間。 7 本紙張尺度適用中困國家標準（CNS>A4 %格（210 * 297公藿） I I ^ — — — — — — — — ^ I - I I I ^ t I I · ί |> I a— ^ I ϋ I I I * - <請先閲讀背面之注意事項再填寫本頁) 450873 五、發明說明（） 本發明的再一項優點是利用統計方法，計算出半導體晶 圓的圖案密度，與研磨時間的關係圖，進而預測不同圖案^曰 度的半導體晶圓，所需要的研磨時間。 5-4圖式簡單說明： 經濟部智慧財產局員工消貧合作杜印製4508 73 A7 B7 V. Description of the invention () 5-1 Field of invention: (Please read the precautions on the back before filling in this page "The present invention relates to a process method of a chemical mechanical polishing process, and particularly relates to a chemical mechanical polishing process Method for estimating the grinding time of the manufacturing process 5-2 Background of the Invention: The current integrated circuit design has progressed from large integrated circuit design to very large integrated circuit, and the pattern size of integrated circuits has changed from one quarter The micron shrinks to less than a quarter of a micron. The design of the entire integrated circuit is oriented towards high integration and small size, and the process integration of the entire integrated circuit also needs constant updates to cope with the entire integrated circuit. Design requirements. The previous process printed by the Intellectual Property Bureau employee consumer cooperative in the Ministry of Economic Affairs printed on the integrated circuit is to define the active area of the integrated circuit, determine the active area on the semiconductor wafer, and each active area is an integrated circuit. In the manufacturing area of a semiconductor wafer, many active areas are fabricated at the same time, and many integrated circuits are formed at the same time. Generally, There are several methods to define the active area, including forming a field oxide layer to surround the entire active area, or forming a shallow trench to isolate the surrounding active areas, or manufacturing components on the silicon dioxide layer, and the silicon dioxide layer becomes the most Good insulation layer. In terms of the existing integrated circuit manufacturing technology, the method of forming a field oxide layer to define the active area will waste too much area, making it impossible to improve the integration degree of integrated circuits. The process of forming components on materials has not yet fully matured, making the shallow trench isolation process the most mature of the current process. 3 This paper size applies to the National Standard for Difficulties (CNS) A4 + fr (210 X 297mm *) 4508 73 A7 B7 Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Isolation technology of the invention. Shallow trench isolation (STI) isolation technology is to form shallow trenches on semi-conductor wafers first, and then backfill two. The silicon oxide material into the trench is used as an insulating material, and then the silicon dioxide material on the surface of the semiconductor wafer is removed, that is, the silicon dioxide on the surface of the active region. Material to form a flat shallow trench fill. The general shallow trench isolation technology will be described below with reference to the drawings. Referring to the first figure, a surface of the semiconductor substrate 100 is covered with a layer of nitrided chip 110 as a The stop layer of the grinding process or the etching process prevents the semiconductor substrate 100 from damaging the manufacturing area of the integrated circuit during the shallow trench isolation process. Then, using the lithography technology, the integrated circuit is defined on the semiconductor substrate 100 Then, using an etching technique, an etching reaction is performed on the semiconductor substrate 100 to form several shallow trenches on the semiconductor substrate 100. Referring to the second figure, a silicon dioxide layer 120 is deposited and backfilled to the semiconductor substrate. In the shallow trenches of 100 mm, and covering the silicon nitride layer 110, the insulation of the silicon dioxide material is used to form a good shallow trench isolation. After depositing the silicon dioxide layer 120, the surface morphology of the entire silicon dioxide layer 120 is uneven, concave in the shallow trench area, and the silicon dioxide layer above the silicon nitride layer 110 is convex. This is because the formation method of silicon dioxide material is usually a chemical vapor deposition process with good step coverage. When the silicon dioxide material is deposited, it will change with the fluctuation of the underlying pattern to form an uneven surface shape. (Topography). After depositing the silicon dioxide layer 120, the silicon dioxide layer 120 above the silicon nitride layer 110 must be removed to form a flat trench filling, which is convenient for the back — — — — — — — — — — — — — — — — II ^ — — — — — — — (Please read the notes on the back 3 * before filling out this page) 4508 73 A7 B7 V. Description of the invention () (Please read the notes on the back before filling out this page ) Integrated circuit manufacturing process. Generally, the method for planarizing the silicon dioxide layer 120 is usually a chemical mechanical polishing process, or a combination of a chemical mechanical polishing process and an etching process, to achieve the purpose of planarizing the entire surface. The most commonly used comprehensive planarization process today is a chemical mechanical polishing process, but this process can effectively smooth the silicon dioxide layer 120, but the time of the process is difficult to control, that is, the polishing time of the semiconductor wafer is difficult control. When the polishing time is not long enough, the silicon dioxide layer 120 will remain on the surface of the silicon nitride layer 110, and subsequent processes cannot be performed. The semiconductor wafer 100 must be chemically and mechanically polished until it is on the surface of the silicon nitride layer 110. The silicon dioxide layer 120 is completely removed; when the polishing time is too long, a depression will be formed on the surface of the silicon dioxide layer Π0 in the trench area, so that the insulation effect in the trench area is deteriorated, and the result of leakage is generated. Please refer to the third figure, which shows that when the polishing time is too short, the silicon dioxide layer 120 will remain on the surface of the silicon nitride layer 110; refer to the fourth figure, which shows that when the polishing time is too long, in the trench area A depression of the silicon dioxide layer 120 is generated. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the above-mentioned shallow trench isolation process. After filling the trench with silicon dioxide material, the grinding time of the chemical mechanical polishing process must be accurately controlled to form in the shallow trench. Filled with a flat silicon dioxide. However, according to the characteristics of the chemical mechanical polishing process, for a larger area of the layer to be polished, the polishing rate is smaller, so that the polishing rate is related to the underlying pattern. According to this process characteristic, a chemical mechanical polishing process is designed to match the etching process. After the silicon dioxide material is filled into the shallow trench, an etching process is performed. The silicon dioxide material in some active areas is removed first, and then chemically processed. The mechanical grinding process will be described in detail below with reference to Figures 5 to 7 of the formula. 5 This standard applies to CNS A4 specifications (210 X 297 mm) 4508 73 Printed by Ai Biao Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, F7, Cooperative Fifth, the description of the invention () Please refer to the fifth circle, The semiconductor wafer 100 is covered with a silicon nitride layer 110 ′, and then several shallow trenches are formed, and then the silicon dioxide layer 120 is covered into the shallow trenches, and the surface of the silicon nitride layer 110 is covered. The uneven surface makes the silicon dioxide layer 120 have an uneven surface morphology. Referring to the sixth figure, a mask is used to define a pattern on the silicon dioxide layer 120, and then the silicon dioxide layer 120 is etched on the silicon nitride layer 110 to expose the surface of the silicon nitride layer 110. The advantage of this etching process is that the silicon dioxide layer 120 on the surface of the silicon nitride layer U0 is removed in advance, and in the subsequent polishing process, the dream dioxide layer 120 on the surface of the silicon nitride layer 110 is more easily removed. Please refer to FIG. 7 ′ for performing a chemical mechanical polishing process to remove the silicon dioxide layer 12 on the silicon nitride layer 110 to form a flat shallow trench fill. The etching process is used in conjunction with the chemical mechanical polishing process to effectively remove the silicon dioxide layer 12 on the surface of the silicon nitride layer 110. However, during the chemical mechanical polishing process of the silicon dioxide layer 120, the semiconductor wafer is polished. Time will affect the grinding effect. Too short grinding time will require another grinding process; too long grinding time will lead to poor insulation effect of shallow trenches. Therefore, the grinding time of the chemical mechanical grinding process will be estimated in advance. Effectively speed up the grinding process of semiconductor wafers and increase the output of production lines. 5-3 Purpose and Summary of the Invention: The present invention discloses the method of estimating the grinding time of the squeegee-releasing chemical-mechanical grinding system, which is calculated on the surface of the active area of the semiconducting hip "cut body circuit. (CNS) A4 Regulation _ 格 撕 χ Tearing $ ------------ Install i ~ One (Please read the precautions on the back before filling this page) 450873 A7 B7 Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Industrial and Commercial Cooperatives 5. Description of the invention () The product ratio is used as the first area ratio; the second area ratio of the silicon dioxide area to the semiconductor wafer is calculated; the first area ratio and the second area ratio are multiplied to obtain the semiconductor The overall pattern density of the wafer is the characteristic value of the semiconductor wafer. Then, a chemical mechanical polishing process is performed on the semiconductor wafer to calculate the polishing time of the semiconductor wafer; the polishing time of the semiconductor wafer is used to calculate the blank space. Corresponding thickness of the polished wafer on the wafer determines the overall density of the semiconductor wafer. 'Corresponding thickness of the polished wafer for blank pattern wafers; determines a linear approximation line for the relationship graph; determines a half to be polished The overall pattern density of the conductor wafer; through the linear approximation to the straight line, the corresponding grinding thickness of the blank circle wafer related to the overall pattern density is found on this straight line; through the polishing rate of the blank pattern wafer, the corresponding grinding is used The thickness is determined by the grinding time corresponding to the grinding thickness. One advantage of the present invention is to use semiconductor wafers with different overall pattern densities to determine the relative grinding thickness of blank pattern crystals. The corresponding thickness of the polished semiconductor wafer on the blank pattern wafer determines the polishing time of the semiconductor wafer to be polished. Another advantage of the present invention is to determine the polishing time of the semiconductor by calculating the overall pattern density of the semiconductor wafer. Reducing the process trial time and increasing the output of the production line. Another advantage of the present invention is to find the linear relationship between the pattern density of the semiconductor wafer and the polishing time of the blank wafer, and approximate it with a linear straight line. Represents the relationship between the two, and calculates the semiconductor wafer before the chemical mechanical polishing process of the semiconductor wafer. The density of the pattern can be converted to know the grinding time of the semiconductor wafer. 7 This paper size applies to the national standard of difficulty (CNS > A4% grid (210 * 297 cm)) II ^ — — — — — — — — ^ I- III ^ t II · ί | > I a— ^ I ϋ III *-< Please read the notes on the back before filling out this page) 450873 V. Description of the invention () Another advantage of the present invention is the use of statistical methods Calculate the pattern density of semiconductor wafers and the relationship between polishing time, and then predict the polishing time required for semiconductor wafers with different patterns ^ degrees. 5-4 Schematic description: Cooperation in poverty
本發明的許多發明目的與優點，將會因為參考下列的詳 細說明’變得更容易被鑑f與瞭解，同時參酌下列的圖式加 以說明，其中： 第一®係顯示習知技術之中，在半導體基材令形成淺渠 溝，作為積體電路的淺渠溝隔離，並定義出積體電 路的主動區域； 第二囷係顯示習知技術之令，沈積二氧化矽材料回填至渠 溝中，在半導體基材的主動區上方形成二氧化矽突 起’其中一氧化矽材料是作為淺渠溝隔離的絕緣材 料； 第二圖係顯示習知技術之中，利用化學機械研磨製程，除 去在主動區上的二氧化矽材料，當研磨時間不夠 長，會在主動區的上方殘留過多的二氧化矽材料； 第四圖係顯示習知技術之中，利用化學機械研磨製程’除 去在主動區上的二氧化矽材料，當研磨時間過長， 會在淺渠溝區域形成二氧化梦層凹陷的剖面； 第五圖係顯示本發明之半導體基材的淺渠溝隔離的剖面 示意圖，在半導艘基材上形成淺渠溝，然後回填二Many of the objects and advantages of the present invention will be more easily recognized and understood by referring to the following detailed description, while referring to the following drawings to illustrate, among which: First, among the display techniques, Shallow trenches are formed on the semiconductor substrate to isolate the shallow trenches of the integrated circuit, and define the active area of the integrated circuit; the second line shows the order of the conventional technology, depositing silicon dioxide material and backfilling the trench In the semiconductor substrate, a silicon dioxide protrusion is formed over the active region of the semiconductor substrate. Among them, the silicon oxide material is an insulating material used as a shallow trench isolation. The second picture shows a conventional technique using a chemical mechanical polishing process to remove When the silicon dioxide material on the active area is not polished for a long time, too much silicon dioxide material will remain above the active area. The fourth picture shows the conventional technology using chemical mechanical polishing process to remove the silicon dioxide material in the active area. The silicon dioxide material on the surface, when the polishing time is too long, will form a cross section of the dream dioxide layer depression in the shallow trench area; the fifth figure shows the semiconductor of the present invention Schematic diagram of the shallow trench isolation of the substrate. A shallow trench is formed on the semi-conductor substrate, and then backfilled.
本紙張尺度適用中國國家楳準（CNS)A4規格（210 X 297公jf J 4508 73This paper size applies to China National Standard (CNS) A4 (210 X 297 male jf J 4508 73
五、發明說明（） 氡化矽材料至淺渠溝之中，使得二氧化矽材料在主 動區域形成突起； 第六圖係顯示本發明之半導體基材的淺渠溝隔離的剖面 示意圖，對主動區之上的二氧化矽進行蝕刻反應， 去除一部分的二氧化矽材料，減少在主動區上的二 氧化矽層厚度； 第七圖係顯示本發明之半導體基材的淺渠溝隔離的剖面 示意圖，對二氧化矽材料進行化學機械研磨製程， 去除在半導體基材表面的二氧化矽材料，在淺渠溝 之中形成平坦的填入； 第八圖係顯示習知技術之方法，以在半導體基材上的主動 區的圖案密度，統計不同圖案密度對空白晶圓的二 氧化矽磨除厚度的關係，比較此關係是否為線性； 經濟部智慧財產局貝工消费合作社印製 第九圖係顯示本發明之方法，以在半導體基材上主動區域 的圊案密度，乘上在半導體基材上有二氧化矽材料 區域的圖案密度，對空白片磨除厚度的關係圖，求 得具有不同圊案密度的半導體基材相對於空白晶圓 的二氧化矽磨除厚度：及 第十圖係以流程圈解釋本發明之化學機械研磨製程的研 磨時間預估方法。 5-5發明詳細說明： 本紙張尺度適用令0 «家標準（CNS)A4規格（210 X 297公釐） 450873V. Description of the invention () The siliconized material enters the shallow trench, so that the silicon dioxide material forms a protrusion in the active area; The sixth figure is a schematic cross-sectional view showing the shallow trench isolation of the semiconductor substrate of the present invention. The silicon dioxide on the region is subjected to an etching reaction to remove a part of the silicon dioxide material and reduce the thickness of the silicon dioxide layer on the active region. The seventh diagram is a schematic cross-sectional view showing the shallow trench isolation of the semiconductor substrate of the present invention. The chemical mechanical polishing process is performed on the silicon dioxide material to remove the silicon dioxide material on the surface of the semiconductor substrate to form a flat filling in the shallow trench. The eighth figure shows a method of conventional technology to The pattern density of the active area on the substrate is used to calculate the relationship between different pattern densities and the thickness of the silicon dioxide removal thickness of the blank wafer, and to compare whether the relationship is linear. Shows the method of the present invention, multiplying the density of the active region on the semiconductor substrate by the density of the silicon dioxide material region on the semiconductor substrate. The relationship between the density of the blanks and the thickness of the blanks, and the thickness of the silicon dioxide removal of semiconductor substrates with different densities relative to the blank wafers: and the tenth figure is a process circle explaining the chemistry of the present invention. Method for estimating grinding time in mechanical grinding process. 5-5 Detailed description of the invention: This paper size applies to order 0 «Home Standard (CNS) A4 Specification (210 X 297 mm) 450873
五、發明說明（ 於本發明之中揭露一種化學機械研磨製程的控制方法， 計算在定義淺渠溝微影製程與定義二氧化矽層圖案微影製 程之光罩的圖案密度’進行計算出在兩次微影製程之後，在 淺渠溝圖案上的二氧化矽層的總體圖案密度，然後對淺渠溝 隔離晶圓片進行研磨製程，計算研磨時間，換算成在空白圖 案晶園片上的磨除厚度。進行數個半導體晶圓的總體圖案密 度對空白圖案晶圓片上的磨除厚度關係量測，當計算出一個 淺渠溝圖案晶圓的總體圖案密度時，經由上述的關係圖，計 算出相對於空白圖案晶圓片的磨除厚度，進而決定淺渠溝圖 案晶圓的研磨時間。 請參閱第五圖，首先在半導體晶圓100上覆蓋一層氮化 矽層110’接著利用微影與蝕刻製程，在半導體晶圓1〇〇 上形成淺渠溝區域，而氣化♦層110作為一研磨停止層， 然後沈積二氧化矽層120至淺渠溝之中，並覆蓋在氮化矽 層110的表面，二氧化矽層120的形成方法為化學氣相沈 積製程，由於底層圖案的表面形態為高低起伏，所以二氧 化矽層120也呈現出凹凸不平的表面形態（t〇p〇graphy)。在 一較佳實施例之中，二氧化矽層120為高密度電漿化學氣 相沈積二氧化矽材料(HDP-Oxide)。 請參閱第六圖，利用微影與蝕刻製程，蝕刻在氮化矽層 110表面的二氧化矽層120 ,預先去除部份的二氧化矽層 120 ’此為第二次的微影與蝕刻製程。 請參閱第七圖，利用化學機械研磨製程，對二氧化矽層 120進行研磨製程，去除在氮化矽層u〇表面的二氡化矽層 10 本紙張尺度適用中國國家標单（CNS)A4規格（210 X 297公爱） -----------裝 - ------訂··-------線'^ (請先閱讀背面之注意事項再填冩本頁) 經濟部智慧財產局ΒΚ工消費合作社印製 450873 A7 B7___ 五、發明說明（） 120 ’並以氣化石夕$ 11〇作為研磨停止層在化學研磨製程 之後，去除氮化碎層110,以形成具有良好絕緣效果的淺渠 溝隔離（STI)。 以上所敘述的淺渠溝隔離製程，為一蝕刻與化學機械研 磨製程混合使用的製程，能夠有效去除在氮化碎層110表 面的一氧化矽層120ο在這個淺渠溝隔離製程之中，使用兩 道蝕刻與微影步驟，第一次的微影步驟定義出淺渠溝區 域，第一次的微影步驟定義出在氮化矽層上欲除去的二氧 化矽區域》 在第二次微影步驟之中，由於氮化矽層區域為積體電路 主動區域，此區域寬度必須大於某個尺寸以上，現行的微 影製程，才能將圖案對準到二氧化矽層之上β換言之’在 某些尺寸較小的主動區域，會因為對準誤失的緣故，使得 第二次微影製程無法轉移圖案到小尺寸的主動區域。理論 上來講，應該在第一次微影與蚀刻製程之中，將氮化紗層 頂面的一氧化矽材料完全去除，是最為理想的情況。但是， 小尺寸區域無法精準的對準，所以第一次微影製程所使用 的罩幕圖案，與第二次微影製程所使用的罩幕圖案並不是 互補》 由於化學機械研磨製程對待磨層的底層圖案密度有很 大的關係，所以藉由計算底層圖案密度，尋找與研磨速率 的關連性’進而預估化學機械研磨製程的研磨時間。 首先’計算在積體電路主動區域的圖案密度（pattern density)，也就是積體電路主動區域佔半導體晶圓的面積比 11 本紙張尺度適用令國囲家楳準（CNS)A4規格（210 X 297公釐） -------------^裳— > - {請先閱讀背面之注意事項再填寫本頁) 訂 -線" 經濟部智慧財產局員工消费合作社印製 經濟部智慧財產局負工消费合作社印製 4508 73 A7 [*......___ B7 I五、發明說明（） 例。此一比例可看出在半導體晶圓上的圖案密度，換言之， 即是在二氧化矽層之下的圖案密度。 在计算出積趙電路主動區域的圖案密度之後，對半導體 晶圓進行化學機械研磨製程，估算需要多少的研磨時間， 能夠完全的去除在停止層之上的二氧化矽材料。在估算出 具有一特定圖案密度之半導體晶圓的研磨時間，計算在相 同研磨時間之中，空白圖案晶圓的磨除厚度，決定特定積 體電路主動區域圖案密度半導體晶圓，對空白圖案半導體 晶圓磨除厚度的關係圖。 請參閲第八圖，顯示在計算半導體晶圓的積體電路主動 區域圖案密度之後’在不同的積體電路圖案密度對空白圖 案晶圓片的磨除厚度的關係圖。虚線部份是實際的實驗數 據，由數個不同積體電路主動區域圖案密度的半導體晶 圆’所得到的空白圖案晶圓片的相對應磨除厚度。而實線 部份為利用線性方式逼近此實驗數據所得的線性關係圖， 表示出整個實驗數據的大致趨勢。 從第八囷來看’可看出實驗數據與線性模擬直線有相當 大的差距’每個實驗數據點與直線的差距相當大，這代表 整個實驗數據並不是呈現出線性的變化。依照化學機械研 磨製程的特性而言，當研磨面積越大的區域，研磨製程所 得的研磨速率會越低，整個關係會是一種反比的情形。由 於具有積體電路圖案的半導體晶圓，所相對應的空白圖案 晶圓的磨除厚度，即是代表積體電路圖案半導體晶圓的研 磨速度，所以兩者之間的關係也應呈現出一線性關係，所 12 本紙張尺度適用中a國家標準（CNS>A4規格（210 X 297公釐）V. Description of the Invention (In the present invention, a control method of a chemical mechanical polishing process is disclosed, and the pattern density of a mask defining a shallow trench lithography process and a silicon dioxide layer pattern lithography process is calculated. After two lithography processes, the overall pattern density of the silicon dioxide layer on the shallow trench pattern, and then the grinding process is performed on the shallow trench isolation wafer, and the polishing time is calculated and converted into the grinding on the blank pattern wafer. Divide thickness. Measure the relationship between the overall pattern density of several semiconductor wafers and the ablation thickness on a blank pattern wafer. When the overall pattern density of a shallow trench pattern wafer is calculated, calculate it through the above relationship diagram. The polishing thickness relative to the blank pattern wafer is determined to determine the polishing time of the shallow trench pattern wafer. Referring to the fifth figure, a semiconductor nitride 100 is first covered with a silicon nitride layer 110 'and then a lithography is used. And an etching process, a shallow trench region is formed on the semiconductor wafer 100, and the gasification layer 110 is used as a polishing stop layer, and then a silicon dioxide layer 120 is deposited Shallow trenches cover the surface of the silicon nitride layer 110. The method for forming the silicon dioxide layer 120 is a chemical vapor deposition process. Because the surface pattern of the underlying pattern is undulating, the silicon dioxide layer 120 also appears Rugged surface morphology (topography). In a preferred embodiment, the silicon dioxide layer 120 is a high-density plasma chemical vapor deposition silicon dioxide material (HDP-Oxide). Six pictures, using the lithography and etching process, the silicon dioxide layer 120 is etched on the surface of the silicon nitride layer 110, and a part of the silicon dioxide layer 120 is removed in advance. This is the second lithography and etching process. Please refer to In the seventh figure, the chemical mechanical polishing process is used to grind the silicon dioxide layer 120 to remove the silicon dioxide layer on the surface of the silicon nitride layer u0. This paper size applies to China National Standards (CNS) A4 specifications ( 210 X 297 public love) ----------- install- ------ order ·· ------- line '^ (Please read the notes on the back before filling in the transcript Page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, BKK Industrial Cooperative, 450873 A7 B7___ V. Description of Invention () 120 ' Fossil eve $ 110 is used as a grinding stop layer. After the chemical grinding process, the nitride fragmentation layer 110 is removed to form a shallow trench isolation (STI) with good insulation effect. The shallow trench isolation process described above is an etching process. The process mixed with the chemical mechanical polishing process can effectively remove the silicon oxide layer 120 on the surface of the nitrided layer 110. In this shallow trench isolation process, two etching and lithography steps are used. The shadowing step defines the shallow trench area. The first lithography step defines the silicon dioxide area to be removed on the silicon nitride layer. In the second lithography step, the area of the silicon nitride layer is The active area of the body circuit, the width of this area must be greater than a certain size, the current lithography process can align the pattern on the silicon dioxide layer. In other words, in some active areas with smaller sizes, Due to the mistake, the second lithography process cannot transfer the pattern to the small-sized active area. In theory, in the first lithography and etching process, the silicon oxide material on the top surface of the nitrided yarn layer should be completely removed, which is the most ideal situation. However, the small size area cannot be precisely aligned, so the mask pattern used in the first lithography process is not complementary to the mask pattern used in the second lithography process. The underlying pattern density has a large relationship, so by calculating the underlying pattern density, looking for the correlation with the polishing rate, and then estimating the polishing time of the chemical mechanical polishing process. First 'calculate the pattern density in the active area of the integrated circuit, that is, the area ratio of the active area of the integrated circuit to the semiconductor wafer. 11 This paper size is applicable to the National Standard for Domestic Standards (CNS) A4 (210 X 297 mm) ------------- ^ Sang — >-{Please read the precautions on the back before filling out this page) Order-line " Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives Printed by the Consumer Goods Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4508 73 A7 [* ......___ B7 I V. Description of Invention () Example. This ratio can be seen in the pattern density on the semiconductor wafer, in other words, the pattern density under the silicon dioxide layer. After calculating the pattern density of the active area of the product circuit, a chemical mechanical polishing process is performed on the semiconductor wafer to estimate how much polishing time is needed to completely remove the silicon dioxide material above the stop layer. After the polishing time of a semiconductor wafer with a specific pattern density is estimated, the thickness of the blank pattern wafer during the same polishing time is calculated to determine the pattern density semiconductor wafer of the active area of the specific integrated circuit. Relation graph of wafer abrasion thickness. Please refer to the eighth figure, which shows the relationship between the pattern density of the integrated circuit active area pattern of the semiconductor wafer and the thickness of the blank wafer after different pattern density of the integrated circuit. The dotted line is the actual experimental data. The corresponding thicknesses of the blank pattern wafers obtained from the semiconductor wafers with different pattern densities in the active area of the integrated circuit are removed. The solid line is a linear relationship obtained by approximating the experimental data in a linear manner, showing the general trend of the experimental data. From the eighth point of view, it can be seen that there is a considerable gap between the experimental data and the linear simulation straight line. The gap between each experimental data point and the straight line is quite large, which means that the entire experimental data does not show a linear change. According to the characteristics of the chemical mechanical grinding process, when the larger the grinding area, the lower the grinding rate obtained by the grinding process, and the entire relationship will be an inverse situation. Because semiconductor wafers with integrated circuit patterns and the corresponding blank pattern wafer's grinding thickness are representative of the polishing speed of integrated circuit pattern semiconductor wafers, the relationship between the two should also show a line Sexual relations, 12 paper sizes are applicable to China National Standards (CNS > A4 specifications (210 X 297 mm)
<請先閱讀背面之注意事項再填寫本頁) 4508 73 經濟部智慧財產局貝工消費合作杜印製 A7 B7 五、發明說明（） 以第八圖所顯示出的數據圖，並不是一個很好的線性關係。 所以，從第八圖之中得到一個結論，積體電路主動區域 的圖案密度，並不是唯一影響化學機械研磨製程研磨速率 的唯一因素，必須加以考慮其他因素的影響，才能得到— 個線性關係。於是，將第二次微影製程的圖案轉移列入考 慮，在氮化矽層之上所移除的二氧化矽層區域，也是形成 一種圖案’也會影響到化學機械研磨製程的研磨速度。計 算在氮化矽層之上所移除的二氧化矽層區域，佔整個半導 體晶圓的面積比例，成為半導體晶圓的無圖案區域。換言 之，在第二次微影製程之中，所形成圖案的圊案密度為殘 留二氧化矽材料的區域佔半導體晶圓的面積比例，這是在 經過第二次蝕刻製程之後，二氧化矽層所具有的圖案密度。 將積趙電路主動區域所具有的圈案密度，乘上二氧化石夕 層所具有的圖案密度，得到化學機械研磨製程的總體圖案 密度’以這個總體圖案密度，與空白圖案晶圓的相對應磨 除厚度所形成的關係圖，如第九圖的虛線所示。經過線性 逼近的方式，得到實驗數據的線性逼近直線，從圖上可以 看出，整個實驗數據是相當逼近於線性逼近直線，表示出 整個實驗數據是呈現出線性關係》 在得到如第九圖所示的線性逼近直線之後，在進行後續 晶圓片的化學機械研磨製程之前’先計算半導體晶圓的總 體圖案密度，然後，經由線性逼近直線查出在空白圖案晶 圓片的相對應磨除厚度。 由於空白圈案晶圓片具有固定的研磨速率，當得知空白 13 本紙張尺度適用中國國家標準（CNS)A4規袼（210 X 297公釐） -----I ------^4 --I (請先閱讀背面之注意事JS-再填寫本頁) 幻· 線" 4508 五、發明說明（） 請 圖案晶圓片的相對應磨除厚度之後，即可得知化學機械研 磨製程的研磨時間，即是具有積體電路圖案之半導體晶圓 的研磨時間，直接在第一次研磨製程之申，設定研磨時間， 達到最佳的研磨效果》 訂 以下將參閱第十圖，以流程圖解釋本發明的化學機械研 磨製程的研磨時間預估方法。首先進行步驟1〇’計算積體 電路主動區域佔半導艎晶圓的面積比例，此面積比例被定 義為第一面積比例，也就是積體電路主動區域在半導體晶 圓上的圖案密度，接著，進行步驟20’在二氧化石夕層的沈 積後’再進行去除氮化矽層上的二氧化矽層的去除，露出 氮化矽層的表面’也就是在進行上述第二次微影與蝕刻製 程之後，計算二氧化矽區域佔半導體晶圓的面積比例，被 定義為第二面積比例，即為二氧化矽區域佔半導體晶圓的 圖案密度；進行步驟30，將第一面積比例與第二面積比例 相乘，得到總體圖案密度；進行步驟40，決定不同總體圖 案密度對空白圃案晶圓的相對應磨除厚度；進行步驟5〇， 經 濟 部 智 慧 財 產 局 貝 X 消 f 合 作 社 印 製 畫出總體圖案密度對相對應磨除厚度的關係曲線；進行步 驟60，決定步驟50之關係曲線的線性逼近曲線；進行步驟 70，一半導體晶圓要進行化學機械研磨製程之前，先計算 此半導體晶圓的總體圖案密度；進行步驟80，經由上述線 性逼近曲線，利用半導體晶圓的總體圖案密度決定在空白 圖案晶園上的相對應磨除厚度，然後決定半導體晶圓的研 磨時間。在步驟80之中，由於空白圖案晶圓具有固定的研 磨速率，當在空白圖案晶圓上的相對應磨除厚度已經知 本紙張尺度適用中國國家標準（CNS)A4规格（210 * 297公釐〉< Please read the precautions on the back before filling this page) 4508 73 Printed by Ai, B7, Baker, Consumer Cooperation, Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () The data chart shown in Figure 8 is not a Good linear relationship. Therefore, a conclusion is drawn from the eighth figure that the pattern density of the active area of the integrated circuit is not the only factor that affects the polishing rate of the chemical mechanical polishing process. The influence of other factors must be considered to obtain a linear relationship. Therefore, the pattern transfer of the second lithography process is taken into consideration. The area of the silicon dioxide layer removed above the silicon nitride layer is also a pattern. It also affects the polishing speed of the chemical mechanical polishing process. It is calculated that the area of the silicon dioxide layer removed above the silicon nitride layer accounts for the area ratio of the entire semiconductor wafer, and becomes the unpatterned area of the semiconductor wafer. In other words, in the second lithography process, the pattern density of the formed pattern is the area ratio of the remaining silicon dioxide material to the area of the semiconductor wafer. This is the silicon dioxide layer after the second etching process. The density of the pattern. Multiply the density of the case in the active area of the JZ circuit by the pattern density of the stone dioxide layer to obtain the overall pattern density of the chemical mechanical polishing process. The overall pattern density corresponds to the blank pattern wafer. The relationship between the thickness and the thickness is shown in dotted lines in the ninth figure. After the linear approximation method, the linear approximation line of the experimental data is obtained. It can be seen from the figure that the entire experimental data is quite close to the linear approximation line, indicating that the entire experimental data shows a linear relationship. After the linear approximation shown in the figure, the overall pattern density of the semiconductor wafer is calculated before the subsequent chemical mechanical polishing process of the wafer is performed. Then, the corresponding ablated thickness of the blank pattern wafer is found through the linear approximation line. . As the blank circle wafers have a fixed grinding rate, it should be known that the blank 13 paper sizes are applicable to the Chinese National Standard (CNS) A4 Regulation (210 X 297 mm) ----- I ------ ^ 4 --I (Please read the note on the back JS- then fill out this page) Magic · Line " 4508 V. Description of the invention () After removing the corresponding thickness of the pattern wafer, you can know the chemistry The polishing time of the mechanical polishing process is the polishing time of the semiconductor wafer with integrated circuit patterns. The polishing time is set directly in the application of the first polishing process to achieve the best polishing effect. The method for estimating the polishing time of the chemical mechanical polishing process of the present invention is explained with a flowchart. First perform step 10 'to calculate the area ratio of the active area of the integrated circuit to the semiconductor wafer. This area ratio is defined as the first area ratio, which is the pattern density of the active area of the integrated circuit on the semiconductor wafer. Step 20 is performed after the deposition of the SiO2 layer, and then the removal of the silicon dioxide layer on the silicon nitride layer is performed to expose the surface of the silicon nitride layer. That is, the above-mentioned second lithography and After the etching process, the area ratio of the silicon dioxide area to the semiconductor wafer is calculated and defined as the second area ratio, which is the pattern density of the silicon dioxide area in the semiconductor wafer. Go to step 30 to compare the first area ratio with the first Multiply the two area ratios to obtain the overall pattern density. Go to step 40 to determine the corresponding thickness of the blank wafer with different overall pattern densities. Go to step 50. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs X Xf Draw the relationship curve between the overall pattern density and the corresponding thickness; go to step 60 to determine the linear approximation curve of the relationship curve in step 50; Go to step 70. Before a semiconductor wafer is subjected to a chemical mechanical polishing process, first calculate the overall pattern density of the semiconductor wafer. Go to step 80 to determine the blank pattern crystal using the overall pattern density of the semiconductor wafer through the linear approximation curve described above. The corresponding thickness on the circle is removed, and then the polishing time of the semiconductor wafer is determined. In step 80, since the blank pattern wafer has a fixed polishing rate, it is known that the corresponding abrasive thickness on the blank pattern wafer is in accordance with the Chinese National Standard (CNS) A4 specification (210 * 297 mm). 〉
4508 73 五、發明說明（） 道，則研磨時間很容易經由換算相對應磨除厚度來得知3 本發明以較佳實施例說明如上，而熟悉此領域技藝者’ 在不脫離本發明之精神範圍内，當可作些許更動潤飾，其專 利保護範圍更當視後附之申請專利範圍及其等同領域而 定。 (請先聞讀背面之注意事項再填寫本頁> 訂·. 經濟部智慧財產局貝工消费合作杜印製 15 本紙張尺度適用t國困家標準（CNS)A4規格（210 X 297公釐）4508 73 V. Description of the invention (), then the grinding time is easy to know by converting the corresponding thickness. 3 The present invention has been described above with preferred embodiments, and those skilled in the art will not depart from the spirit of the present invention. In addition, when some modifications can be made, the scope of patent protection depends on the scope of the patent application and its equivalent fields. (Please read the precautions on the back before filling out this page.> Order. 15 Printed by the Intellectual Property Bureau, Ministry of Economic Affairs, Shellfish Consumer Cooperation, DuPont. This paper size is applicable to the National Standard for Household Standards (CNS) A4 (210 X 297). %)