4S707 ------------- --------------五、發明説明（1 部 屮 K i? ；/； f •ή' 本發明係提供一種八層電路板之壓合方法及其成品，特 別疋扣一種能達到電路板内外層阻抗匹配，以降低高速信 號反射及電磁干擾之電路板。 按，請參閱第一圖所示，係為一種習知板厚為12mm之 5八層電路板之各層排列示意圖，如圖所示，該電路板之第一、 三、六及八層為訊號走線層S1、S2、S3及S4，第二、四及 七層為接地層GND，而第五層則為電源層power，且第一層si 及第八層S4亦為零件佈設層；其中，該電路板之第四層與 第五層之間係壓合有一 8mil厚之第一絕緣層，該電路板之 ίο第三層與第四層之間及第六層與第五層之間分別壓合有一 5mil厚之第二絕緣層，該電路板之第二層與第三層之間及第 七層與第六層之間分別壓合有一 8mi 1厚之第三絕緣層，該 電路板之第一層與第二層之間及第八層與第七層之間壓合有 一 2. 5mi 1厚之第四絕緣層’而且，該第二絕緣層與第四絕 緣層之材質係為一聚酯膠片（ρ·ρ.)，該第一絕緣層與第三 絕緣層之材質係為一紙質、玻璃纖維之類的基材（c〇re); 而如上所述之各層板間的壓合方式會使得第一層板W對第 二層板GND之阻抗值Rs 1 =第八層板S4對第七層板GND之阻 抗值Rs4与44歐姆’第三層板S2對第二層板GND及第四層 板GND之阻抗值Rs2=第六層板S3對第五層板及第七 層板GND之阻抗值Rs 3乓55歐姆，然而，習知之壓合構造有 下列缺點： 1.高速信號反射嚴重 此種電路板在走高速訊號時，其傳輸線路之阻抗值設 第4頁 15 20 _>、纸张尺度述家嵇卑（CNS ) Λ4現格（210X297公趋)_ 却先閱讀背面之注意事項再"巧本頁 裴- ’11 70 7 A7 B7 五、發明説明（2 ) (誚先閲讀背!&之注意事項再填寫本万〕 計，亦就是層與層之間之阻抗值，依照Intel設定之規格 理論值最好應在55Ω±10%最好，也就是最好在49.5Ω 〜60. 5Ω之間，但由習知電路板所算出之結果，其中第一層 板S1(外層板）及第八層板S4(外層板）之阻抗值Rsl及Rs4 5 等於44Ω，第三層板S2(内層板）及第六層板S3(内層板） 之阻抗值 Rs2及 Rs3 等於 55Ω，即 Rsl=Rs4=44Ω，Rs2=Rs3=H _Ω，内外層板阻抗相差高達11歐姆,而此一内外層板阻括. 差距會造成阻抗不匹配，以致當一高速訊號在此—雷蹊 板中傳輸時，該高速訊號從外層，亦即零件佈設層（如第 10 一層或第八層）穿層至内層（如第三層板威篦六屉炻免 隻_致該高速訊號之訊號反射，造成訊號傳輸品質不良：右 這裡我們可以算出該高速訊號的反射係數係為ρ Ζ1 — Zo __ Rs\ — RsT, n ι τ ί =-二---IJ 丄丄 l Ο ZUZo Rsl + Rs2 ‘ 2.磁通抵消作用變差 15 前述該高速訊號之反射會產生駐波，且該駐波會加 強該高速訊號之電磁波輻射，使其磁通抵消作用變差， 而造成過局之電磁波干擾。 故以，若能使電路板之第一、三、六及八層為訊號走 線層SI、S2、S3及S4相對阻抗值RS1、RS2、Rs3 ' Rs4較 20接近，將可降低反射係數，進而使電磁波干擾減少，進而 適用於高速線路，使產品之利用價值提高；且由於阻抗已 控制’是以當電路板佈局而使走線穿至不同層時，並不需 要改變走線線寬，故可提高佈局之時效性。 ___第5頁 本紙认尺度適中1¾國家標莩（CNS ) Λ4規格（210x2h公旋1 ------- Α7 Β7 正事 本發明之主要 法及其成品鑛俾使各層訊號走線層阻抗匹配，進而降 低高速訊號纖來及電磁波干擾，錢該電路板適用於高 448 70 7 五、發明説明（3 ) 知之缺點，是以，本發明人累積多年從事該 :::經驗’積極爲研究，終有本發明『八層電路板之 麼α方法及其成品丨之產生。 ’係提供一種八層電路板之壓合方 速訊號 而’本發明之主要特徵在於，每一第一絕緣層之厚度 係在2-6mil㈣内’每―第二絕緣層之厚度係在 1〇範圍内’每第三絕緣層之厚度係在3~9mil ^圍内；及每 一第四絕緣層之厚度係在2.5-6· 5mil範圍内；藉此可使各 層訊號走線層阻抗匹配，進而降低高迷訊號之反射及電磁 波干擾，以使該電路板適用於高速訊號之佈設。 爰是，為達到上述之目的，本發明八層電路板壓合方 15法’其中該電路板之第一、三、六及八層為訊號走線層， 第二、四及七層為接地層，第五層為電源層；該方法係包 括下列步驟： a.上述電路板之第四層係以相距第五層於2_6mn範圍内以 絕緣材質壓合； 20 b·步驟a中已壓合之電路板的兩表面係分別以相距於上述 電路板之第三、六層於3-llmil範圍内以絕緣材質壓合 > c.步驟b中已壓合之電路板之兩表面係分別以相距於上述 電路板之第二、七層於3-9mil範圍内以絕緣材質壓合； ___ 第6頁 本紙张欠度適( CNS ) Λ4規格（2!ΟΧ 297公犛） -- 1 ------- I I HL I I - I - K - I . !1- n I I - ------ I I t U5, --° (誚先閱讀背面之;1意事項再項{:1,)冬頁) 448 70 7 A7 ___B7_____ 五、發明說明（4 ) 及 d·步驟C中已壓合之電路板之兩表面係分別以相距於上述 電路板之第一、八層於2. 5-6_ 5mil範圍内以絕緣材質壓 合。 5 本發明八層電路板結構，其中該電路板之第一、三、 六及八層為訊號走線層，第二、四及七層為接地層，第五 層則為電源層’且該電路板之第四層與第五層之間係夾設 有—第一絕緣層’其厚度係在2-6mil範圍内；該電路板之 第三層與第四層之間及第六層與第五層之間分別夾設有一 10第一絕緣層，其厚度係在3-llmil範圍内；該電路板之第二 層與第二層之間及第七層與第六層之間分別夹設有一第三 絕緣層，其厚度係在3-9mil範圍内；該電路板之第一層與 第二層之間及第八層與第七層之間分別夾設有一第四絕緣 層’其厚度係在2. 5-6. 5mi 1範圍内。 15 有關本發明為達上述目的、特徵所採用的技術手段及 其功效’茲例舉較佳實施例並配合圖式說明如下： 第一圖係習知八層電路板之各層間的壓合及厚度示意 圖。 ’ 第二囷係本發明較佳實施例之各層間的壓合及厚度示 20 意圖。 第三圖係本發明較佳實施例八層電路板之部分剖面圖。 第四圖係本發明較佳實施例八層電路板之部分剖面圖。 【本發明之元件符號對照表】 GND接地層（第二、四、七層） _ 笫7頁 !裝--------訂- (請先閱讀背面之注意事項再填寫本頁) ^48707 、三、六、八層） A7 B7 五、發明說明（5 )4S707 ------------- -------------- V. Description of the invention (1 屮 K i?; /; F • price 'This invention provides An eight-layer circuit board pressing method and its finished product, in particular a circuit board capable of achieving impedance matching between the inner and outer layers of the circuit board to reduce high-speed signal reflection and electromagnetic interference. Press, please refer to the first figure, which is A schematic diagram of the arrangement of layers of a five-eight-layer circuit board with a conventional board thickness of 12 mm. As shown in the figure, the first, third, sixth, and eight layers of the circuit board are signal wiring layers S1, S2, S3, and S4. The second, fourth, and seventh layers are the ground layer GND, and the fifth layer is the power layer power, and the first layer si and the eighth layer S4 are also parts layout layers. Among them, the fourth and fifth layers of the circuit board There is a first insulating layer with a thickness of 8 mil, and a second insulating layer with a thickness of 5 mil is pressed between the third and fourth layers and between the sixth and fifth layers of the circuit board. A third insulation layer with a thickness of 8 mi and 1 layer is laminated between the second layer and the third layer and between the seventh layer and the sixth layer of the circuit board, and between the first layer and the second layer of the circuit board and Between the eight layers and the seventh layer, there is a 2.5 m 1 thick fourth insulating layer. Furthermore, the material of the second insulating layer and the fourth insulating layer is a polyester film (ρ · ρ.). The material of the first insulating layer and the third insulating layer is a paper, glass fiber or the like (coor); and as described above, the pressing method between the various layers will make the first layer W to the first layer. The resistance value of the second layer GND Rs 1 = the resistance value of the eighth layer S4 to the seventh layer GND Rs4 and 44 ohms. The resistance value of the third layer S2 to the second layer GND and the fourth layer GND Rs2 = The resistance value of the sixth layer S3 to the fifth layer and the seventh layer GND is Rs 3 55 ohms. However, the conventional press-fit structure has the following disadvantages: 1. High-speed signal reflection is serious. This type of circuit board is at high speed. When the signal is transmitted, the impedance value of its transmission line is set on page 4 15 20 _ >, paper scales are described as CNB Λ4 is present (210X297) _ but read the precautions on the back first -'11 70 7 A7 B7 V. Description of the invention (2) (诮 Read the notes of the back! &Amp; then fill in this million] plan, which is the impedance between layers According to the specifications set by Intel, the theoretical value should preferably be 55Ω ± 10%, which is preferably between 49.5Ω ~ 60. 5Ω, but the result calculated by the conventional circuit board, among which the first layer board S1 (Outer board) and eighth board S4 (outer board) impedance values Rsl and Rs4 5 are equal to 44Ω, and the third and sixth board S2 (inner board) and sixth board S3 (inner board) impedance values Rs2 and Rs3 are equal to 55Ω, that is, Rsl = Rs4 = 44Ω, Rs2 = Rs3 = H _Ω, the impedance difference between the inner and outer layers is as high as 11 ohms, and this inner and outer layer is blocked. The gap will cause impedance mismatch, so when a high-speed signal is here-Thunder When transmitting in the fascia, the high-speed signal passes from the outer layer, that is, the component layout layer (such as the 10th or eighth layer) to the inner layer (such as the third-layer board, six-drawer, etc.). Signal reflection, resulting in poor signal transmission quality: Right here we can calculate the reflection coefficient of the high-speed signal as ρ ZO1 — Zo __ Rs \ — RsT, n ι τ ί =-二 --- IJ 丄 丄 l Ο ZUZo Rsl + Rs2 '2. The magnetic flux cancellation becomes worse. 15 The aforementioned reflection of the high-speed signal will generate a standing wave, and the standing wave will increase. The high-speed signal of electromagnetic radiation, so that the magnetic flux offset by deterioration caused by electromagnetic interference through the Bureau. Therefore, if the first, third, sixth, and eighth layers of the circuit board can be used as the signal routing layers SI, S2, S3, and S4, the relative impedance values RS1, RS2, Rs3, and Rs4 are closer to 20, which will reduce the reflection coefficient. It further reduces electromagnetic wave interference, which is further suitable for high-speed lines, which increases the use value of the product; and because the impedance has been controlled, it is not necessary to change the trace width when the traces are routed to different layers when the circuit board is laid out. Therefore, the timeliness of the layout can be improved. ___Page 5 This paper recognizes medium scale 1¾ National Standard (CNS) Λ4 specification (210x2h revolution 1 ------- Α7 Β7 The main method of the present invention and its finished product ore make the signal routing layer impedance of each layer Matching, thereby reducing the high-speed signal fiber and electromagnetic wave interference, the circuit board is suitable for high 448 70 7 V. Description of the invention (3) The disadvantages of the knowledge are that the inventor has accumulated years of experience in this ::: experience 'active research There is finally the invention of the "eight-layer circuit board alpha method and its finished product". 'It is an eight-layer circuit board pressing speed signal.' The main feature of the present invention is that each first insulating layer The thickness is in the range of 2-6 mil ', the thickness of each-the second insulation layer is within the range of 10, and the thickness of each third insulation layer is in the range of 3 to 9 mil ^; and the thickness of each fourth insulation layer is In the range of 2.5-6 · 5mil; this can match the impedance of the signal routing layers of each layer, thereby reducing the reflection and electromagnetic interference of high-frequency signals, so that the circuit board is suitable for the deployment of high-speed signals. 爰 Yes, in order to achieve the above For the purpose, the eight-layer circuit board of the present invention is laminated 15 method 'wherein the first, third, sixth and eighth layers of the circuit board are signal wiring layers, the second, fourth and seventh layers are ground layers, and the fifth layer is a power layer; the method includes the following steps: a. The fourth layer of the above circuit board is laminated with an insulating material within a range of 2_6mn from the fifth layer; 20 b. The two surfaces of the circuit board which have been laminated in step a are separated from each other by the third, Six layers are laminated with insulating material within the range of 3-llmil> c. The two surfaces of the circuit board that has been laminated in step b are separated from the second and seventh layers of the above circuit board within the range of 3-9mil. The insulation material is laminated; ___ page 6 The paper is not suitable (CNS) Λ4 specification (2! 〇Χ 297 公 牦)-1 ------- II HL II-I-K-I.! 1- n II------- II t U5,-° (诮 Read the back of the book first; 1 item and then the item (: 1,) winter page) 448 70 7 A7 ___B7_____ V. Description of the invention (4) and d · The two surfaces of the pressed circuit board in step C are laminated with insulating materials within the range of 2. 5-6_ 5mil from the first and eight layers away from the above circuit board, respectively. 5 The eight-layer circuit board structure of the present invention, wherein the first, third, sixth and eighth layers of the circuit board are signal routing layers, the second, fourth and seventh layers are ground layers, and the fifth layer is a power layer 'and the The fourth layer and the fifth layer of the circuit board are interposed therebetween-the first insulating layer 'has a thickness in the range of 2-6mil; the third and fourth layers of the circuit board and the sixth layer and A 10 first insulating layer is sandwiched between the fifth layer, and its thickness is in the range of 3-llmil; the second and the second layer of the circuit board and the seventh and the sixth layer are respectively sandwiched A third insulating layer is provided, the thickness of which is in the range of 3-9mil; a fourth insulating layer is sandwiched between the first layer and the second layer and between the eighth layer and the seventh layer of the circuit board. The thickness is in the range of 2. 5-6. 5mi 1. 15 The technical means adopted by the present invention to achieve the above-mentioned objects and features, and their effects, are described below with reference to the preferred embodiments and the drawings: The first figure is the conventional press-fitting between layers of an eight-layer circuit board and Schematic of thickness. ′ The second aspect is the intention of the lamination and thickness between the layers in the preferred embodiment of the present invention. The third figure is a partial cross-sectional view of an eight-layer circuit board according to a preferred embodiment of the present invention. The fourth figure is a partial cross-sectional view of an eight-layer circuit board according to a preferred embodiment of the present invention. [Comparison table of component symbols of the present invention] GND ground layer (second, fourth and seventh layers) _ 页 7 pages! Installation -------- order-(Please read the precautions on the back before filling this page) ^ 48707, 3rd, 6th and 8th floors) A7 B7 V. Description of the invention (5)
Power電源層（第五層） SI、S2、S3、S4訊號走線層（第 HI、H2、H3、H4絕緣層之厚度 首先，請參考第二圖所示，本發明係為—八層電路板 5 ，其板厚係在0. 7-1. 7 mm之間，在此係以板厚1. 2_之八 層電路板作為較佳實施例之說明，本發明之八層電路板係 包括了四層訊號走線層SI、S2、S3及S4，三層接地層GND ，一層電源層Power，及分別失置於兩兩相鄰電路板間的 絕緣層，茲分述如后，其中： 10 該電路板之第一、三、六及八層為訊號走線層SI、S2 、S3及S4，且訊號走線層SI ' S2、S3、S4多利用銅鉑， 且第一層S1及苐八層S4係供電子零件佈設； 第二、四及七層為接地層GND ; 第五層則為電源層Power ; 15 在該電路板之第四層與第五層之間係夹設有〜第—絕 緣層’其厚度為H1 ’且該第一絕緣層所使用的材質係為紙 質、玻璃纖維之類的基材（core); 在該電路板之第二層與第四層之間及第六層與第五層 之間分別夾設有一第二絕緣層，其厚度為H2，且软第二絕 2〇 緣層所使用的材質係為聚s旨勝片（prepreg); 在該電路板之第二層與第三層之間及第七層與第六層 之間分別夾設有一第三絕緣層，其厚度為H3 ’且該室= X乐二絕 緣層所使用的材質係為紙質、玻璃纖維之類的基松 ^ ^ core 第8頁 本紙張尺度通用中囵國家標.準（CNS)A.丨規格（2〗〇 X 297公爱 ---------- ---------訂· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 );及 44870 Λ7 B7 經 濟 邨 智 慧 財 產 局 員 工 消 t 合 作 社 印 製 五、發明說明（6 ) 在該電路板之第一層與第二層之間及第八層與第七層 之間分別夾設有一第四絕緣層，其厚度為H4，且該第四絕 緣層所使用的材質係為聚酯膠片（prepreg)。 誠如本案發明背景中所述，電路板之各該訊號走線層 5 SI、S2、S3、S4之相對阻抗值最好相等或相近，且最好在 於Intel規定之高速線路理論阻抗值49.5〜59.5歐姆内， 本發明人發現可藉由改變各絕緣層之厚度而使各該訊號走 線層SI、S2、S3、S4之相對阻抗值隨之改變，進而達到各 層阻抗匹配之目的；又因八層電路板的壓合方法，首先為 第四層與第五層之間夾置第一絕緣層壓合，接著第三層與 第四層之間及第六層與第五層之間分別夾置第二絕緣層後 壓合’並且第二層與第三層之間及第七層與第六層之間分 別夾置第三絕緣層後壓合，最後在第一層與第二層之間及 第八層與第七層之間分別夾置有一第四絕緣層壓合後構成 八層電路板，故若使兩第二絕緣層的厚度相同兩第三絕緣 層及兩第四絕緣層之厚度亦相同不僅製造上較為方便，亦 較符合現今的製造方式，為使本發明更加容易明瞭，故藉 由下列之公式來大致說明本發明之研發過程： 首先，請配合參閱第三圖所示，電路板外層之相對阻 抗值即為第一訊號走線層S1相對於接地層GND (即電路板 第二層）之阻抗值Rsl，或為第八訊號走線層S4相對於接 地層⑽（即電路板第七層）之阻抗值Rs4，故可利用下列 公式1求出阻抗值Rsl (或Rs4 ’由於兩第四絕緣層厚度相 10 15 20 第9頁 本紙張尺度適用中國國家標準（CNS)Al規格 ---------- it--------訂· C請先閱讀背面之注咅？事項再填窝本頁> ^ 48 70 7 A7 五、發明說明（7 ) 同，是以Rsl=Rs4) 87Power power layer (fifth layer) SI, S2, S3, S4 signal wiring layer (thickness of HI, H2, H3, H4 insulation layer) First, please refer to the second figure, the invention is an eight-layer circuit Board 5, the thickness of which is between 0. 7-1. 7 mm, here is a description of the preferred embodiment of the eight-layer circuit board with a plate thickness of 1.2_, the eight-layer circuit board of the present invention It includes four signal routing layers SI, S2, S3, and S4, three ground layers GND, one power layer Power, and insulation layers that are lost between two adjacent circuit boards, respectively. : 10 The first, third, sixth and eighth layers of the circuit board are signal wiring layers SI, S2, S3, and S4, and the signal wiring layers SI 'S2, S3, and S4 mostly use copper and platinum, and the first layer S1 The second and fourth layers are the ground layer GND; the fifth layer is the power layer Power; 15 is sandwiched between the fourth and fifth layers of the circuit board Yes ~ The first insulation layer 'its thickness is H1' and the material used for the first insulation layer is paper, glass fiber or the like (core); the second and fourth layers of the circuit board A second insulating layer is sandwiched between the sixth layer and the fifth layer, the thickness of which is H2, and the material used for the soft second insulating 20 edge layer is a prepreg; A third insulating layer is sandwiched between the second layer and the third layer and between the seventh layer and the sixth layer of the circuit board, and the thickness is H3 ', and the chamber = X Le Er insulating material It is based on paper, glass fiber, etc. ^ ^ core Page 8 This paper is a standard of China National Standard. Standard (CNS) A. 丨 Specifications (2) 〇X 297 Public Love -------- ---------- Order (Please read the notes on the back before filling this page) (Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs); and 44870 Λ7 B7 Cooperative printed 5. Description of the invention (6) A fourth insulating layer is sandwiched between the first layer and the second layer and between the eighth layer and the seventh layer of the circuit board, and the thickness is H4, and the The material used for the fourth insulating layer is prepreg. As described in the background of the present invention, each of the signal wiring layers of the circuit board 5 SI The relative impedance values of S2, S3, and S4 are preferably equal or similar, and preferably within the theoretical impedance value of 49.5 ~ 59.5 ohms specified by Intel for the high-speed line. The inventors have found that by changing the thickness of each insulating layer, The relative impedance values of the signal routing layers SI, S2, S3, and S4 change accordingly, thereby achieving the purpose of impedance matching of each layer; and because of the pressing method of the eight-layer circuit board, the first is the sandwich between the fourth layer and the fifth layer The first insulating laminate is laminated, and then the second insulating layer is sandwiched between the third and fourth layers and between the sixth and fifth layers, respectively, and the two layers are pressed together. A third insulating layer is sandwiched between the seventh layer and the sixth layer and then pressed, and finally a fourth insulating laminate is sandwiched between the first layer and the second layer and between the eighth layer and the seventh layer. Eight layers of circuit boards are formed after being combined, so if the thicknesses of the two second insulating layers are the same, the thicknesses of the two third insulating layers and the two fourth insulating layers are not only more convenient in manufacturing, but also more in line with the current manufacturing methods. The present invention is easier to understand, so it is roughly described by the following formula The research and development process of the present invention: First, please refer to the third figure. The relative impedance value of the outer layer of the circuit board is the impedance value Rsl of the first signal trace layer S1 relative to the ground layer GND (ie, the second layer of the circuit board). , Or the resistance value Rs4 of the eighth signal trace layer S4 relative to the ground plane ⑽ (ie, the seventh layer of the circuit board), so the following formula 1 can be used to obtain the resistance value Rsl (or Rs4 'due to the thickness of the two fourth insulation layers) Phase 10 15 20 Page 9 This paper size is applicable to China National Standard (CNS) Al specifications ---------- it -------- Order · C Please read the note on the back first? Matters refill this page> ^ 48 70 7 A7 V. Description of the invention (7) Same as Rsl = Rs4) 87
In 5.98//4 4er+\m l〇_8妒+Π .公式1 15 其t :ER =介電係數=4. 5 H4 =第四絕緣層之厚度 W =線寬’線寬可為2_8niii，在此係以5rail作 為較佳實施例之說明 T1 —第一仏號走線層S1的厚度= i.4mil 在本發明較佳實施例中，電路板各層的厚度除外層（ 即為第一訊號走線層S1及第八訊號走線層之S4)的厚彦 為1· 4mil，其他各層的厚度皆為〇, 7mii ;電路板之内層之 相對阻抗即為第二訊號走線層S2相對於接地層GND (電路 板第二層）與接地層GND (電路板第四層）之相對阻抗 ，或為第三訊號走線層S3相對於電源層PoweF (電路板第 五層）與接地層GND (電路板第七層）之相對阻抗Rs3,再 利用下列公式2求出阻抗值Rs2 (或rs3，由於兩第二絕緣 層之厚度H2相同’是以Rs2=Rs3 )，並請一併參閱第四圖所 -----------R.--------訂 (請先閱讀背面之注意ί項再填寫本頁) 經濟部智慧財產局員工消費合作社印*1^ 20 RS2In 5.98 // 4 4er + \ ml〇_8 jealousy + Π. Formula 1 15 Its t: ER = dielectric constant = 4. 5 H4 = thickness of the fourth insulating layer W = line width 'line width can be 2_8niii, in This is a description using 5rail as the preferred embodiment. T1—the thickness of the first trace line layer S1 = i.4mil. In the preferred embodiment of the present invention, the thickness of each layer of the circuit board is excluded (that is, the first signal trace). The thickness of the wire layer S1 and the eighth signal wiring layer S4) is 1.4mil, and the thickness of the other layers is 0,7mii; the relative impedance of the inner layer of the circuit board is the second signal wiring layer S2 relative to the ground layer The relative impedance between GND (the second layer of the circuit board) and GND (the fourth layer of the circuit board), or the third signal routing layer S3 relative to the power layer PoweF (the fifth layer of the circuit board) and the ground layer GND (the circuit Board seventh layer) relative impedance Rs3, and then use the following formula 2 to find the impedance value Rs2 (or rs3, because the thickness H2 of the two second insulation layers are the same 'is Rs2 = Rs3), and please also refer to the fourth figure ------------ R .-------- Order (please read the note on the back first and then fill out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs * 1 ^ 20 RS2
In- 4(//3+ g2) 0.67^fF| 0.8 + ZZ V w …公式2 示，其中：ER=介電值係數=4.5 H2=第二絕緣層厚度 H3 =第三絕緣層厚度 T2=第二訊號走線層之厚度=〇. 7mil 第10頁 本紙張尺度適用中0國家標.準（CNS)/y規格（210 X 297公釐） Η A7 B7 五 、發明說明（ w=線寬，線寬可為2-8mil，在此係以5n]il作 為較佳實施例之說明In- 4 (// 3+ g2) 0.67 ^ fF | 0.8 + ZZ V w… Equation 2 is shown, where: ER = dielectric value coefficient = 4.5 H2 = thickness of the second insulating layer H3 = thickness of the third insulating layer T2 = The thickness of the second signal trace layer = 0.7mil. Page 10 This paper is applicable to the national standard of 0. Standard (CNS) / y (210 X 297 mm) Η A7 B7 V. Description of the invention (w = line width , The line width can be 2-8mil, here is 5n] il as a description of the preferred embodiment
2m+im + 2H2 + IHl + m + βΤ2 = 4S.6mil· 此外，電路板之總厚度必須為l‘2mm (即為48mil)或 在其誤差範圍内，亦可說如公式3所表示，本發明人利用 上列之方式，求出本發明之較佳實施例： 即虽第一絕緣層的厚度在2-6mi 1範圍内，在此以 Hl=4mi 1 為佳； 第二絕緣層的厚度H2在3-Umil範圍内，以H2 = 7mil 為佳； 第一絕緣層的厚度H3在3~9mil範圍内，以H3=6mii 為佳；及 I :裝--- 〈靖先閱續背面之注意事項再填寫本頁) 訂_ 經濟部智慧財產局員工消費合作社印製 第四絕緣層的厚度H4在2 5_6· 5mi 1範圍内，以 H4=4. 5mi 1 為佳； 此時，第一訊號走線層S1相對於接地層GND (電路板 15第二層）之阻抗值Rsl等於第四訊號走線層S4相對於接 地層GND (電路板第七層）之阻抗值Rs4=58歐姆，即Rsi = Ε§4·ϊ=58Ω (外層阻抗）;而第二訊號走線層S2相對於二接 地層GND (電路板第二及第四層）之相對阻抗Rs2等於第 二訊號走線層S3相對於電源層p〇wer (電路板第五層）與 20接地層GND (電路板第七層）之相對阻抗RS3等於52歐姆 ’即-R@=Rs3^~5担（阻抗）;該等阻抗值全部都落在55 Ω ±10%的範圍内，且内、外層板阻抗僅相差 6歐姆，為習 第11頁 本紙張尺度適用中國國家標準（CNS)A.丨規格（210 x 297公餐） U 4β 70 i A7 B7 五、發明說明（9 ) 知者的一半。 且符合 2H4+2H3+2H2+1H1+2T1+6T2=2X4.5 mil +2X6 mil + 2x7 mil + lX4 mil + 2xl.4 mi 1 +6 X 0. 7mi 1 =46mil 与1. 2mm (在容許誤差内）。 5 綜上所述，本發明之『八層電路板壓合方法及其成品 t’確能藉上述所揭露之方法，製造出具有下列優點的 路板： 1.降低高速訊號之反射 在本發明較佳實施例中，Rs1=Rs4=58D，Rs2=Rs3=52 ι〇 Ω，該等阻抗值全部都落在55Ω ±10%的範圍内，且内、 外層板阻抗僅相差6歐姆，為習知板厚1 · 2mm八層電路 板的一半，反射係數亦明顯降低為習知者的一半，反射 係數僅0. 054，是以’高速訊號反射之情形明顯降低，更 適於高速訊號行走。 15 2.降低電磁波干擾 由於高速訊號反射的情形明顯改善、降低了，所以較 不會產生駐波’進而使其磁通抵消作用較佳，電磁波干 擾情形降低，而得以符合目前之EMI標準。 經濟部智慧財產局員工消費合作社印製 -----------裝--------訂· (請先閱讀背面之注意事項再填寫本頁) 3.適用於高速訊號佈局 2〇 誠如前述，由於藉由本發明之壓合方法得以降低高 速訊號之反射’進而降低電磁波干擾，使高速訊號行走 不會產生問題，故適用於高速訊號佈局，而得以因應配 合現今電路板製造業往高速訊號發展的趨勢，提升產品 的利用價值及競爭力。 第12頁 本紙張尺度適闬中國國家標準（CNS)A-!規格（210 X 297公餐） 4^8 7〇 10 A7 五、發明說明（w ) 4·提高佈局之時效性 佈局時’在走線由外層穿至内層的情況下，因各絕 緣層之厚度固定及内、外層之相對阻抗已經達到阻抗匹 配’所以不需改變走線線寬，即可達到阻抗控制的效果 ’進而使佈局的時效性提高。 本案申請前未見於刊物亦未公開使用，符合發明專利 之新穎、進步等要件。 惟’上述所揭之圖式及說明，僅為本發明之實施例而 已’非為限定本發明之實施；大凡熟悉該項技藝之人仕， 其所依本發明之特徵範疇，所作之其他等效變化或修飾， 皆應涵蓋在以下本案之申請專利範圍内。 (請先閱讀背面之注意事項再填寫本頁) 裝 5 Ί-SJ. 經濟部智慧財產局員工消費合作社印製 ο 2 本紙張尺度適用中國國本標準（CNS)A-丨規格（2]〇 X 297公Μ )2m + im + 2H2 + IHl + m + βΤ2 = 4S.6mil · In addition, the total thickness of the circuit board must be l'2mm (that is, 48mil) or within its error range. It can also be said that as shown in Equation 3, this The inventor uses the methods listed above to find a preferred embodiment of the present invention: that is, although the thickness of the first insulating layer is in the range of 2-6 mi 1, it is better to use H1 = 4 mi 1 here; the thickness of the second insulating layer H2 is in the range of 3-Umil, preferably H2 = 7mil; the thickness of the first insulating layer H3 is in the range of 3 to 9mil, and H3 = 6mii is preferred; and I: installation --- Please fill in this page again) Order _ The thickness of the fourth insulation layer H4 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is in the range of 2 5_6 · 5mi 1, and H4 = 4.5 mi 1 is preferred; at this time, the first The resistance value Rsl of the signal routing layer S1 relative to the ground layer GND (the second layer of the circuit board 15) is equal to the resistance value Rs4 of the fourth signal routing layer S4 relative to the ground layer GND (the seventh layer of the circuit board) = 58 ohms. That is, Rsi = Ε§4 · ϊ = 58Ω (outer layer impedance); and the relative impedance Rs2 of the second signal trace layer S2 relative to the two ground layers GND (the second and fourth layers of the circuit board), etc. The relative impedance of the second signal routing layer S3 relative to the power supply layer power (the fifth layer of the circuit board) and the 20 ground layer GND (the seventh layer of the circuit board) RS3 is equal to 52 ohms, that is -R @ = Rs3 ^ ~ 5 All of these impedance values fall within the range of 55 Ω ± 10%, and the impedance of the inner and outer plates differ only by 6 ohms. For the purpose of page 11, this paper standard applies Chinese National Standard (CNS) A.丨 Specifications (210 x 297 meals) U 4β 70 i A7 B7 V. Description of the invention (9) Half of the knowers. 2H4 + 2H3 + 2H2 + 1H1 + 2T1 + 6T2 = 2X4.5 mil + 2X6 mil + 2x7 mil + lX4 mil + 2xl.4 mi 1 +6 X 0.7 mi 1 = 46mil and 1.2mm (within tolerance Inside). 5 In summary, the "eight-layer circuit board pressing method and its finished product t" of the present invention can indeed use the methods disclosed above to manufacture a road board with the following advantages: 1. Reduce the reflection of high-speed signals in the present invention In the preferred embodiment, Rs1 = Rs4 = 58D, Rs2 = Rs3 = 52 μmΩ, all of these impedance values fall within the range of 55Ω ± 10%, and the impedance of the inner and outer plates differ only by 6 ohms. Knowing that the thickness of the half-layer circuit board is 1-2mm, the reflection coefficient is also significantly reduced to half that of a conventional person, and the reflection coefficient is only 0.554, which is significantly reduced in the case of 'high-speed signal reflection, which is more suitable for high-speed signal walking. 15 2. Reduction of electromagnetic wave interference Since the situation of high-speed signal reflection is significantly improved and reduced, standing waves are less likely to be generated, and the magnetic flux cancellation effect is better, and the electromagnetic wave interference situation is reduced to meet current EMI standards. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ---------------------------- Order (please read the precautions on the back before filling this page) 3. Suitable for high speed Signal layout 20 As mentioned above, because the high-speed signal reflection can be reduced by the compression method of the present invention, thereby reducing electromagnetic wave interference, so that high-speed signal walking will not cause problems, it is suitable for high-speed signal layout, and can be adapted to match current circuits. The development trend of the board manufacturing industry towards high-speed signals increases the utilization value and competitiveness of products. Page 12 This paper is suitable for Chinese National Standard (CNS) A-! Specifications (210 X 297 meals) 4 ^ 8 7〇10 A7 V. Description of invention (w) 4 · Improve the timeliness of layout When the traces are routed from the outer layer to the inner layer, because the thickness of each insulation layer is fixed and the relative impedances of the inner and outer layers have reached impedance matching, so the effect of impedance control can be achieved without changing the width of the traces, thereby making the layout Improved timeliness. This case has not been seen in publications or used publicly before the application, which meets the requirements for novelty and progress of invention patents. However, the above-mentioned disclosed drawings and descriptions are merely examples of the present invention, and are not intended to limit the implementation of the present invention. Anyone who is familiar with the technology can make other things based on the features and scope of the present invention. All changes or modifications shall be covered by the scope of patent application in the following case. (Please read the precautions on the back before filling this page) Pack 5 Ί-SJ. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ο 2 This paper size applies to China's National Standard (CNS) A- 丨 specifications (2). X 297mm)