448 7 1 0 A7 B7 * I •一 — I I > .. _ 五、發明说明（1 ) — 本發明係提供一種八層電路板之壓合方法及其結構 特別是指一種能達到電路板内外層阻抗匹配，以降低高速 信號反射及電磁干擾之電路板者。 i · —I- - n -.n ii - i -- · I - I 1— m I - I X 爿彳 •y**' (讀先閱讀背面之注意事項再填K-本頁) 按，一般傳統八層電路板1之各層排列方式係如第一 5圖所示，其中由上而下該電路板之第一、三、六及八層板 分別為訊號走線層SI、S2、S3及S4，第二、四及七層板 分別為接地層GND，且第五層板為電源層PWR，而且第 一層板S1及第八層板S4亦為零件佈設層；其中，於該 第四層板GND與第五層板PWR之間係壓合有一厚度為 10 8mil之第一絕緣層2,該第四層板GND與第三層板S2及 第五層板PWR與第六層板S3之間分別壓合有一厚度為 5mU之第二絕緣層3，該第三層板S2與第二層板GND及 第六層板S3與第七層板GND之間分別壓合有一厚度為 8mil之第三絕緣層4,且該第二層板GND與第一層板S1 15 及第七層板與第八層板之間分別壓合有一厚度為9.5mil 之第四絕緣層5，而且，該第一絕緣層2與第三絕緣層4 係為一膠片（P.P) ’該第二絕緣層3與第四絕緣層係為一 基材（core);而以如上所述之各層板間的壓合方式會得到 第一層板S1對第二層板GND之阻抗值RS1 =第八層板S4 20 對第七層板GND之阻抗值Rs4与76.4歐姆，第三層板S2 對第二層板GND及第四層板GND之阻抗值Rs2=第六層 板S3對第五層板PWR及第七層板GND之阻抗值Rs3与51 歐姆。由此我們可以看出，第一層板S1 (外層板）及第八 層板S4(外層板）之阻抗值Rsl及RS4分別與第三層板 第4頁 本紙張尺度適州中囡國家梯準（CNS > A4规格（2丨OX297公;t ) 44871 0 Α7 Β7 五、發明説明（2 ) S2(内層板）及第六層板S3(内層板）之阻抗值Rs2及Rs3相 差了 25.4歐姆，而此一内外層板阻抗之明顯差距則會造 成阻抗不匹配，以致一高速訊號在此一電路板中傳輸時， 當該高速訊號從外層，亦即零件佈設層（如第一層板51或 5第八層板S4)穿層走線至内層（如第三層板S2或苐六層板 S3)時，會導致該高速訊號因行經之内外層板的阻抗不匹 配而導致訊號反射，造成高速訊號之傳輪品質不良；在這 裡我們可以算出該高速訊號的反射係數為： p — ZI-Zo，Rsl - Rs2，q 21 + Zo Ssl + Rs2 而且’因為該尚速訊號於反射過程中會產生駐波，且 該持續產生之駐波會加強該南速訊號之電磁波輕射，而使 其磁通抵消作用變差，造成電磁波干擾。 另外，此種電路板在走高速訊號時，其傳輸線路之阻 抗值設計’亦就是層板與層板之間的阻抗值，依照Intel 15 設定之規格理論值應在55Ω ±10%左右最好，也就是在 49.5 Ω〜60.5 Ω附近，但由習知電路板所算出之外屠板， 即第一層板S1及第八層板S4之阻抗值Rsl(或Rs4) = 76.4 Ω，已超出此一範圍甚多，所以即使其内層板，即第三層 板S2及第六層板S3之阻抗值Ks2(或Rs3) = 51Q是在此一 20 範圍中’也因為内外層板之阻抗不匹配而會造成高速訊號 之反射，因此該電路板實不適於走高速訊號。 綜上所述，我們知道了高速訊號在電路板上傳輸時， 會造成高速訊號之訊號反射及產生電磁波干擾之原因，主 _ 第5頁 本紙張尺度適扣中國囤家標準（CNS ) Μ規格（210X297公釐） .—I - —I I— l·— I - - I 1- I - __ (誚先閱讀背面之注意事項4"巧各茛) 448 7 1 Ο A 7 —_______________Β7 五、發明説明（3 ) "" — 要是因為電路板之内外層板阻抗不匹配所導致，故針對上 述習知八層電路板之缺失，是以，本案創作人以累積多年 {誚先閲讀背面之注意事項再"寫本頁) 經驗，積極研究，以創作一適於走高速訊號之八層電路板 為目標’終有本發明『八層電路板之壓合方法及其結構』 5 之產生。 本發明之主要目的係提供一種八層電路板之壓合方法 及其結構，使内外層板能達到阻抗匹配，而降低高速訊號 反射及電磁波干擾。 本發明係提供一八層電路板之壓合方法及其結構，該 1〇電路板之第一、三、六及八層板為訊號走線層，該第二、 四及七層板為接地層且該第五層板係為電源層，其中，該 第四層板與第五層板之間係壓合有一第一絕緣層；該第四 廣板與第三層板及第五層板與第六層板之間分別壓合有一 第二絕緣層；該第三層板與第二層板及第六層板與第七層 15板之間分別壓合有一第三絕緣層，且該第二層板與第一層 板及第七層板與第八層板之間分別壓合有一第四絕緣層； 而本發明之主要特徵係為：該第一絕緣層之厚度係在 4±2mil之間；該第二絕緣層之厚度係在11：fc4mn之間； 該第二絕緣層之厚度係在1 〇±3mil之間及該第四絕緣層之 20厚度係在5,5±2mil之間，使得該電路板之内外層板能達 到阻抗匹配’而降低高速訊號之訊號反射及電磁波干擾。 爰是，為達到上述目的，本發明係為一八層電路板之 壓合方法及其結構’其中，該電路板之第一、三、六及八 層板為訊被走線廣’該第二、四及七層板為接地層，且該 . _ 第6頁_ 本紙張尺度適用中囤囷家標準（CMS ) A4規格（210X297公廣) ' 448 7 1 〇 Α7 I___________ Β7 五、發明説明（4 ) {請先閱讀背面之注意事項再楨荇衣頁) 第五層板為電源層；其特徵在於該電路板之第四層板與第 五層板之間壓合有一厚度在4±2mil之間之第一絕緣層； 該第四層板與第三層板及第五層扳與第六層板之間分別壓 合有一厚度在ll±4mil之間之第二絕緣層；該第三層板與 5第二層板及第六層板與第七層板之間分別壓合有一厚度在 10±3mil之間之第三絕緣層，及該第二層板與第一層板及 第七層板與第八層板之間分別壓合有一厚度在5.5±2mil 之間之第四絕緣層。 有關本發明為達上述目的、特徵所採用的技術手段及 10 其功效，茲例舉較佳實施例並配合圖式說明如下： 第一圖係習知八層電路板之各層板間的壓合及絕緣層 厚度示意圖。 第二圖係本發明較佳實施例八層電路板之各層板間的 壓合及絕緣層厚度示意圖。 15 第三圖係本發明較佳實施例八層電路板之部分剖面 圖。 圖號元件對照表： 6 八層電路板 Si訊號走線層（第一層板） S2訊號走線層（第三層板）S3訊號走線層（第六層板） 20 S4訊號走線層（第八層板）gnd接地層 PWR電源層 61第一絕緣層 63第二絕緣層 65第三絕緣層 67 第四絕緣層 本發明對於板厚從1.1 mm〜2.1 mm範圍内之八層電路 ______第7頁 本紙張尺度適川中固國家標率（CNS ) Μ说格（210Χ297公缝） " 448 7 1 Ο Α7 ______________Β7_五'發明説明（5) — 板皆可適用而無虞，而在以下之實施例中，係以一板厚 1.6mm之八層電路板為本發明之較佳實施例而為之詳細說 明，惟其並非本發明之限制，凡熟習此項技藝者，根據本 發明之教示而為之變更實施亦均屬本發明之範疇。 5 首先請參考第二圖所示，係為本較佳實施例板厚 1.6mm之八層電路板6;其中：該電路板6由上而下排列， 係序為第一、三、六及八層板係為訊號走線層S卜S2、S3、 S4,該第二、四及七層板係為接地層GND，且該第五層 板係為電源層P WR，並且’該電路板6之第·一層板S1及 第八層板S4亦為零件佈設層；另外，在該第四層板GND 與第五層板PWR之間係夹設有一第一絕緣層61 ;在該第 四層板GND與第三層板S2及第五層板PWR與第六層板 S3之間係分別夾設有一第二絕緣層63 ;在該第三層板S2 與第二層板GND及第六層板S3與第七層板GND之間係 分別夾設有一第三絕緣層65，及在該第二層板GND與第 _層板S1及第七層板GND與第八層板S4之間係分別夾 設有一第四絕緣層67，而且，該第一絕緣層61與第三絕 緣層65係為一聚酯膠片（p_p)，該第二絕緣層63與第四 絕緣層67係為一基材（core)。 一般電路板層板與層板之間的阻抗值，通常是依照 Intel設定之規格理論值來設計，而設計以走高速訊號為 主之電路板’其層板與層板之間的阻抗值規格應設計在55 土10%Ω左右’才能符合局速線路的設計要求；並且為了改 善上述習知之缺失，使電路板之内外層板間的阻抗能夠匹 第8頁 ίο 15 20 本紙張尺度延用中囤國家標率（CNS)八4現格（21〇χ297公釐 I 1- I - I I - - -,+SL - I - - - I - - (f I I X· *-'B (对先閱讀背面之注意事項再填5-T本s ) 448 71 Ο Α7 _________Β7五、發明説明（6 ) 配’本創作人發現可以以調整各層板之間的絕緣層61、 63、65及67之厚度來改變層板與層板之間的阻抗值，而 使内外層板之阻抗值相等’以達到各層板間的阻抗匹配， 是以提出下列之計算公式： 公式一（求外層阻抗Rs 1及Rs4之計算公式）： 5448 7 1 0 A7 B7 * I • I — II & .. _ V. Description of the invention (1) — This invention provides an eight-layer circuit board pressing method and its structure, in particular, it can reach the inside and outside of the circuit board Layer impedance matching to reduce high-speed signal reflection and electromagnetic interference on the circuit board. i · —I--n -.n ii-i-· I-I 1— m I-IX 爿 彳 • y ** '(Read the precautions on the back and fill in the K-page) Press, General The arrangement of the layers of the traditional eight-layer circuit board 1 is shown in Figure 5; the first, third, sixth, and eight-layer boards of the circuit board from top to bottom are the signal routing layers SI, S2, S3, and S4, the second, fourth, and seventh layers are the ground layer GND, and the fifth layer is the power layer PWR, and the first layer S1 and the eighth layer S4 are also parts layout layers; A first insulating layer 2 having a thickness of 108 mil is laminated between the layer GND and the fifth layer PWR. The fourth layer GND and the third layer S2, and the fifth layer PWR and the sixth layer S3. A second insulation layer 3 with a thickness of 5mU is pressed between the third layer S2 and the second layer GND, and a sixth layer S3 and the seventh layer GND are each pressed with a thickness of 8mil. The third insulating layer 4 and a fourth insulating layer 5 having a thickness of 9.5 mil are respectively pressed between the second layer GND and the first layer S1 15 and between the seventh layer and the eighth layer. First insulating layer 2 and third insulating layer 4 It is a film (PP). The second insulating layer 3 and the fourth insulating layer are a core; and the first layer S1 to the second layer are obtained by the pressing method between the layers as described above. The resistance value of the layer GND RS1 = the resistance value of the eighth layer S4 20 to the seventh layer GND Rs4 and 76.4 ohms, the resistance value of the third layer S2 to the second layer GND and the fourth layer GND Rs2 = The resistance values Rs3 and 51 ohms of the sixth layer S3 to the fifth layer PWR and the seventh layer GND. From this we can see that the resistance values Rsl and RS4 of the first layer S1 (outer layer) and the eighth layer S4 (outer layer) are respectively the third layer and the fourth layer. Standard (CNS > A4 specification (2 丨 OX297); t) 44871 0 Α7 Β7 V. Description of the invention (2) The impedance values Rs2 and Rs3 of S2 (inner board) and S3 (inner board) differ by 25.4 Ohm, and the obvious difference between the impedance of the inner and outer layers will cause impedance mismatch, so that when a high-speed signal is transmitted in this circuit board, when the high-speed signal is transmitted from the outer layer, that is, the part layout layer (such as the first layer board) 51 or 5 Eighth layer board S4) When passing through the layer to the inner layer (such as the third layer board S2 or the six layer board S3), it will cause the high-speed signal to reflect the signal due to the impedance mismatch between the inner and outer board. , Resulting in poor transmission quality of high-speed signals; here we can calculate the reflection coefficient of this high-speed signal as: p — ZI-Zo, Rsl-Rs2, q 21 + Zo Ssl + Rs2 and 'because the high-speed signal is in the reflection process A standing wave will be generated in the medium, and the continuously generated standing wave will strengthen the power of the South Speed signal. The magnetic wave is lightly emitted, which makes its magnetic flux cancellation effect worse, which causes electromagnetic wave interference. In addition, when this circuit board is used at high speed signals, the impedance design of the transmission line is' the impedance value between the laminate and the laminate According to the specifications set by Intel 15, the theoretical value should be about 55Ω ± 10%, which is around 49.5 Ω ~ 60.5 Ω, but it is calculated by the conventional circuit board, that is, the first layer S1 and the first layer The resistance value Rsl (or Rs4) of the eight-layer board S4 = 76.4 Ω, which is far beyond this range, so even the inner layer boards, namely the third-layer board S2 and the sixth-layer board S3, have an impedance value Ks2 (or Rs3). = 51Q is in this range of 20 '. Also because of the impedance mismatch between the inner and outer layers, high-speed signals will be reflected, so this circuit board is not suitable for high-speed signals. In summary, we know that high-speed signals are in the circuit. When transmitting on the board, it will cause the reflection of high-speed signals and the cause of electromagnetic wave interference. _ Page 5 The paper size is suitable for the Chinese storehouse standard (CNS) M specification (210X297 mm). —I-—II— l · — I--I 1- I-__ (诮 read the back first Precautions 4 " Qiaoge buttercups) 448 7 1 Ο A 7 —_______________ Β7 V. Description of the invention (3) " " — If it is caused by the impedance mismatch between the inner and outer layers of the circuit board, the eight layers of the above-mentioned conventional knowledge The lack of circuit boards is based on the fact that the creators of this case have accumulated years of experience (诮 read the precautions on the back and then write this page) and actively research to create an eight-layer circuit board suitable for high-speed signals. Eventually, the "compression method and structure of an eight-layer circuit board" 5 of the present invention will be produced. The main object of the present invention is to provide an eight-layer circuit board pressing method and structure, so that the inner and outer layer boards can achieve impedance matching, and reduce high-speed signal reflection and electromagnetic wave interference. The invention provides a pressing method and structure of an eight-layer circuit board. The first, third, sixth, and eight-layer boards of the 10-circuit board are signal wiring layers, and the second, fourth, and seventh-layer boards are connected. The ground layer and the fifth layer are the power layer, wherein a first insulating layer is laminated between the fourth layer and the fifth layer; the fourth wide plate, the third layer, and the fifth layer A second insulating layer is pressed between the sixth layer and the sixth layer; a third insulating layer is pressed between the third layer and the second layer, and the sixth layer and the seventh layer 15 are respectively pressed, and the A fourth insulating layer is respectively pressed between the second layer, the first layer, and the seventh layer and the eighth layer. The main feature of the present invention is that the thickness of the first insulating layer is 4 ± 2mil; the thickness of the second insulation layer is between 11: fc4mn; the thickness of the second insulation layer is between 10 ± 3mil and the 20th thickness of the fourth insulation layer is 5,5 ± 2mil This makes it possible to achieve impedance matching between the inner and outer layers of the circuit board and reduce signal reflection and electromagnetic interference from high-speed signals. That is, in order to achieve the above-mentioned object, the present invention is a method and structure for laminating an eight-layer circuit board. Among them, the first, third, sixth, and eight-layer boards of the circuit board are widely used. The second, fourth, and seventh layers are grounding layers, and this. _ Page 6 _ This paper size is applicable to the CMS A4 specification (210X297 public) 448 7 1 〇Α7 I___________ Β7 5. Description of the invention (4) {Please read the precautions on the back first, and then close the clothing page) The fifth layer is the power supply layer; it is characterized in that the thickness between the fourth layer and the fifth layer of the circuit board is 4 ± A first insulating layer between 2 mils; a second insulating layer with a thickness of ll ± 4 mils is pressed between the fourth layer and the third layer and between the fifth layer and the sixth layer; A third insulating layer with a thickness of 10 ± 3 mil is pressed between the three-layer board and the second second board, the sixth layer and the seventh board, and the second board and the first board and A fourth insulating layer with a thickness between 5.5 ± 2 mils is laminated between the seventh layer and the eighth layer. Regarding the technical means adopted by the present invention to achieve the above-mentioned objectives, features, and its effects, the preferred embodiments are illustrated with drawings to illustrate the following: The first diagram is the compression of the layers of the conventional eight-layer circuit board. And insulation layer thickness. The second figure is a schematic diagram of the pressure bonding and the insulation layer thickness between the various layers of the eight-layer circuit board according to the preferred embodiment of the present invention. 15 The third diagram is a partial cross-sectional view of an eight-layer circuit board according to a preferred embodiment of the present invention. Figure number component comparison table: 6 eight-layer circuit board Si signal wiring layer (first layer board) S2 signal wiring layer (third layer board) S3 signal wiring layer (sixth board) 20 S4 signal wiring layer (Eighth layer board) GND ground layer PWR power layer 61 first insulating layer 63 second insulating layer 65 third insulating layer 67 fourth insulating layer The present invention is applicable to eight-layer circuits with a plate thickness ranging from 1.1 mm to 2.1 mm. _____Page 7 This paper is suitable for Chuanzhonggu National Standards (CNS), M Grid (210 × 297 cm) " 448 7 1 〇 Α7 ______________B7_5 'Description of the invention (5) — The board can be used without any problems, In the following embodiments, an eight-layer circuit board with a thickness of 1.6 mm is described in detail as a preferred embodiment of the present invention, but it is not a limitation of the present invention. The implementation and modification of the teachings of the invention also belong to the scope of the present invention. 5 First, please refer to the second figure, which is an eight-layer circuit board 6 with a thickness of 1.6 mm according to the preferred embodiment; wherein: the circuit board 6 is arranged from top to bottom, and the sequence is first, third, sixth and The eight-layer board is the signal routing layer S2, S3, S4, the second, fourth, and seventh layers are the ground layer GND, and the fifth layer is the power layer P WR, and 'the circuit board The first layer S1 and the eighth layer S4 of 6 are also parts laying layers. In addition, a first insulating layer 61 is sandwiched between the fourth layer GND and the fifth layer PWR; A second insulating layer 63 is sandwiched between the layer GND and the third layer S2 and the fifth layer PWR and the sixth layer S3, respectively; between the third layer S2 and the second layer GND and the sixth layer A third insulating layer 65 is sandwiched between the layer S3 and the seventh layer GND, and between the second layer GND and the first layer S1 and the seventh layer GND and the eighth layer S4. A fourth insulating layer 67 is respectively sandwiched, and the first insulating layer 61 and the third insulating layer 65 are a polyester film (p_p), and the second insulating layer 63 and the fourth insulating layer 67 are one. Substrate (core). Generally, the impedance value between the circuit board and the board is usually designed according to the theoretical values set by Intel. The circuit board designed for high-speed signals is mainly designed for the impedance value between the board and the board. It should be designed at about 55% 10% Ω to meet the design requirements of local speed lines; and in order to improve the lack of the above-mentioned knowledge, the impedance between the inner and outer layers of the circuit board can be matched to page 8 15 20 This paper is extended. The national standard rate (CNS) in the store is 8 4 (21〇χ297 mm I 1- I-II---, + SL-I---I--(f IIX · *-'B (read first Note on the back, fill in 5-T book s) 448 71 〇 Α7 _________B7 V. Description of the invention (6) The author found that the thickness of the insulation layers 61, 63, 65, and 67 between each layer can be adjusted to To change the impedance value between the laminates and make the impedance values of the inner and outer laminates equal to each other to achieve impedance matching between the various laminates, the following calculation formula is proposed: Formula One (Find the outer layer impedances Rs 1 and Rs4 Calculation formula): 5
Rsl or Rs4 87 rill·! 5.9m 10 15 l〇w+7j 其中，&=4·5 ’係為介電常數； 請配合參照第三圖所示，其中： Η ’係為介電厚度’亦即第一層板si與第二 層板GND及第七層板GND與第八層板S4之 間的第四絕緣層67之厚度； W=6mi1’係為走線寬度（實際上W值從2~8mil 皆可，但以6mil為最佳）； T=1.4mi卜係為走線厚度； 公式一（求内層阻抗Rs2及Rs3之計算公式） 60Rsl or Rs4 87 rill ·! 5.9m 10 15 l〇w + 7j where & = 4 · 5 'is the dielectric constant; please refer to the third figure, where: Η' is the dielectric thickness' That is, the thickness of the fourth insulating layer 67 between the first layer si and the second layer GND and the seventh layer GND and the eighth layer S4; W = 6mi1 'is the wiring width (actually W value It can be from 2 ~ 8mil, but 6mil is the best); T = 1.4mi is the thickness of the trace; Formula 1 (Calculation formula for inner layer resistance Rs2 and Rs3) 60
Rs2 or Rs3 = -^=inRs2 or Rs3 =-^ = in
4B 0.67 撕 0.8 +4B 0.67 tear 0.8 +
T W 其中，厶=4.5，係為介電常數： 請再配合參照第三圖所示，其中： B，係為總介電厚度，亦即第二層板gnd(去 地層）與第四層板GND(接地層）之間或第五4 _____^第 9頁 本紙張尺度通用中囡國家標準（CNS ) A4it^TTi07297^iy 20 ----------裝------訂------r / (ti先閱讀背面之注意事項再填寫本頁) ^7\〇 A7 〜〜s__________B7 —_ 五'發明説明（7 ) 板PWR(電源層）與第七層板GND(接地層）之 間的第二絕緣層63加上第三絕緣層65的厚 度； (誚先閲讀背面之注意事項再"寫本頁) T=0_7mil，係為走線厚度； 5 W=6mi1，係為走線寬度（實際上W值從2〜8mil 皆可，但以6mil為最佳）； 首先，Rsl(或Rs4)及Rs2(或RS3)之阻抗值必須落在 55±10°/〇Ω ’即49.5Ω〜60.5Ω之間才能符合走高速訊號之 没計要求’故可先從公式一中’ Rs 1 (或Rs4)分別以49.5 10 Ω及60.5Ω代入，求得Η之值係介於一範圍中，如 5.5mi卜6.0mil ;又如第二圖所示，我們知道各層板之板 厚由上而下分別為 1.4mil、0.7mil、0.7mil、0.7mil、〇.7mil、 〇_7mil、0.7mil及1.4mil ’由此可求得各層板之總板厚為 7mil;且因為電路板之總板厚為i.6mm=64mil，故可得出TW where 厶 = 4.5, is the dielectric constant: Please refer to the third figure, where: B, is the total dielectric thickness, that is, the second layer gnd (remove the ground) and the fourth layer Between GND (grounding layer) or the fifth 4 _____ ^ page 9 This paper is a common Chinese national standard (CNS) A4it ^ TTi07297 ^ iy 20 ---------- installation ------ Order ------ r / (ti read the precautions on the back before filling this page) ^ 7 \ 〇A7 ~~ s __________ B7 —_ Five 'Description of the invention (7) Board PWR (power layer) and seventh layer board The thickness of the second insulating layer 63 plus the third insulating layer 65 between GND (ground layer); (诮 Read the precautions on the back before writing this page) T = 0_7mil, which is the thickness of the wiring; 5 W = 6mi1, which is the trace width (actually the W value can be from 2 ~ 8mil, but 6mil is the best); First, the impedance value of Rsl (or Rs4) and Rs2 (or RS3) must fall within 55 ± 10 ° / 〇Ω 'that is, between 49.5Ω ~ 60.5Ω can meet the requirements of high-speed signals', so you can first use formula 1' Rs 1 (or Rs4) to substitute 49.5 10 Ω and 60.5Ω respectively, to find Η The value is in a range, such as 5.5mi and 6.0mil As shown in the second figure, we know that the thickness of each layer is 1.4mil, 0.7mil, 0.7mil, 0.7mil, 0.7mil, 〇_7mil, 0.7mil, and 1.4mil from top to bottom. The total board thickness of each layer can be obtained is 7mil; and because the total board thickness of the circuit board is i.6mm = 64mil, it can be obtained
15 2H+2B+D=64mil-7miI=57mil，2B+D=57mil-2H，即 2B+D 介於46mi l~45mi 1之間；繼而在公式二中，代入一 β值可 計算出Rs2(或Rs3)，並比較Rsl(或Rs4)與Rs2(或Rs3) 兩者數值的差距，及兩者是否皆落在55土 10%Q (49.5Ω 〜60.5Ω)附近’並以此比較之結果來分別調整η及B之數 20 值，再分別代入公式一及公式二中計算出另一 RS1 (或Rs4) 及Rs2(或Rs3)值，再相互比較、調整Η及B的厚度大小， 即能求出Rsl(或Rs4)與Rs2(或Rs3)兩者最接近且皆落在 55土10%0(49_5 0〜60_5 0)之間的值，而當11及6值確定 後，即可求得D之值，因此第一絕緣層61之厚度（即D)、 第10頁 本紙張尺度適扣中围國家標準（CNS ) Α4規格（2丨0X297公釐） 赛仙71〇 Α7 ___________Β7____ 五、發明説明（8 ) ---------裳-- (誚先閱讀背面之注意事項再功本頁) 第二絕緣層63(即Η2)加第三絕緣層65(即Η3)之厚度（即 Β)及第四絕緣層69之厚度（即Η)之最適當厚度因而碟定， 使得2H+2B+DK各層板厚度和（7mil)) =電路板之板厚 =1.6mm 〇 5 藉由上述公式一、二之運算及求解過程，可找出最佳 值為當 H=5. 5mi 1，B=22. 4mi 1 及 D=4mi 1 時，Rsl(或 Rs4) 与 60Ω ’ Rs2(或 Rs3)与 60Ω，皆落在 55±1〇%Ω (49.5Ω ~60.5 Ω )之間，内外層阻抗值差距可達〇 Q，完全達到阻 抗匹配的目的，因此當高速訊號在此電路板6中傳輸時， 10 當高速訊號從外層板，亦即零件佈設層（如第一層板si或 第八層板S4)穿層至内層板（如第三層板S2或第六層板S3) 時’因内外層板之阻抗完全匹配，所以能消除該高速訊號 之訊號反射量（即駐波），在此可算出其反射係數為： n _Zl~Zo Rs\-Rs2 Λ p =-=-=〇15 2H + 2B + D = 64mil-7miI = 57mil, 2B + D = 57mil-2H, that is, 2B + D is between 46mi l ~ 45mi 1; then in Formula 2, substituting a β value can calculate Rs2 ( Or Rs3), and compare the difference between the values of Rsl (or Rs4) and Rs2 (or Rs3), and whether both fall near 55% 10% Q (49.5Ω ~ 60.5Ω) and compare the results To adjust the values of η and B, respectively, and calculate the other RS1 (or Rs4) and Rs2 (or Rs3) values in Formula 1 and Formula 2, respectively, and then compare and adjust the thickness of Η and B. Can find the value of Rsl (or Rs4) and Rs2 (or Rs3) that are closest and both fall between 55 and 10% 0 (49_5 0 ~ 60_5 0), and when the values of 11 and 6 are determined, you can Find the value of D, so the thickness of the first insulating layer 61 (that is, D), page 10 The paper size is suitable for the national standard (CNS) Α4 specification (2 丨 0X297 mm) Saixian 71〇Α7 ___________ Β7 ____ 5 、 Explanation of the invention (8) --------- Shang-- (诮 Read the precautions on the back first, and then go to this page) Second insulation layer 63 (ie Η2) plus third insulation layer 65 (ie Η3) The thickness of the fourth insulating layer 69 (i.e., Η) The thickness is thus determined, so that the thickness of each layer of 2H + 2B + DK (7mil)) = the thickness of the circuit board = 1.6mm 〇5 Through the calculation and solving process of the above formulas 1 and 2, the best value can be found When H = 5. 5mi 1, B = 22. 4mi 1 and D = 4mi 1, Rsl (or Rs4) and 60 Ω 'Rs2 (or Rs3) and 60 Ω, all fall within 55 ± 10% Ω (49.5Ω ~ 60.5 Ω), the difference between the inner and outer layer impedance values can reach 0Q, which completely achieves the purpose of impedance matching. Therefore, when high-speed signals are transmitted in this circuit board 6, 10 when high-speed signals are transmitted from the outer board, that is, the part layout layer ( For example, when the first layer si or the eighth layer S4) is penetrated to the inner layer (such as the third layer S2 or the sixth layer S3), the impedance of the inner and outer layers is completely matched, so the high-speed signal can be eliminated. Signal reflection (ie standing wave), the reflection coefficient can be calculated here: n _Zl ~ Zo Rs \ -Rs2 Λ p =-=-= 〇
Zl + Zo Rs\ + Rs2 15 相較於習知之反射係數P=〇.199係明顯地且完全地 改善了尚速訊號之反射’自然大大地消減了電磁波之干 擾，提昇了高速訊號的傳輸品質。 另外，在電路板之佈局時，雖然訊號線之走線穿至不 同層，但由於已控制了電路板之壓合厚度，使内外層阻抗 20達到阻抗匹配，故不需改變訊號線之走線寬度即可達到阻 抗控制的效果，提高了佈局之時效性。 綜上所述’本發明之『八層電路板之壓合方法及其結 構』，確能藉上揭構造、裝置，達到預期之目的與功效， 第 11 頁 本紙張尺度適用中國國家樣率（CNS) A4規格（210ϋ7公釐） ------ ^48 7 1 Ο 五 Α7 Β7 發明説明（9) 且申請前未見於刊物亦未公開使用，符合發明專利之新 穎、進步等要件。 惟，上揭圖式及說明，僅為本發明之實施例而已，非 為限定本發明之實施；大凡熟悉該項技藝人仕，依本發明 特徵範令所作其他等效變化或修飾，皆應涵蓋在以下:案 之申請專利範圍内0 I HJ II— ---- I « I - . 士 良 I - I — I- I n i Τ» (7F先M讀背面之注意事項再坫艿冬Η ) 対浐部中次"n<^,，jiT,"於合作71印鲈 頁 2 本紙張尺度適用中國國家標準（CNS M4規格（210X297公釐）Zl + Zo Rs \ + Rs2 15 Compared with the conventional reflection coefficient P = 0.199, it significantly and completely improves the reflection of high-speed signals. Naturally, it greatly reduces the interference of electromagnetic waves and improves the transmission quality of high-speed signals. . In addition, in the layout of the circuit board, although the signal wires are routed to different layers, because the pressed thickness of the circuit board has been controlled so that the impedance of the inner and outer layers reaches impedance matching, there is no need to change the signal wire routing. The width can achieve the effect of impedance control, which improves the timeliness of the layout. In summary, the "compression method and structure of an eight-layer circuit board of the present invention" can indeed achieve the desired purpose and effect by using the structure and device of the cover-up. CNS) A4 specification (210ϋ7 mm) ------ ^ 48 7 1 〇 5 A7 B7 Invention description (9) It was not used in publications or published before application. It meets the requirements for novelty and progress of invention patents. However, the drawings and descriptions above are only examples of the present invention, and are not intended to limit the implementation of the present invention. Anyone skilled in the art and making other equivalent changes or modifications in accordance with the features of the present invention should apply. Covered in the following: within the scope of the patent application for the case 0 I HJ II— ---- I «I-. Shiliang I-I — I- I ni Τ» (7F first read the precautions on the back and then read the winter notes) ) The middle part of the crotch " n < ^ ,, jiT, " in cooperation 71 Indian sea bass page 2 This paper size applies to Chinese national standards (CNS M4 specification (210X297 mm)