TW447138B - Manufacturing method of thin-film transistor - Google Patents
Manufacturing method of thin-film transistor Download PDFInfo
- Publication number
- TW447138B TW447138B TW089108111A TW89108111A TW447138B TW 447138 B TW447138 B TW 447138B TW 089108111 A TW089108111 A TW 089108111A TW 89108111 A TW89108111 A TW 89108111A TW 447138 B TW447138 B TW 447138B
- Authority
- TW
- Taiwan
- Prior art keywords
- film transistor
- source
- layer
- thin film
- drain
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 239000002210 silicon-based material Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 168
- 239000004020 conductor Substances 0.000 claims description 65
- 239000000463 material Substances 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 39
- 239000000956 alloy Substances 0.000 claims description 23
- 229910045601 alloy Inorganic materials 0.000 claims description 22
- 239000011241 protective layer Substances 0.000 claims description 22
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 21
- 229910052719 titanium Inorganic materials 0.000 claims description 21
- 239000010936 titanium Substances 0.000 claims description 21
- 229910052782 aluminium Inorganic materials 0.000 claims description 20
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 16
- 229910000838 Al alloy Inorganic materials 0.000 claims description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 14
- 239000002131 composite material Substances 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 239000010931 gold Substances 0.000 claims description 9
- 238000001459 lithography Methods 0.000 claims description 9
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 8
- 229910052804 chromium Inorganic materials 0.000 claims description 8
- 239000011651 chromium Substances 0.000 claims description 8
- 230000002079 cooperative effect Effects 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 229910052750 molybdenum Inorganic materials 0.000 claims description 8
- 239000011733 molybdenum Substances 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 229910052709 silver Inorganic materials 0.000 claims description 8
- 239000004332 silver Substances 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- 150000002739 metals Chemical class 0.000 claims description 7
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 239000004576 sand Substances 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- 229910052702 rhenium Inorganic materials 0.000 claims description 4
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 claims description 4
- 238000012856 packing Methods 0.000 claims description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 claims description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 2
- 230000000717 retained effect Effects 0.000 claims description 2
- 229910052725 zinc Inorganic materials 0.000 claims description 2
- 239000011701 zinc Substances 0.000 claims description 2
- 229910052779 Neodymium Inorganic materials 0.000 claims 3
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 claims 3
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 claims 1
- 150000002343 gold Chemical class 0.000 claims 1
- 238000009434 installation Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000002243 precursor Substances 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000018044 dehydration Effects 0.000 description 1
- 238000006297 dehydration reaction Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Description
經濟部智慧財產局員工消費合作社印製 ΑΑΊ13 8 Λ7 5372twf.doc/〇〇g 五、發明說明(f ) 本發明是有關於一種薄膜電晶體的製造方法,且特別 是有關於一種以四道光罩製程製造薄膜電晶體的方法。本 案所請薄膜電晶體的製造方法,除可運用於傳真機(FAX machine )'接觸式影像感測器(CIS ),例如掃描器 (scanner),以及其它各種電子元件等之製造外,亦可運 用於一般薄膜電晶體平面顯示器之製造,其中平面顯示器 則可以是液晶顯示器(L C D )、有機光激發雙極晶體(〇 L E D )等平面顯示器。 薄膜電晶體平面顯示器主要係由薄膜電晶體元件和平 面顯示元件構成,其中薄膜電晶體元件係由多個薄膜電晶 體組成,而以矩陣的方式排列,其中每一個薄膜電晶體都 對應一個畫素電極(Pixel Electrode)。上述之薄膜電晶體主 要是由形成於一絕緣基材上之聞極(Gate)、聞介電層(Gate Dielectric)、通道層(Channel Layer) '與源極/汲極堆疊而 成,此薄膜電晶體係用來作爲平面顯示單元的開關元i牛。 習知技藝之薄膜電晶體的製造步驟略述如下。 請參照第1A圖,首先提供絕緣基材1〇〇,再於絕緣 基材100上濺鍍一導體層,該導體層係由一層或多層(如 複合層)之包含至少一種或多種選自金屬或/及其合金之 材料所形成,其中之金屬或/及其合金係可選自鋁、銅、 金、銀 '鉬、鉻、鈦、鎢等材料,其中之鋁合金亦可包含 銳C N d )。在一較佳實施例中其係可爲至少包含一駄/ 銘/駄複合層(未顯示),而其中之欽、鋁等材料亦包含其 合金之範圍’而鋁合金亦可包含鈸(N d ),然後進行第 4 本紙張尺度適用中國國家標準(CNS)A4規格(210x 297公釐) (請先閱讀背面之泫意事項再填寫本頁) 裝---- 訂---------線 經濟部智慧財產局員工湞費合作社印製 447138 Λ7 5872twf.doc/008 B7 五、發明說明(>) 一次微影蝕刻製程,圖案化此駄/鋁/鈦複合層以形成閘 極110與閘極線路。 請參照第1B圖,接著依序沉積較佳爲至少包括一氮 化矽層(SiNx)120、較佳爲至少包括一非晶矽層(a-Si:H)l 30、與較佳爲至少包括一慘雑非晶砂層(n+ a-Si) 140 於絕緣基材100之上’再進行第二次微影蝕刻製程,其僅 保留位於閘極110上方的較佳爲至少包括一非晶矽層130 與較佳爲至少包括一摻雜非晶矽層140。 請參照第1C圖,接下來濺鍍一層或多層(如複合層) 之包含至少一種或多種選自金屬或/及其合金之材料之金 屬層150於絕緣基材之上’其中該金屬或/及其合金 係可選自鋁、銅、金、銀、鉬、鉻、鈦、鎢等材料,其中 之鋁合金亦可包含銨(N d.)。在一較佳實施例中其係可 爲至少包含一駄/銘/欽之複合層’而其中之欽、銘等材 料亦包含其合金之範圍,而鋁合金亦可包含銳(N d ) ’ 再進行第三次微影蝕刻製程’依序圖案化此金屬層與其下 方之較佳爲至少包括一摻雜非晶矽層140,以形成源極/汲 極線路150a、源極/汲極金屬層150、與源極/汲極140a。 請參照第1D圖,接著沉積較佳爲至少包括一氮化砍 保護層160於絕緣基材〗00之上,再進行第四次微影蝕刻 製程,以在氮化矽保護層160中形成開口 166,此開口】66 暴露出源極/汲極金屬層150的一部分。 請參照第1E圖,接下來於絕緣基材100之上濺鍍較 佳爲至少包括一氧化銦錫層(Indium Tin Oxide ; ΙΤΟ)Π〇 ’ 5 本紙張尺度適用中國國家標準(CNS)A4規格(210x 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝---- 訂---------線 A7 !37 五 經濟部智慧財產局員工消費合作社印製 447138 5872twf(doc/008 發明說明(、) 最後進行第五次微影蝕刻製程,圖案化此氧化麵錫層以形 成畫素電極170。 如上所述,習知技藝之薄膜電晶體的製造方法總丑需 要至少5次彳·_製程。_每〜次㈣㈣呈皆靖 經過去水烘烤(Dehydration Bake)、塗底(primm 衣彳,白心、 軟烤(Soft Bake)、曝光(Exposure)、曝光後执上光「且 (Development)、硬烤(Hard Bake)、蝕刻(Etch^、烤、顯影 光阻等步驟,故每增加一次微影蝕刻製程,ng)、以及去 生產成本。而且每經過—次上述步驟, 會增加許多 漸降低。 <具率亦會逐 本發明提出一種薄膜電晶體的製造方法, 傳真機(FAX machine)、接觸式影像感測器〜刁運用方、 如掃描器(scanner),以及其它各種電子元件等CB),例 亦可運用於一般薄膜電晶體平面顯示器之製兔之製造外, 顯示器則可以是液晶顯示器(L C 1D ) '有^,其中平面 晶體(Q L E D )等平翻示器。本案时物發雙極 緣基材,其步驟如下。首先於絕緣基材上依摩趫用於一絕 體層、閘介電層、矽材料層、與摻雜矽材料騰t成第—導 案化摻雜矽材料層、矽材料層、閘介電層、與第,再依序圖 以形成閘極與閘極線路。接著於絕緣基材上、私二,體層, 層,再依序圖案化第二導體層與摻雜矽材料騰成第二導體 極/汲極線路主體、源極/汲極導體層、與源梅/以形成源 源極/汲極線路主體位於閘極線路兩側,月未丨及極’其中 導體層連接,以免源極/汲極線路主體接們φ辑源極/汲極 啊到_極與閘極 本纸張尺度適用中國國家標準(CNS)A4规格(210 x 297公釐) <請先閱讀背面之注意事項再填寫本頁> 裝--------訂---------線 1 _ 447 1 3 8 5 8 7 2 ti * ci 〇 c / 0 0 8 A7 U7 經濟部智慧財產局員工消費合作社印製 五、發明說明(π ) 線路而導致短路。接下來於絕緣基材上形成保護層,再圖 案化此保護層,以形成數個開口於源極/汲極導體層與鬧 極線路兩側之源極/汲極線路主體之上。最後形成透明導 體層於保護層之上與所有開口之中,再圖案化此透明導體 層,以形成一畫素電極,並保留另一部分的透明導體層, 以使閘極線路兩側之源極/汲極線路主體與源極/汲極導體 層電性連接’而完成一源極/汲極線路。 如上所述,在本發明之薄膜電晶體的製造方法中,源 極/汲極前身(即摻雜矽材料層)之圖案化與閘極及閘極線路 之圖案化共只需要一次微影製程,且源極/汲極線路主體' 源極/汲極導體層、與源極/汲極之形成共只需要一次微影 製程。因此,使用本發明可以使製造薄膜電晶體所需之微 影鈾刻製程數目由5次以上減爲4次’也就是說可以降低 成本,以及增加量產之良率。 爲讓本發明之上述目的'特徵、和優點能更明顯易懂, 下文特舉一較佳實施例,並配合所附圖式,作詳細說明如 下: 圖式之簡單說明: 第1A-1E圖所繪示爲習知技藝中,薄膜電晶體平面顯 示器中的薄膜電晶體的製造流程剖面圖。 第2、3A、4 ' 圖所繪示爲本發明之較佳實施 例中,薄膜電晶體平#'示器中的薄膜電、曰<體的製造流程 剖面圖。第3Β、5&Β圖各自爲第3Α圖之上視 圖。 4' 7 本紙張尺度適用中S國@準規袼(2l〇x 297公Έ ------------_! ^--------訂-----I---線 (請先閱讀背面之注意事項再填寫本頁) 47138 5072twf 'doc / 008 Λ7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明(l ) 圖式之標號說明: 100、200 :絕緣基材 110、210a :閘極 120、220 :氮化矽層、閘介電層 130、230 :非晶矽層、矽材料層 140、240 :摻雜非晶矽層、摻雜矽材料層 140a、240a :源極/汲極 150、250a :源極/汲極金屬層、源 150a ' 280 :源極/汲極線路 160、260 :氮化矽保護層、保護層 166、266 :開口 170、27〇a :畫素電極 210、250 :導體層 210b :閘極線路 25〇b :源極/汲極線路主體 27〇 :透明導體層 較佳實施例說明 請參照第2圖,首先提供絕緣基材200,再依序於絕 緣基材200之上形成導體層2丨◦、閘介電層22〇、矽材料 層23〇、與摻雜矽材料層24〇。其中,導體層21〇係由〜 層或多層(如複合層)之包含至少—種或多種選自金 =及其合金之材料所形成,其中之賴或/及其合金; 进自銘、銅、金、銀、鉬.、鉻 '欽、鎢等材料,其中二 ./汲極導體層 合金亦可包含敏(Nd)。在—較佳實施例中可 (請先閲讀背面之注意事項再填寫本頁) -------—訂·--—----III --- f紙張尺度適用中國國家標準(CNS)A4^T^ 297公釐) 44713 8 5872twf,doc/〇〇| Λ: Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明(6 ) 少包含一鋁/鈦複合層,而其中之鈦、鋁等材料亦包 含其合金之範圍,而鋁合金亦可包含鈸(N d ),閘介電 層220較佳爲至少包括一氮化矽層,矽材料層23〇之材質 較佳爲至少包括一非晶矽,摻雜矽材料層240之材質較佳 爲至少包括〜hi型摻雜非晶矽。 請參照第3A-3B圖,其中第3B圖爲第3A圖之上視 圖’而沿直線I-Ι切割第3B圖所得之剖面圖即爲第3A圖。 如第3A_3B圖所示,接著進行第一次微影蝕刻製程,依序 圖案化摻雜矽材料層240、矽材料層230、閘介電層220、 與導體層210,以得閘極21〇a與閘極線路2]〇b。 請參照第4圖,接著於絕緣基材200之上形成導體層 25〇 ’此導體層2S0係由一層或多層(如複合層)之包含 至少一種或多種選自金屬或/及其合金之材料所形成,其 中之金屬或/及其合金係可選自鋁、銅 '金、銀、鉬、鉻' 鈦、鎢等材料,其中之鋁合金亦可包含鈸(N d )。在一 較佳實施例中其係可爲至少包含一鈦/鋁/鈦複合層,而 其中之鈦、鋁等材料亦包含其合金之範圍,而鋁合金亦可 包含銳(N d )。 請參照第5A-5B圖’其中第SB圖爲第5A圖之上視 圖’而沿直線ΙΙ-Π切割第5B圖所得之剖面圖即爲第5A 圖。如第5A-5B圖所示,接著進行第二次微影蝕刻製程’ 依序圖案化導體層250與摻雜砂材料層240,以形成源極/ 汲極線路主體MOb、源極/汲極導體層25〇a,以及源極/汲 極240a。其中,源極/汲極240a係位於矽材料層23〇之上, 9 -------------- 裝--------訂---------線 (請先閱讀背面之注意事項再填寫本1) 本紙張尺度適用中园國家標準(CNS)A4規格(210 X 297公爱> _ M. 經濟部智慧財產局員工消費合作社印製 447138 Λ7 5872twf-doc/008 ny 五、發明說明(q ) 源極/汲極導體層250a位於源極/汲極240a之上,源極/汲 極線路主體250b則位於閘極線路210b兩側之絕緣基材200 之上,且未與源極/汲極導體層250a相連,使得源極/汲極 線路主體250b不致於接觸閘極210a與閘極210b而導致 短路。 請參照第6A_6B圖,其中第6B圖爲第6A圖之上視 圖,而沿直線ΙΙΙ-ΠΙ切割第6B圖所得之剖面圖即爲第6A 圖。如第6A-6B圖所示,接下來於絕緣基材200之上形成 保護層260,此保護層260較隹爲至少包括一氮化矽層。 接著進行第三次微影蝕刻製程來圖案化保護層260,以形 成數個開口 266於閘極線路兩側的源極/汲極線路主體250b 與源極/汲極導體層250a之上。 請參照第7A-7B圖,其中第7B圖爲第7A圖之上視 圖,而沿直線IV-IV切割第7B圖所得之剖面圖即爲第7A 圖。如第7A-7B圖所示,接著形成透明導體層27〇於保護 層260之上與所有開口 266之中,此透明導體層270較佳 爲至少包括一氧化銦錫層,接著再進行第四次微影蝕刻製 程來圖案化透明導體層270,以形成畫素電極270a,同時 保留另一部分的透明導體層270,藉以電性連接閘極線路 210b兩側的源極/汲極導體層250a與源極/汲極線路主體 25〇b,此時源極/汲極線路主體250b與透明導體層270即 構成了完整的源極/汲極線路280。 如第7A-7B圖所示,依本發明較佳實施例之薄膜電晶 體的製造方法所得之薄膜電晶體係由下列部分所構成:絕 本纸張尺度賴巾®國家標準(CNS)A4規格(210 X 297 11 — 1 11111 .-Γ < -----I — ^ > —------- <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 在4713 8 五、發明說明(ϊ) 緣基材200、閘極210b '閘極線路210b、閘介電層220 ' 矽材料層230、源極/汲極240a、源極/汲極導體層250a、 源極/汲極線路280、保護層260 '以及畫素電極270a,其 中源極/汲極線路280係由源極/汲極線路主體250b與透明 導體層270組成。 請參照第7A-7B圖,上述之閘極210a位於絕緣基材 200之上。閘極線路210b位於絕緣基材200之上。閘介電 層220位於閘極210a與閘極線路210b之上。矽材料層230 位於閘介電層220之上,且當由垂直絕緣基材200之方向 觀視時,矽材料層230、閘介電層220之形狀與閘極210a 加上閘極線路210b之形狀相同且重合。源極/汲極240a位 於矽材料層230之上。源極/汲極導體層250a位於源極/汲 極240a之上。源極/汲極線路280中的源極/汲極線路主體 250b之材質與源極/汲極導體層250a相同,且位於閘極線 路210b兩側之絕緣基材200上,此分段之源極/汲極線路 主體250b係藉由源極/汲極線路280中的透明導體層270 以行電性連接,並藉之與源極/汲極導體層250a電性連接。 保護層260位於矽材料層230、源極/汲極導體層250、與 源極/汲極線路主體250b之上,且位於透明導體層270之 下,此保護層260中具有數個開口 266,而透明導體層270 係經由這些開口 266以電性連接源極/汲極導體層250a與 閘極線路210b兩側之源極/汲極線路主體250b,以構成完 整的源極/汲極線路280。畫素電極270a之材質與透明導 體層270相同,此畫素電極270a係位於保護層260之上。 本紙張疋度適用中國國家標準(CNS)A4規格(210x 297公釐) ------------- 裝--------訂·-------•線 (請先閒讀背面之注意事項再填寫本頁) Λ4713 8 Λ7 5872twf.doc/008 uj , 五、發明說明(q) 如上所述,在本發明較佳實施例之薄膜電晶體的 方法中,源極/汲極前身(即第3圖中圖案化之摻雜矽材料 層240)之形成與閘極2 1 Oa及閛極線路21 Ob之形成共只需 要一次微影製程(請見第3A-3B圖);且源極/汲極線路主體 250b、源極/汲極導體層250a '與源極/汲極240a之形成亦 只要一次微影製程(請見第5A-5B圖)。因此,使用本發明 可以使製造薄膜電晶體所需之微影蝕刻製程數目由5次以 上減爲4次,也就是說可以降低成本,以及增加量產之良 率。 雖然本發明已以一較佳實施例揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精 神和範圍內,當可作各種之更動與潤飾,因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 -I--I I—---I I i . . I I-----_ν__π· —----I-- (請先閱讀背面之注咅?事項再填寫本頁) 經濟部智婪財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4蜆格(210 X 297公釐)
Claims (1)
- 8 3 8 ο ο / C 0 d f w t 2 7 8 5 8 88 8 ABCD 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 1.一種薄膜電晶體的製造方法,適用於一絕緣基材, 該方法包括下列步驟: 依序形成一第一導體層、一鬧介電層、一砂材料層、 一摻雜矽材料層於該絕緣基材上; 進行第一微影蝕刻步驟,依序圖案化該摻雜矽材料層、 該矽材料層、該閘介電層、與該第一導體層,以形成一閘 極與一閘極線路; 形成一第二導體層於該絕緣基材上; 進行第二微影蝕刻步驟,依序圖案化該第二導體層與 該摻雜矽材料層,以形成一源極/汲極導體層、一源極/汲 極、與位於該閘極線路兩側之該絕緣基材上之一源極/汲 極線路主體; 形成一保護層於該絕緣基材之上; 進行第三微影蝕刻步驟,圖案化該保護層,以形成複 數個開口於該源極/汲極導體層上與該閘極線路兩側之該 源極/汲極線路主體上; 形成一透明導體層於該保護層之上與該些開口之中; 以及 進行第四微影蝕刻步驟,圖案化該透明導體層,以形 成一畫素電極,並保留另一部分的該透明導體層,以使該 閘極線路兩側之該源極/汲極線路主體與該源極/汲極導體 層電性連接,而完成一源極/汲極線路。 如申請專利範圍第1項之薄膜電晶體的製造方法, 其中該第一導體層係由一層或多層之包含至少一種或多種 本紙張又度適用中國國家標準(CNS)A.4規格(210 X 297公釐) ------------裝----! ---訂---------線1 <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 471 3 8 as R8 C8 _5 8 7 2 tw£ . doc/ 0 0 8_™_ 六、申請專利範圍 選自金屬或/及其合金之材料所形成。 3.如申請專利範圍第、項之薄膜電晶體的製造方法, 其中該金屬或/及其合金係選自鋁、銅、金、銀、鉬、鉻、 鈦、鎢等材料。 4如申請專利範圍第3項之薄膜電晶體的製造方法, 其中該鋁合金係可包含钕(N d )。 5. 如申請專利範圍第1項之薄膜電晶體的製造方法, 其中該第一導體層係至少包含一鈦/鋁/鈦複合層,其中 之鈦、鋁等材料亦包含其合金之範圍。 6. 如申請專利範圍第5項之薄膜電晶體的製造方法, 其中該鋁合金係可包含鈸(Nd)。 7. 如申請專利範圍第1項之薄膜電晶體的製造方法, 其中該閘介電層至少包括一氮化矽層。 8. 如申請專利範圍第1項之薄膜電晶體的製造方法, 其中該矽材料層之材質至少包括一非晶矽。 _ 9.如申請專利範圍第1項之薄膜電晶體的製造方法, 其中該摻雜矽材料層之材質至少包括一 N型摻雜非晶矽。 10. 如申請專利範圍第1項之薄膜電晶體的製造方法, 其中該第二導體層係由一層或多層之包含至少一種或多種 選自金屬或/及其合金之材料所形成。 11. 如申請專利範圍第10項之薄膜電晶體的製造方法, 其中該金屬或/及其合金係選自鋁、銅、金、銀、鉬、鉻、 欽、鎢等材料。 12. 如申請專利範圍第11項之薄膜電晶體的製造方法, 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -------------裝·!-----訂---1-----線' {請先閱讀背面之泫意事項再填寫本頁) A8 B8 C8 D8 ^4713 8 Ll72 七 wf+ doc/008 、申請專利範圍 其中該鋁合金係可包含钕(Nd)。 13.如申請專利範圍第1項之薄膜電晶體的製造方法, 其中該第二導體層係至少包含一鈦/鋁/鈦複合層,其中 之鈦、鋁等材料亦包含其合金之範圍》 ]4.如申請專利範圍第13項之薄膜電晶體的製造方法, 其中其中該鋁合金係可包含銨(Nd)。 15. 如申請專利範圍第1項之薄膜電晶體的製造方法, 其中該透明導體層至少包括一氧化銦錫層。 16. 如申請專利範圍第1項之薄膜電晶體的製造方法, 其中該保護層至少包括一氮化砂層。 Π.如申請專利範圍第1項之薄膜電晶體的製造方法, 其係可運用於一般薄膜電晶體平面顯示器之製造’其中平 面顯示器則可以是液晶顯示器(LCD)、有機光激發雙 極晶體(0 L E D )等之平面顯示器。 18. 如申請專利範圍第1項之薄膜電晶體的製造方法, 其係可運用於於傳真機(FAX machine)、接觸式影像感 測器(CIS) ’以及其它各種電子元件等之製造。 19. 一種薄膜電晶體,適用於一絕緣基材,該薄膜電晶 體結構包括: 一閘極’該閘極位於該絕緣基材之上; 一閘極線路’該閘極線路位於該絕緣基材之上; 一閘介電層位於該閘極與該閘極線路之上; 一矽材料層位於該閘介電層之上,當由該絕緣基材上 方觀視時’該砂材料層、該閘介電層之形狀與該閘極加上 ------;----^--裝--------訂---------線 (請先閱讀^面之注意事項再填寫本頁〕 經濟部智慧財產局員工消費合作社印製 @國家標準(CNS)A域格(21〇 x 297公釐) 44713 8 5 8 7 2 twf. doc/008 AS R8 C8 Π8 經濟即智慧財產局員工消費合作社印製 六、申請專利範圍 該閘極線路之形狀相同且重合; 一源極/汲極位於該矽材料層之上; 一源極/汲極導體層位於該源極/汲極之上; 一源極/汲極線路,該源極/汲極線路包含一源極/汲極 線路主體與一透明導體層,其中該源極/汲極線路主體僅 位於該閘極線路兩側之該絕緣基材上,且該源極/汲極線 路主體之材質舆該源極/汲極導體層相同,而該透明導體 層電性連接該源極/汲極導體層與該閘極線路兩側之該源 極/汲極線路主體; 一保護層位於該矽材料層、該源極/汲極導體層、與該 源極/汲極線路主體之上,但位於該透明導體層之下,該 保護層中具有複數個開口,該透明導體層係經由該些開口 而與該源極/汲極導體層及該閘極線路兩側之該源極/汲極 線路主體電性連接;以及 一畫素電極,其材質與該透明導體層相同,該畫素電 極係位於該保護層之上。 20. 如申請專利範圍第19項之薄膜電晶體,其中該閘 極與該閘極線路之材質係由一層或多層之包含至少一種或 多種選自金屬或/及其合金之材料所形成。 21. 如申請專利範圍第20項之薄膜電晶體,其中該金 屬或/及其合金係選自鋁、銅、金、銀、鉬、鉻、鈦、鎢 等材料。 22. 如申請專利範圍第21項之薄膜電晶體,其中該鋁 合金係可包含钕(N d )。 16 ----------! '裝--------訂---------線 (請先閱讀背面之注咅?事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 147138 5872twf.doc/008 A8 H8 C8 D8 六、申請專利範圍 23. 如申請專利範圍第19項之薄膜電晶體,其中該閘 極與該閘極線路之材質係至少包含一鈦/鋁/鈦複合層, 其中之鈦'鋁等材料亦包含其合金之範圍。 24. 如申請專利範圍第23項之薄膜電晶體,其中該鋁 合金係可包含銳(Nd)。 25. 如申請專利範圍第19項之薄膜電晶體,其中該閘 介電層至少包括一氮化矽層。 26. 如申請專利範圍第19項之薄膜電晶體,其中該矽 材料層之材質至少包括一非晶矽。 27. 如申請專利範圍第19項之薄膜電晶體,其中該源 極/汲極之材質至少包括一 N型摻雜非晶矽。 28. 如申請專利範圍第19項之薄膜電晶體,其中該導 體層與該源極/汲極導體層之材質係由一層或多層之包含 至少一種或多種選自金屬或/及其合金之材料所形成。 29. 如申請專利範圍第28項之薄膜電晶體,其中該金 屬或/及其合金係選自鋁、銅、金、銀、鉬、鉻、鈦、鎢 等材料。 30. 如申請專利範圍第29項之薄膜電晶體,其中該鋁 合金係可包含鈸(N d )。 31. 如申請專利範圍第19項之薄膜電晶體,其中該保 護層至少包括一氣化敬層。 32. 如申請專利範圍第19項之薄膜電晶體,其中該透 明導體層與該畫素電極之材質至少包括一氧化銦錫。 33. 如申請專利範圍第19項之薄膜電晶體,其係可運 <請先閲讀背面之注意事項再填寫本頁) 裝--------訂---------線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標竿(CNS)A4規格(210 X 297公釐) 80088 Am^cn d47l3B 5872twf.doc/008 六、申請專利乾圍 用於一般薄膜電晶體平面顯示器之製造’其中平面顯示器. 則可以是液晶顯示器(L C D ) '有機光激發雙極晶體(〇 L E D )等平面顯示器° 34.如申請專利範圍第19項之薄膜電晶體’其係可運 用於傳真機(FAX machine)、接觸式影像感測器(CIS) ’ 以及其它各種電子元件等之製造° :------^-------裝--------訂---------線: • 1-' I - (請先閱讀背面之沒意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)Ai規格(210 X 297公釐)
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TW089108111A TW447138B (en) | 2000-04-28 | 2000-04-28 | Manufacturing method of thin-film transistor |
US09/843,994 US6486009B2 (en) | 2000-04-28 | 2001-04-27 | Method of fabricating thin-film transistor |
US10/154,603 US6597015B2 (en) | 2000-04-23 | 2002-05-22 | Method of fabricating thin-film transistor |
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Cited By (1)
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US6900461B2 (en) | 2001-06-14 | 2005-05-31 | Idemitsu Kosan Co., Ltd. | Conductive thin film for semiconductor device, semiconductor device, and method of manufacturing the same |
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TW447138B (en) * | 2000-04-28 | 2001-07-21 | Unipac Optoelectronics Corp | Manufacturing method of thin-film transistor |
US7211828B2 (en) | 2001-06-20 | 2007-05-01 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device and electronic apparatus |
TW548860B (en) | 2001-06-20 | 2003-08-21 | Semiconductor Energy Lab | Light emitting device and method of manufacturing the same |
KR100669688B1 (ko) * | 2003-03-12 | 2007-01-18 | 삼성에스디아이 주식회사 | 박막트랜지스터 및 이를 구비한 평판표시소자 |
KR20050014060A (ko) * | 2003-07-29 | 2005-02-07 | 삼성전자주식회사 | 박막 트랜지스터 표시판 및 그의 제조 방법 |
US7427776B2 (en) * | 2004-10-07 | 2008-09-23 | Hewlett-Packard Development Company, L.P. | Thin-film transistor and methods |
CN100372083C (zh) * | 2005-06-02 | 2008-02-27 | 友达光电股份有限公司 | 形成薄膜晶体管的方法 |
TW200707048A (en) * | 2005-08-10 | 2007-02-16 | Novatek Microelectronics Corp | Active matrix display with higher aperture |
WO2011056710A2 (en) * | 2009-11-03 | 2011-05-12 | Applied Materials, Inc. | Thin film transistors having multiple doped silicon layers |
CN105527771A (zh) * | 2016-02-18 | 2016-04-27 | 武汉华星光电技术有限公司 | 阵列基板及液晶显示装置 |
CN106449764B (zh) * | 2016-11-23 | 2023-07-18 | 天津大学 | 一种柔性薄膜底栅双沟道晶体管 |
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EP1338914A3 (en) * | 1995-11-21 | 2003-11-19 | Samsung Electronics Co., Ltd. | Method for manufacturing liquid crystal display |
JP3288615B2 (ja) * | 1997-10-21 | 2002-06-04 | 株式会社アドバンスト・ディスプレイ | 薄膜トランジスタの製造方法 |
KR100305527B1 (ko) * | 1998-07-09 | 2001-11-01 | 니시무로 타이죠 | 반도체장치의 제조방법 및 제조장치 |
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JP2000332248A (ja) * | 1999-05-14 | 2000-11-30 | Internatl Business Mach Corp <Ibm> | 薄膜トランジスタおよびその製造方法 |
KR100338011B1 (ko) * | 1999-06-30 | 2002-05-24 | 윤종용 | 액정 표시 장치용 기판의 제조 방법 |
KR100313125B1 (ko) * | 1999-12-08 | 2001-11-07 | 김순택 | 박막 트랜지스터의 제조 방법 |
TW447138B (en) * | 2000-04-28 | 2001-07-21 | Unipac Optoelectronics Corp | Manufacturing method of thin-film transistor |
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US6900461B2 (en) | 2001-06-14 | 2005-05-31 | Idemitsu Kosan Co., Ltd. | Conductive thin film for semiconductor device, semiconductor device, and method of manufacturing the same |
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US6597015B2 (en) | 2003-07-22 |
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US6486009B2 (en) | 2002-11-26 |
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