TW447036B - Etching method using reactive ions - Google Patents

Abstract

The present invention provides an etching method using reactive ions, comprising the following steps. At the beginning, a semiconductor substrate is provided on which a material layer to be etched is formed. Thereafter, the semiconductor substrate is moved into a reactive ion etching chamber having a first electrode and a second electrode used to load the semiconductor substrate. Next, the material layer is selectively etched, wherein the etching process at least comprises a first phase and a second phase. During the first phase of the etching process, there is a first gap between the first electrode and the second electrode. During the second phase of the etching process, there is a second gap between the first electrode and the second electrode. The present invention discloses that in the different etching phases, the gaps between the electrodes are adjusted so that the etching uniformity for every part of the semiconductor wafer is enhanced by using the same etching steps (conditions) and the performance of the semiconductor device is maintained.

Description

44ZM6_. V. Description of the invention (1) Field of the invention The present invention relates to an ultra-large integrated circuits (ICs), and in particular to a reactive ion etching method. Description of the source / and bit line contact window of the metal oxide semiconductor transistor (MOS transistor). Descriptions of related technologies are applied to dry etching systems for semiconductor integrated circuits, including (1) plasma money engraving systems (p 1 asma et ch i ng) and (2) reactive ion etching systems (reactive ion etching; RIE), Generally speaking, plasma etching systems are isotropic (icotropic) etching, while reactive ion etching systems are anisotropic (& 11 丨 3〇1; 1′〇9 丨 〇 :) etching. When using 0.4 as the reaction gas, in the case of discharge, in addition to free molecules and atoms that are highly chemically reactive, cations such as CFa + and CF2 + are also generated. At this time, the semiconductor wafer with the material layer to be etched is placed on the cathode, and the cations impinge on the surface of the material layer to be etched under the acceleration of the electric field. Then, deterioration (F- and CFf) occurs. It is extremely susceptible to reaction, thus speeding up the engraving process. The impact of such ions is concentrated only in the depth direction, so the etching is performed only in the vertical direction 'and is called anisotropic etching. A parallel plate reactive ion etching system is equipped with a pair of parallel plate-type electrodes in the reaction of money carving, and a radio frequency (radio μ frequency; RF) voltage is applied to one side of the electrode, and the other electrode is connected To the ground potential 'and the wafer is placed on either side of the electrode, the bridging device, the reactive ion device which is engraved with silver. # ^

Page 4 447036 5. Description of the invention (2) The inventor has discovered that the electrode gap affects the concentration or quantity distribution of reactive ions throughout the semiconductor wafer, such as the ion concentration at the center or edge of the semiconductor wafer Or the quantity distribution is different, so it is easy to achieve a uniform etching rate of the material layer (such as an oxide layer) to be etched at various positions on the wafer, which affects the quality of the semiconductor device. Specifically, in the past, in the process of dynamic random access memory, the insulating layer was etched to form a bit line contact window. When the electrode pitch is large, the speed of the insulating layer in the center of the semiconductor wafer is greater than that of the semiconductor crystal. Round edges. Conversely, when the electrode pitch is small, the etching speed of the edge of the semiconductor wafer is greater than the center of the semiconductor wafer. In general, when a large electrode pitch is conventionally used, in order to avoid the etching stop of the insulating layer on the edge of the semiconductor wafer, the etching time must be increased. In this case, it will cause local (over the center of the semiconductor wafer) over-etching and even an unexpected short circuit. problem. In addition, it leads to problems of high cost and reduced throughput. SUMMARY OF THE INVENTION AND OBJECTS OF THE INVENTION In view of this, the object of the present invention is to provide a method for reactive ion etching, which can improve the uniformity of etching of the material to be etched at various positions on the semiconductor wafer by adjusting the electrode pitch. To further ensure the performance of semiconductor components such as dynamic random access memory (DRAM), and to control production and manufacturing costs. According to the foregoing objective, the present invention provides a method for reactive ion etching, including the following steps: providing a semiconductor substrate having a material layer to be etched on a surface thereof; and forming a semiconductor substrate having the material layer to be etched as described above.

4 4 7 0 3 6 V. Description of the invention (3) Move to the bottom of a reactive ion etching reaction chamber, the reaction chamber has a first electrode and a second electrode for carrying the semiconductor substrate; The material layer includes at least a first-stage etching and a second-stage etching. When the first-stage etching is performed, the first electrode and the second electrode have a first distance. When the second-stage etching is performed, the first An electrode has a second distance from the second electrode. That is, 'the first pitch is different from the second pitch, by adjusting the distance between the electrodes at different stages of the etching process, and performing more than two stages of etching', the uneven etching phenomenon caused by different ion concentration or quantity distribution Lighten. According to the above object, the present invention provides a method for manufacturing a bit line contact window, which is suitable for forming a semiconductor substrate with a gate electrode. The manufacturing method includes the following steps: (a) forming an oxide insulating layer on the semiconductor substrate; (b) The semiconductor substrate with the oxide insulating layer formed is moved to a reactive ion etching reaction chamber. The reaction chamber has a first electrode and a first electrode for carrying the semi-V body substrate; (c) selective silver engraving described above The insulating layer is oxidized to form a one-bit line contact window on the side of the gate electrode, which includes at least a first-stage etching and a second-stage etching. The two electrodes have a first pitch, and when the second-stage etching is performed, the first electrode and the second electrode have a second pitch. Furthermore, in the above-mentioned manufacturing method of the bit line contact window, the first pitch is approximately 33 to 37 inches (for example, 37 mm), and the second pitch is 27 to 31 (for example, 27 mm). Furthermore, the processing time of the first stage etching can be between 30 and 40 seconds.

447036 V. Description of the invention (4). The remaining processing time in the second stage is between 35 and 40 seconds. Furthermore, in the above-mentioned method for manufacturing a bit line contact window, in step (c), the oxide insulating layer can be etched using CF4, co, and Ar as a reactive gas. In addition, in the method for manufacturing a bit line contact window, after step (c), a polymer etching step may be further included to prevent the etching from stopping. This step may use CF4, CO, Ar, and 02 as reaction gases. . Furthermore, in the above-mentioned method for manufacturing a bit line contact window, the oxidation insulation material may be composed of a side wall dream glass material and a stone dioxide material. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make it clear as follows: "Simplified description of the Tian Shuo diagram 1 Figure 5 is a cross-sectional view of a process for forming a bit according to an embodiment of the present invention. _ Figure 6 shows a schematic diagram of a reactive ion etching device. < Explanation of the symbols of the two electrodes layer). 100 ~ semiconductor substrate. 140 ~ compound crystal material. G C-Gate. 1 0 0 ~ nitride < 5th side wall layer 200 ~ backing layer (line; r 220 ~ oxide insulating layer β 260 ~ photoresist pattern. 120 ~ gate oxide layer. 160 ~ metal fragmentation. 1 8 0 ~ Silicon nitride mask. 2 40 ~ Anti-reflection coating layer. 280 ~ Silver engraved opening.

4470 3 6 V. Description of the invention (5) 300, 300 '~ Middle contact hole. 300 " ~ Bit line contact window. Embodiments The following is a cross-sectional view of the process of the bit line contact window shown in Figs. 1 to 5 and the electrode shown in Fig. 6 to illustrate the preferred embodiment of the present invention. First, please refer to FIG. 1. This figure shows a cross-sectional view of the initial steps of the embodiment of the present invention, where the symbol 100 represents a semiconductor substrate 100 made of, for example, a P-type single crystal silicon, and the symbol 120 represents a gate formed by a thermal oxidation method. The “electrode layer” symbol GC represents a gate electrode (gatee 1 ectr 〇), which is composed of polycrystalline stone material 140 and metal polycrystalline stone compound (p〇1 yci de) 1 6 0, and the gate electrode The upper surface and the sidewall (si de wa 11 s) of the GC are respectively formed with a mask layer 180 made of a nitrided material and a nitride stone spacer 190, which are used as a etching stop layer in the subsequent steps. stop layer), and the mask layer 180 also functions as a polish stop layer. In addition, reference numeral 200 in FIG. 1 indicates a liner layer made of, for example, si licon oxynitride, which is used to ensure the effect of stopping the etching and prevent the gap between the gate and the source / drain. An unexpected short circuit has occurred. In addition, symbol 220 is, for example, a borophosphosilicate glass (BPSG) formed by chemical vapor deposition and an oxidation using silicon dioxide material (tetra-ethy ortho-si 1 icate; TEOS as a reaction gas). Insulation. 'Next, the symbol 2 40 represents an anti-reflection coating (ARC) made of a material such as oxysilicide, which is used to prevent the lithography process &11〇1; 〇111: 11〇8 ^ 117) Photoresist pattern distortion during exposure. Pick up

Page 8 447036 V. Description of the invention (6) The steps of photo-resist coating, exposure, develop, and bake using traditional lithography process are formed to have Photoresist pattern 260 of the opening 280. Next, referring to FIG. 6, “the semiconductor substrate 100 (ie, semiconductor wafer) on which the above-mentioned components are formed” is moved to a reactive ion money engraving machine, such as a DRM machine manufactured by TEL. The etching reaction chamber has a first electrode E1 and a second electrode E2 for carrying the semiconductor substrate 100. The gap (gap) between the electrodes El and E2 of this machine is adjustable (27mm ~ 37mm). Then, please refer to FIG. 2 ′ uses the photoresist pattern 26 as the etching shield, and removes the unshielded anti-reflection coating layer 240 through the opening 280 until the surface of the oxide insulating layer 220 is exposed. Furthermore, please refer to FIG. 3, and pass in an etching gas such as CF4, C0, and Ar with an appropriate flow ratio into the reaction chamber, and then 'move a part of the oxide insulating layer 2 2 0 to form an intermediate contact hole 300'. This includes at least a first-stage etching and a second-stage etching. When performing the first-stage etching, the distance between the first electrode E1 and the second electrode E2 is set to 37 mm, and the etching time is about 30 to 40 seconds. The etching speed of the oxide insulating layer in the first stage is smaller at the edge of the wafer than at the center of the wafer. When performing the above-mentioned second-stage etching, the distance between the first electrode £ 1 and the second electrode E2 is set to 27ππη, and the time of money engraving is about 35 to 40 seconds. The etching speed of the oxide insulating layer in this second stage is greater than the edge of the wafer. Wafer center. This step of forming the intermediate contact hole 300 is generally called " SA (> 1 etching step ".) Next, referring to FIG. 4, "SAC-1 etching step",

447036

When the flow ratio of CF4, CO'Ar, and & etc. etching gas, that is, adding 〇2 as a reaction gas' to perform polymer etching (p 〇1 y JJ] e Γ removal) step to avoid etching Stop (etch stop). This step is generally called " S A C-2 # 刻 步骤 " ’is used to form another intermediate contact hole 300 ′. V. Description of the invention (7) Secondly, referring to FIG. 5, the appropriate flow rate of% is passed in, and the liner layer 200 is removed through the middle contact hole 300 to form a one-bit wire connected to the window 30 (Γ. Hungary In this embodiment, an oxide insulating layer is engraved on a shoe to form a bit line contact window as an example. However, the inventive concept of adjusting two-stage or more etching at different electrode intervals can also be applied to the etching of other materials, such as Crystal silicon = material, metal material. Furthermore, the present invention is applicable to machines at any distance to improve the uniformity of the entire semiconductor wafer: the comparison example of the entire electrode & phase ratio ΓΛ to Λ one stage SAC-1 silver The distance between the first electrode 511 and the second electrode E2 in place of the example is set to 32mm, and the distance between the first electrode 511 and the second electrode E2 is calculated. The concentration and quantity of the square used in the comparative example are particularly reactive. The entire 1+ conductor wafer edge layer of ions is formed with :::: uniformly, the result is that the oxidation formed in the center of the wafer is completely different. The etching rate of the oxide insulating layer of a round edge is somewhat poor. Inventive features and effects ^ Invention Provides-Kind of Reactivity The etching step selects two or more stages of etching 1 " From the same 447036 V. Invention description (8) Pole pitch, the uniformity of the I-etching at each position of the semiconductor wafer is improved, thereby ensuring the performance of the semiconductor element. Although the present invention The above embodiments have been disclosed as above, but they are not intended to limit the present invention. Any person skilled in the art can make changes and decorations without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be Subject to the scope of the attached patent application.

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Claims (1)

4470 3 6 Six 'application patent scope 1. A method for manufacturing a bit line contact window, which is suitable for a semiconductor substrate having a gate electrode formed. The above manufacturing method includes the following steps: (a) forming an oxide insulating layer on the semiconductor substrate; (b) moving the semiconductor substrate with the oxide insulating layer formed thereon to a reactive ion etching reaction chamber, which has a first electrode and a second electrode for carrying the semiconductor substrate; (c) selective silver engraving The oxidized insulating layer forms a one-bit line contact window on the side of the gate electrode, which includes at least a first stage touch engraving and a second stage money engraving. The electrode and the second electrode have a first distance, and during the second-stage etching, the first electrode and the second electrode have a second distance. 2. The method of manufacturing a bit line contact window as described in item 1 of the patent application scope, wherein the first pitch is greater than the second pitch. 3. The method of manufacturing a bit line contact window according to item 2 of the scope of the patent application, wherein the first pitch is approximately 33 to 37 mm, and the second pitch is 27 to 31 mm. 4. The method for manufacturing a bit line contact window as described in item 3 of the scope of patent application, wherein the first pitch is about 3 mm ′, and the first pitch is about 2 7 mm. The method for manufacturing a bit line contact window according to item 1, wherein the first pitch is smaller than the second pitch. 6. The method of manufacturing a bit line contact window as described in item 1 of the patent application scope, wherein the processing time of the first-stage etching is between 30 and 40 seconds. 4470 3 6 VI. Scope of patent application 7. The method for manufacturing a bit line contact window as described in item 6 of the scope of patent application, wherein the processing time of the second-stage etching is between 35 and 40 seconds. 8. The method for manufacturing a bit line contact window according to item 1 of the scope of the patent application, wherein step (c) etching the halogenated insulating layer uses CF4, CO, and Ar as the reaction gases. 9. The method for manufacturing a bit line contact window according to item 1 of the scope of the patent application, wherein after step (c), a polymer etching step is further included to prevent the remaining stoppage. 10. The method for manufacturing a bit line contact window as described in item 1 of the patent application scope, wherein the polymer etching step uses eh, co, Ar, and 0 as reactive gases. 2 11. The method for manufacturing a bit line contact window as described in item 1 of the scope of the patent application, wherein the oxide insulating layer is composed of a borophosphosilicate glass breaking material and a dream material. 12. · A method of reactive ion etching, including the following steps, providing a semiconductor substrate with a material layer to be etched formed on its surface. The semiconductor substrate with the material layer to be etched is formed as described above. Chamber, the reaction chamber has a first arrow & a reverse. Jujube electrode and a second electrode carrying the semiconductor substrate with a clip; selective etching of the above-mentioned material layer to be etched, which includes at least-a stage etching and a first Two-stage etching, the first step is performed. The first electrode and the second electrode have a first distance. The electrodes have a second pitch. 13 Page 13 4470 36