TW444259B - Fabricating process of thin ball grid array substrate - Google Patents

Abstract

This invention is about the fabricating process of thin ball grid array substrate. In this invention, a thin copper surface layer is first sputtered on a polyimide film and is followed by electroplating a thicker copper layer on the copper surface layer. After that, the thicker copper layer is covered with a photosensitive coating, which is then separated by an appropriately treated mask (having the disposed circuit track) so as to be irradiated and underexposed. Therefore, the corresponding position on the photosensitive coating layer with respect to the circuit track of mask is etched away so as to form a circuit track of photosensitive coating that is recessed to copper layer. The manner of electroplating is used to make the thickness of copper circuit track become thicker. Substrate that is not protected by the bottom photosensitive coating is etched away. Metal material (such as lead tin alloy 63Sn/37Pb) is electroplated inside the recessed track of the front photosensitive coating. After removing the photosensitive coating and etching away the excess copper route, the process is completed.

Description

4442 5 9 V. Description of the invention (1) Field of the invention: The present invention is a thin ball grid array (TBGA) substrate (Prcess) process, mainly to overcome the conventional thin ball grid array substrate The process of plating high circuit lines by electrolytic plating will leave the plated circuits on the substrate, resulting in the lack of poor electrical characteristics of the substrate. 'Furthermore, it has developed an advantage that can use the plating method to plate high circuit lines.' The plating line remains on the substrate. Know-how: General portable mobile electronic and electrical equipment pays attention to characteristics such as lightness, thinness, and small size. Therefore, a thin ball grid array substrate is often used as an application motherboard, and the circuit layout of the conventional thin ball grid array substrate is widely used. The process is generally based on electrolytic electricity and electroless plating (ie, electroless plating). The electrolytic plating process is shown below (see Figures 1 to Ik): Process a: Use polyimide η thin film layer (p (Iyimide film) as the carrier 1. Process b: Sputter a thin layer of copper 12 on the polyfluorene ammonium 11 film layer. »Process c: Electroplating a relatively thick copper layer 13 on the surface of the thin layer 12 of the carrier 1 copper. Process d: Apply the entire layer of 14 layers of laminated photosensitive paint to the upper and lower layers of the carrier 1 with an appropriate thickness. Process e: A photomask 15 ’is provided above the top layer and below the bottom layer. The photomask 15 has a light-transmitting circuit track 151,

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And be exposed. Process f: After exposure processing, the photoresist is removed from the layer 14 of the laminated photosensitive paint with respect to the circuit track 151, and the rest is left, so that a concave circuit trace is formed on the laminated photosensitive paint layer. β process g: a layer of copper 16 is mined on the copper layer 13 on the bottom surface of the copper circuit 16 ′ on the surface of the concave circuit track to make it the same height as the layer 14 of the laminated photosensitive paint. Process h: An etching operation is performed on the bottom layer, so that the polysilicon thin dielectric layer at the position of the circuit traces removed by the process f development is eaten. Process i: Wash away the 14 layers of the photosensitive coating with a chemical agent. Process j: Remove the excess part of the copper layer 13 on the surface, leaving only the circuit wire 19 and its plating line 17 (see Figure 所示 κ). Process k: Use the plating line 17 to lead the positive and negative electrodes of the plating equipment to perform Electroplating operation 'coats each circuit line 19 with a metal plating layer 18 such as nickel or gold. Although the above electrolytic plating method can plate a thicker circuit thickness, and can choose more kinds of metals to be plated on copper lines', this method will leave plating lines, causing transmission delays, noise, The signal energy is attenuated and the electrical characteristics are not good. Another method is electroless plating (chemical plating). The existing circuit wires can only be covered with metals such as nickel (Ni), gold (Au), and tin (sn). The thickness is limited, but the biggest advantage is that there is no electroplated wire on the substrate. It has better circuit characteristics; there is no one process

4442 5 9 V. Description of the invention (3) A process method that can maintain the advantages of obtaining a thicker circuit plating layer by electrolytic plating, and eliminate the plating line to obtain effective electrical characteristics. The disclosure of the present invention can provide the advantages of the two processes of pre-exposure, that is, both more plating types of metal can be used for plating, and thicker circuits can be plated without leaving the plating lines on the substrate. Process. In order to achieve the above-mentioned object of the present invention, and to better understand the structural principle used by it, the following is described with a simple diagram: Specific embodiments: The present invention is mainly a thin ball grid array (TBGA) substrate (Substrate) The manufacturing process can overcome the current conventional thin ball grid array substrate manufacturing process, which cannot only consider the advantages of "electroless plating" and "electrolytic plating", and then develops an advantage that can use the plating method to plate high circuit line thickness without This plating line is left on the substrate process. Please refer to Figures 2a to 2k and refer to the following a to t processes. First: Process a: Use polyimide 21 film layer (poiyimide fiini) as the body 2. Ά Process b: In order to grow a copper layer 23 on the polyfluorene ammonium 21 film layer, a thin steel layer 22 is sputtered on the polyfluorene ammonium 21 film layer. Process c: A relatively thick copper layer 23 is plated on the entire surface of the thin copper layer 22 of the carrier 2 as a medium for subsequent electroplating. Process d: The upper and lower layers of the monolithic carrier 2 are coated with 24 and 25 layers of photosensitive paint on the upper and lower layers of an appropriate thickness.

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V. Description of the invention (4): A photomask 26 is provided above the top layer and below the bottom layer, and the photomask 26 has a light-transmitting circuit trace 261, and is exposed (exposure). Process f: After exposure Developed after processing, the radon was removed from the upper and lower layers of photosensitive paint 24 and 25 relative to the circuit line configuration track 261, and the rest was left, so that recesses were formed on the upper and lower layers of photosensitive paint 24. Circuit diagram 241,251 of the circuit layout JW -to · g • Copper 27 on the surface of the carrier 2 is forged with copper 27 ', and the copper layer 23 under the circuit trace 241 of the ej is plated with a layer of copper 27, the height and The upper 24 layers of photosensitive paint are slightly lower. Process h: An etching operation is performed on the bottom layer of the carrier 2 to remove the recessed circuit trace 251 on the bottom surface, that is, the polyimide film not covered by the laminated photosensitive coating 25 is eaten. Process i. Electroplating on the copper 27 of the carrier complex surface (ie, at the position of the recessed circuit trace 241) with a metal material 29 (such as tin-lead alloy 63Sn / 37Pb) connected to the solder, The upper build-up photosensitive paint 24 has the same height. Process j: The remaining upper layer of photosensitive paint 24 and the lower layer of photosensitive paint 25 are washed away with a chemical. Process k: Etching removes the excess part of the copper layer 23 on the surface, leaving only the circuit line 3 (as shown in Figure 2K (Shown) and the metal material 29 to which the material is connected. Accordingly, after the process of the present invention is completed, a solder ball can be directly applied on the metal material 29 connected to the solder. So there is no need to stay on circuit line 3

4442 5 9 V. Description of the invention (5) The nickel plating and gold plating must be used as the conventional plating line 17, and the present invention is used when the copper layer 23 is electroplated with copper 27 (process g) (not shown in the figure). It has also been removed by etching with the copper layer 23 during the process k. Therefore, the present invention can apply the electroplating method to obtain a better thickness of the circuit line 3, and can remove the electroplated line that causes poor electrical characteristics, which overcomes the conventional process Missing good way. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection shall also refer to those defined in the appended patent application scope.

Page 10 ο 9 Brief Description of Drawings Figures la ~ lk are schematic diagrams of the electrolytic plating process of the conventional TBG Α substrate. Figure 1K is a schematic perspective view of Figure 1f. Figures 2a to 2k are schematic diagrams of the TBG A substrate manufacturing process of the present invention. Figure 2K is a schematic perspective view of the second figure. Explanation of symbols used in each drawing: 1. Carrier 1 1. Polyammonium cyanide 12. Copper 1 3. Copper layer 1 4. Laminated photosensitive paint 15. Photomask 1 5 1. Circuit trace 1 6 and copper 1 7. Plating Line 18. Nickel, gold and other metal plating layer 1 9. Circuit wire 2. Carrier 21. Polyammonium polyimide 22. Copper 23. Copper layer 24. Upper layer of photosensitive coating 241. Recessed circuit track 25. Lower layer of photosensitive Paint 251. Four-entry circuit track

Page 11 4 Schematic description 26. Mask 2 6 1. Circuit track 2 7 ‘Copper 29. Metal material for solder connection 3. Circuit wire

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Claims (1)

4442 5 VI. Scope of patent application A thin ball grid array substrate manufacturing process is a process that can plate the substrate circuit to a better thickness and remove the plating lines on the substrate; the process is as follows: Process a: using polyammonium The thin film layer is used as a carrier; Process b: Sputtering a thin copper layer on the polyfluorene ammonium film layer; Process c: Quickly plating a relatively thick copper layer on the surface of the thin copper layer of the carrier; Process d: In The upper and lower layers of the carrier are coated with the entire thickness of the upper and lower layers of the photosensitive coating layer. Process e: a photomask is provided above the top layer and below the bottom layer, and the photomask has light-transmitting circuit traces. And exposure processing; process f: after exposure processing, development, the photoresist is removed on the upper and lower layers of the photosensitive paint layer with respect to the position of the circuit circuit configuration track, and the rest is left, so that the upper and lower layers of the photosensitive paint are laminated A recessed circuit trace configuration diagram is formed on the layer; process g: copper is plated on the surface of the carrier, and a copper layer is plated on the copper layer under the recessed circuit trace, the height of which is sensitive to the upper layer The material layer is slightly lower. Process h: the bottom of the carrier is subjected to an etching operation, and the concave circuit traces of the bottom surface that are removed, that is, the polyimide film layer not covered by the laminated photosensitive coating is eaten; process i: at The copper on the surface of the carrier (that is, the position of the recessed circuit trace) is plated with a metal material connected to the solder, so that Page 13 4442 5 9 6. The scope of the patent application is the same as that of the upper layer of the photosensitive coating; Process j: the remaining upper layer of the photosensitive coating layer and the lower layer of the photosensitive coating layer are washed away with a chemical agent; the process k: etching removes the surface For the rest of the circuit line, only the circuit line and the metallic material connected to the solder remain. Page 14