443038 C7 _ P7____ 五、創作説明（丨） 本發明是有關於一種類比至數位轉換器，特別是關 於具有雙軌式摺疊器之高速高解析度的類比至數位轉換 器，結構簡單且具較高可靠度，又能消除信號閃爍的現 象，並提高每個細格分出的位元數，以提高信號處理速 度以及信號品質。 經濟部中央揉準局貝工消費合作.杜印裝 (#先閏讀背面之注意事項再填寫本頁) 習用類比至數位轉換器中，使用摺疊器以及比較器 ，將類比輸入信號轉換爲數位資料。參閱圖一，一般摺 疊器結構，以摺八疊之摺疊波爲例，係包含有八對CMOS 差額對，其中每個CMOS差額對的一 CMOS元件得閘極 爲輸入信號 Vin的輸入端，而另一輸入端則分別輸 .入Vrefl , Vref2，〜Vref9 ,—般是等間距分壓，每個CMOS 差額對的CMOS汲極並聯在一起，形成Vout+,而另 一 CMOS 汲極也並聯在一起，形成 Vout·, 而V〇ut = V〇Ut、Vout-。圖二A與B分別顯示出摺二疊， 摺四疊與摺八疊之摺疊波以及對應的位元値。圖二A的 曲線F8爲該摺八疊之摺疊波的轉換函數。如果只使 用 Vref2, Vref4，Vref6，Vref8，則得到圖二 A 的曲線 F4 ，亦即爲摺四疊之摺疊波。同理，如果只使用 Vref4 與Vref8，則得到圖二A中摺二疊之摺疊波的曲線f2。 如果將上述F*，F4 , F2以比較器取出高低準位，亦即數 位信號，得到圖二B所示的三高位元資料，B8, B7, B,。 利用取樣保持器取出類比輸入信號，在由摺疊器將取樣 保持器的輸出信號轉換成摺疊波信號，接著經複數個比 本紙張尺度迸用中國囷家橾準（CNS ) 格（210X297!釐) 經濟部中央標準局員工消費合作社印策 443038 C7 _ D7 五 '創作説明（1 ) 較器取出數位資料，而這種架構的轉換器對於一個九位 元快閃高速類比至數位轉換器來說，共需要五百一十二 個比較器。此外，雖然可以利用比較器將摺二疊，摺四 疊與摺八疊之摺疊波轉換成三高位元資料，但不幸的是 ’高三位元資料（U8 、U7 ' U6)之狀態轉變値不盡相 同 '會導致暫時性錯誤，產生信號的誤解現象。 習用類比至數位轉換器需要大量的放大器緩衝器， 且低位元處理器需要使用4組摺八疊之摺疊波，而高位 元需要八個快閃比較器，需較多的晶片面積且電路較複 雜，整體電路的可靠度較低。 習用類比至數位轉換器利用類比平均 (analog averaging)來修正偏移器（interpolation block) 中等效電阻（R)所產生的直流誤差，.所以需增加額外電路 ，並占用較多的晶片面積。 此外，習用類比至數位轉換器中每個細格只分出一 個位元，效率較低，無法大幅提高信號處理速度。 進一步來說，習用類比至數位轉換器若不含位元同 步電路，會造成誤差碼，使輸出信品質降低。 因此很需要一種結構簡單且具較高可靠度的高速高 解析度類比至數位轉換器，又能消除信號誤解現象，並 提高每個細格分出的位元數，以提高信號處理速度。 本發明的主要目的在於提供一種類比至數位轉換器 ，利用摺疊器與比較器將輸入類比信號轉換成數位資料 本紙張尺度適用中國國家標準（CNS〉A4現格（210X297泰釐） (诗先閱讀背面之注意事碩再填寫本頁) 4.43 0 C7 D7 五、創作説明（>) ，其中摺疊器產生各有二組的摺二疊，摺四疊與摺八疊 之摺疊波，二組摺二疊與摺四疊之摺疊波經高位元雙軌 m- 式摺疊處理器，產生高三位元資料，而二組的摺八疊之 摺疊波經等相偏移器的相位移動處理後，產生32相位信 號，給下一級的比較器取出數位資料，再經編碼器編碼 處理取得中段五位元資料。另外，以此五位元値饋回細 格選擇器，選出正確細格邊線第K、K+ 1、K+16、及K+17 相移位波，再利用快閃比較器比較第Κ+ 1 6相，第Κ相與 第Κ+ 1相之中間値（或第Κ+ 1 6相與第Κ+ 1 7相之中間値 和第Κ+ 1相比較），經簡單邏輯運算得最小一位元。最 後將這九位元作溢載處理後，由閂鎖器讀取正確數位化 資料。 經濟部中央標準局員工消費合作杜印策 (讀先閱讀背面之注意事項再填寫本頁) 本發明的另一目的在於提供一種類比至數位轉換器 ，利用三段式轉換，對於九位元解析度的轉換器，分別 取出三個高位元，五個中段位元與一個低位元的數位資 料，可以只使用35個比較器來實現，與習用技術中需要 5 1 2個比較器來做比較，大幅降低元件數目，進而簡化 整體架構，提升電路的可靠度，並進一步降低消耗功率 。本發明之最後一級，利用高速快閃比較器，使其擴充 性大爲提高，本實施例僅使用一位元快閃比較器，只要 信號在進入快閃比較器之前被放大十數倍，便可改採用 4位元快閃比較器，而輕易的提高解析度到1 2位元。 本紙張尺度適用中國國家梠車（CNS )八4規| ( 210X297备嫠} 〇3 8 C7 D7 五、創作説明（今） (請先閱讀背面之注意事項再填寫本頁) 本發明的進一步目的在於提供一種類比至數位轉換 器，利用雙軌式摺疊處理器取得高位元資料，消彌誤解 現象，提高信號品質。 ®氏之簡單說明 ί 圖一爲一般摺疊器結構。 圖二Α與Β.分別顯示出摺二疊，摺四疊與摺八疊之摺.疊 波以及對應的位元値。 圖三爲依據本發明類比至數位轉換器的功能方塊圖。 圖四爲依據本發明雙軌式讀取之資料圖。 ' .圖五爲依據本發明將F8偏移十一點二五度共三十一次 後所產生的三十二相摺疊波形圖。 圖六爲依據本發明第k個細格結.構。 圖七爲等相偏移器之基本結構。 經濟部中夬揉準局貝工消費合作杜印褽 圖式中之參考數號 1 取樣保持器 3 時脈產生器 1 1參考電壓產生器 摺疊器 1 5寺相偏移器 1 7細格選擇器 19高位元摺疊處理器 本紙張尺度適用中國國家標率(CNS ) 210X297^·釐) 卜 443038 C7 D7 五、創作説明（ζ ) 23快閃比較器 25比較器 27編碼器 29閂鎖器 茲將本發明的內容配合相關圖式以及最佳實施例做詳細 的說明。 參閱圖三，本發明類比至數位轉換器的功能方塊圖 ，其中該類比至數位轉換器包含一取樣保持器1，一時 脈產生器3，一參考電壓產生器11，一摺疊器13，一等 /. 1 . 經濟部中央標準局貝工消費合作社印繁 {讀先閱讀背面之注意事項再填寫本頁) 相偏移器15，一細格選擇器I7，一高位元雙軌式摺疊處 理器19，一快閃比較器23，複數個.比較器25，一編碼器 27，以及一閂鎖器29,其中取樣保持器1取出類比輸入 信號，摺疊器13會將取樣保持器1的輸出信號轉換成各 有二組摺二疊，摺四疊與摺八疊之摺疊波，二組摺二疊 與摺四疊之摺疊波給高位元雙軌式摺疊處理器19，二組 .摺八疊之摺疊波給等相偏移器15。高位元雙軌式摺疊處 理器19會產生三高位元資料，而等相偏移器15將摺八 疊之摺疊波偏栘三Η•• —次，每次Η~ —點二五度，產生三 十二柜摺疊波形給細格選擇器1 7。細格選擇器1 7選取 所需的細格，再以三十二個比較器，同時數位化此三十 丨二相摺疊波形，經編碼器2 7編碼成中段五位元資料。 本紙張尺度適用中國國家標率（CNS ) Α4規格（210Χ297厶釐） 經濟部中央捸準局員工消费合作杜印袋 443038 C7 D7 五、創作説明（k ) .細格選擇器17選取一細格給後級的快閃比較器23，比 較第K相與第K+ 1相之中間値，以及第K+〗6相與第K+ 1 7 相之中間値，經邏輯運算得最小一位元。最後將這九位 元作溢載處理後，由閂鎖器29讀取正確數位化資料， 時脈產生器3發出三個連續非重疊時鐘訊號CP0 ' CPI、 CP2。當CP0時，讀取前一週期轉換之正確 九位元；重新取樣待轉換之類比信號，旋即將之推入摺 疊器中，得到F 2、F 4、Fs，如圖二A所示。接著利用電 阻分壓方法，將Fs合成偏位三十二相，數位化後編碼成 五位元（K);當CP1時，將F2 ' F4、F*以雙軌游走方式 ’編碼成高段三位元；當CP2時，選取第 K小網格πιΚ (由之第ί^Κ+Ι,Κ+Ιό,Κ+η相偏位所圍），以第Κ+16 或Κ+17相偏位値，和第Κ，Κ+1相偏位平均値AVE比 較’取'得正確最小位元。以上所得九位元，將於下一個CP0 時被讀取並輸出，如此周而復始地轉換出一筆筆並列九 位元碼。 本系統的目的在於將轉換範圍內（1^至xw)的類比電 壓轉換成九位數位資料，亦即， y=[512 (x-Xj. )/(.xff-x£)] 爲方便說明，我們輸入一斜波S= f ( t ) =x，開始時 x爲 零伏特’結束時 x爲五伏特。以射極偶合對（ECP )陣 本紙張尺度適用中國圉家標準（CNS )八4见格（2ϊΟΧ297先釐） — in n^i— Λ ^^^^1 tt _ - 国 n si (诗先閱讀背面之注意事項再填寫本頁) 訂 443038 C7 D7 經濟部中夹搮準居貝工消費合作社印製 五、創作説明（7 ) 列組成之摺疊器，將此一斜波折疊成：二折、四折及八 折等三條近似餘弦波之摺疊波，以 F 2、F ,、SF分別近 似之，如圖二A所示，表示爲 F： = c 〇 s Θ j 其中㊀』=J = 2,4,8 使用比較器完成類比信號的數位化，即 若A>0則令《A》= 0; 若A<0則令《A》= l: 理論上，我們若數位化 F 2、F 4、Fs ，即可得高三位元 値Μ 3 : M3 = 22-Us + 2'-U7+2°-U6 其中=《F2》；υ7二《F4》；U6 =《Fs》. 但是，U8 、U7、 116之狀態轉變之對應輸入値不盡 相同’將導致錯誤碼因此本系統以雙軌式讀取法，利 用雙套摺疊及簡單邏輯線路消除該現象。讀取之値和原 値間’僅有些許邏輯延遲，而幾乎爲即時信號。 上述雙軌式讀取法之說明如下： 參閱圖四，依據本發明雙軌式讀取之資料圖。將原摺疊 器之參考電壓，調降（ΧγΧ/)/16後得F2_ = Sin(e2-7i/8); F4'=sin(04-7r/4); (请先閲讀背面之注意事項再填寫本頁) i }| 裝' 訂 1S線 本紙張尺纽用 t ® ) Λ4^ { 210Χ297Γ* ) C7 D7 <4303β 五、創作説明（？） 其中X ^爲ADC輸入最大値，而X i爲ADC輸入最小値 Ρ8'=5ΐη(θ8-π/2); 數位化後得第二軌値Μ 3 _ : Μ 3'=Ug ' * 2 2 + U 7' * 21 + U 6 · 2 U8，“F〆》；。’ =《F4_》；ΐν =《FS’》 今將U 6細分成四相： a、第二、三相時，取第一軌，即正確高三位 元 [BSB7B6]=[USU7U6] ; T3=M3 。 b '第一相時，取第二軌’即正確高三位 元 [BSB7B6] = [US，U7，U，6] ; Τ3=Μ3·。 c '第四相時，取第二軌，即正確高三位 元[B8B7B6] = [IVU/U6•卜 1 ; Τ3=Μ3· ·1。 正確的高三位元値Τ 3，在兩軌之間游走，迴避誤解點， 得八個大網格，消除了誤解現象，編碼成高三位 元[BSB7B6]。 本系統接著切割每大網格Μη(η = 0〜7)，成十六小網 格k(k = 0〜15)，方法如下： 參閱圖五，依據本發明將？8偏移十一點二五度共三 十一次後所產生的三十二相摺疊波形圖。將 Fs偏移 k7t/16強度，令 k = 0~31得三十二條曲線 Fsk(k = 0〜31) ’此三十二條曲線在 X軸上形成十六個等距網格 m t 本紙張尺度適用中國國家梯丰（CNS ) A4現格（210X297^釐} (讀先聞讀背面之注意事碩再填寫本頁) -裝---- in - 1— 經濟部中央#準局員工消費合作社印製 443038 經濟部中央標準局員工消費合作.杜印策 C7 D7 五、創作説明（气） ，稍後證明： FSk = s i η ( θ8 - k7i / 1 6 ) =sin08· cos ( ku/16) + cosGs - sin(kn/16) =AkFg + BkFg ' (k = 〇 ,1,2...7 keN) 其中 Av = cos(k7t/16) ; Bt = sin(kTW16); 故F8k可以依據FS、F/兩曲線，藉由電阻分壓方式 合成如下，此組電阻稱爲等相位偏移器： k=0 : A〇 =0 ; B〇=：ri+r2+r3+r4+r5+r5+r-j+rg k~l . A| =Γ] ; Β]=Γ2+Γ3+Γ4+γ5+γ$+Γ7+γ8 : A2 =Γι+ r2 ; B2=r3+r,+r5+r6+r7+r8 k—3 . A3 —Γ]+ Γ2+ Γ3 , B3— r4-i-r5+ r6+ r7+ ig k=4 : A4 =r】+ r2+r3+i^ ; B4=r5+r6+r7+rg k=5 : A5 =rt+ r2-fr3+r4+r5 ; Bs=r6+r-j+r8 k=6 : =Γ)+ r2+r3+r^+r5+r6 ; B6=r7+r8 k=7 : A7 =r!+ r2+r3+r4+r5+r6+r7 ; By=r8 我們求出等效電阻値rk，依其比例取實際電阻値Rk ( Ω ) :(如圖七所示）443038 C7 _ P7____ V. Creation Instructions (丨) The present invention relates to an analog-to-digital converter, especially a high-speed, high-resolution analog-to-digital converter with a dual-track folder. The structure is simple and high Reliability, can eliminate the phenomenon of signal flicker, and increase the number of bits divided by each cell to improve the signal processing speed and signal quality. Central Government Bureau of the Ministry of Economic Affairs, Consumer Affairs Cooperation, Du Yinzhuang (#Please read the notes on the back and fill in this page) Custom analog to digital converter, use the folder and comparator to convert the analog input signal into digital data. Referring to FIG. 1, a general folder structure, taking folded waves folded as an example, includes eight pairs of CMOS differential pairs, in which a CMOS element of each CMOS differential pair is gated to the input terminal of the input signal Vin, and the other One input terminal respectively inputs Vrefl, Vref2, ~ Vref9, which are generally equally spaced voltage dividers. The CMOS drains of each CMOS differential pair are connected in parallel to form Vout +, and the other CMOS drains are also connected in parallel. Vout · is formed, and Vout = Vout, Vout-. Figures A and B show the folded waves of the folded two, folded four, and folded eight, respectively, and the corresponding bit chirp. The curve F8 in Fig. 2A is the conversion function of the folded wave. If only Vref2, Vref4, Vref6, and Vref8 are used, the curve F4 of A in Fig. 2 is obtained, that is, a folded wave folded in four. Similarly, if only Vref4 and Vref8 are used, the curve f2 of the folded wave folded in Fig. 2A is obtained. If the above-mentioned F *, F4, F2 are taken out of the high and low levels by the comparator, that is, the digital signal, the three high-bit data shown in Figure 2B are obtained, B8, B7, B ,. The sample holder is used to extract the analog input signal, and the output signal of the sample holder is converted into a folded wave signal by a folder, and then a plurality of paper scales are used in China (CNS) grid (210X297!). The Ministry of Economic Affairs Central Standards Bureau ’s Consumer Cooperative Cooperative Printing Co., Ltd. 443038 C7 _ D7 Five 'Creation Instructions (1) Take out digital data from a comparator, and this converter is a nine-bit flash high-speed analog-to-digital converter. A total of 512 comparators are required. In addition, although the comparator can be used to convert the folded wave of folded two, folded four and folded eight into three high-bit data, unfortunately, the state of 'high three-bit data (U8, U7, U6) does not change. 'Identical' can cause temporary errors and misinterpretations of signals. The conventional analog-to-digital converter requires a large number of amplifier buffers, and the low-bit processor needs to use four sets of folded waves, while the high-bit requires eight flash comparators, which requires more chip area and more complicated circuits. , The reliability of the overall circuit is low. The conventional analog-to-digital converter uses analog averaging to correct the DC error caused by the equivalent resistance (R) in the interpolation block. Therefore, additional circuits are required and more chip area is occupied. In addition, the conventional analog-to-digital converter only allocates one bit for each cell, which has low efficiency and cannot greatly improve the signal processing speed. Further, if the conventional analog-to-digital converter does not include a bit synchronization circuit, it will cause error codes and reduce the quality of the output signal. Therefore, there is a great need for a high-speed, high-resolution analog-to-digital converter with a simple structure and high reliability, which can eliminate signal misunderstanding and increase the number of bits per cell to increase the speed of signal processing. The main purpose of the present invention is to provide an analog-to-digital converter, which uses an folder and a comparator to convert the input analog signal into digital data. Read the notes on the back of the page and fill in this page) 4.43 0 C7 D7 V. Creative Instructions (>), where the folder generates two groups of folded waves, four folded waves and eight folded waves, two groups The folded waves of the folded two and folded four pass through the high-bit dual-track m-type folding processor to generate high-order three-bit data, and the folded waves of the two groups of folded eight are produced by the phase shift processing of the isophase shifter to generate 32-phase signal, take out the digital data to the comparator of the next stage, and then get the middle five-bit data through the encoder encoding process. In addition, the five-bit 値 is fed back to the grid selector to select the correct grid side K, K + 1, K + 16, and K + 17 phase-shifted waves, and then use a flash comparator to compare the K + 1 6th phase, the middle 値 between the K + 1 and K + 1 phases (or K + 1 6 phase) Compared with the middle 値 of the K + 1 7th phase and the K + 1 of the 7th phase), with simple logic The least bit is calculated. Finally, after the nine bits are overloaded, the correct digitized data is read by the latch. Du Yince, employee cooperation of the Central Bureau of Standards, Ministry of Economic Affairs (Read the precautions on the back before reading (Fill in this page) Another object of the present invention is to provide an analog-to-digital converter that uses a three-stage conversion. For a converter with nine-bit resolution, three high-order bits, five middle-order bits and one Low-level digital data can be implemented using only 35 comparators, compared with 5 1 2 comparators in conventional technology, which greatly reduces the number of components, thereby simplifying the overall architecture, improving the reliability of the circuit, and further reducing Power consumption. In the last stage of the present invention, a high-speed flash comparator is used to greatly expand its scalability. This embodiment uses only a one-bit flash comparator, as long as the signal is amplified by ten or more before entering the flash comparator. Times, you can switch to a 4-bit flash comparator, and easily increase the resolution to 12 bits. This paper size is applicable to China National Car (CNS) 8-4 regulations | (210X297嫠} 〇3 8 C7 D7 V. Creation Instructions (Today) (Please read the precautions on the back before filling out this page) A further object of the present invention is to provide an analog-to-digital converter that uses a dual-track folding processor to achieve high positions Metadata eliminates misunderstandings and improves signal quality. A brief description of ®'s. Figure 1 shows the general folder structure. Figures 2A and B. show the folded two, folded four, and folded eight, respectively. Figure 3 shows the functional block diagram of the analog-to-digital converter according to the present invention. Figure 4 shows the data map of the dual-track reading according to the present invention. 'Figure 5 shows the F8 offset according to the present invention. Thirty-two phase folded waveforms generated after a total of 31 times at 11.25 degrees. FIG. 6 is a k-th lattice structure according to the present invention. Figure 7 shows the basic structure of the phase shifter. The reference number in the scheme of the Ministry of Economic Affairs of the Chinese Ministry of Economic Affairs, DuPont, and India. 1 Sample Holder 3 Clock Generator 1 1 Reference Voltage Generator Folder 1 5 Temple Phase Shifter 1 7 Cell Selection 19 high-level folding processor This paper scale applies to China's national standard (CNS) 210X297 ^ ·)) 443038 C7 D7 V. Creative Instructions (ζ) 23 Flash comparator 25 Comparator 27 Encoder 29 Latcher The content of the present invention will be described in detail with reference to the related drawings and the preferred embodiment. Referring to FIG. 3, a functional block diagram of the analog-to-digital converter according to the present invention, wherein the analog-to-digital converter includes a sample-and-hold device 1, a clock generator 3, a reference voltage generator 11, a folder 13, and the like. 1. Printed by Fangong Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs {Read the precautions on the back before filling in this page) Phase shifter 15, a grid selector I7, a high-bit dual-track folding processor 19 A flash comparator 23, a plurality of comparators 25, an encoder 27, and a latch 29, in which the sample-and-hold 1 takes out the analog input signal, and the folder 13 converts the output signal of the sample-and-hold 1 There are two sets of folded waves, four folded and folded eight folded waves, two sets of folded folded and folded four folded waves to the high-bit dual-track folding processor 19, two groups. Folded folded eight波 给 等 相差 器 15。 Wave to the phase offset device 15. The high-bit dual-track folding processor 19 will generate three high-bit data, while the isophase shifter 15 will bias the folded wave by three times. •• —times, each time Η ~ —points 25 degrees, producing three Twelve cabinets fold the waveform to the fine grid selector 1 7. The grid selector 17 selects the required grid, and then digitizes the thirty-two two-phase folded waveforms with thirty-two comparators, which are encoded into the middle five-bit data by the encoder 27. This paper scale is applicable to China National Standards (CNS) A4 specifications (210 × 297mm). Consumption cooperation for employees of the Central Bureau of Standards of the Ministry of Economic Affairs Du printed bags 443038 C7 D7 V. Creation instructions (k). The grid selector 17 selects a grid To the flash comparator 23 at the subsequent stage, the intermediate 値 between the Kth phase and the K + 1th phase, and the intermediate 6 between the K + 6th phase and the K + 1 7th phase are compared, and the smallest bit is obtained by logical operation. Finally, after the nine bits are overloaded, the correct digitized data is read by the latch 29, and the clock generator 3 sends three consecutive non-overlapping clock signals CP0'CPI, CP2. When CP0, read the correct nine bits converted in the previous cycle; resample the analog signal to be converted, and then push it into the folder to get F 2, F 4, Fs, as shown in Figure 2A. Then, Fs is synthesized into 32 partial phases by using the resistance voltage division method, which is digitized and encoded into five bits (K); when CP1, F2 'F4, F * are coded into a high section in a dual-track walk mode. Three bits; when CP2, select the Kth small grid πικ (surrounded by the phase deviation of ^^ + Ι, Κ + Ιό, κ + η), and deviation with κ + 16 or κ + 17 Position 値, compared with the K, K + 1 phase-shifted average 値 AVE, 'take' the correct minimum bit. The nine bits obtained above will be read and output at the next CP0, so that a round of parallel nine-bit codes will be converted again and again. The purpose of this system is to convert the analog voltage in the conversion range (1 ^ to xw) into nine-digit data, that is, y = [512 (x-Xj.) / (. Xff-x £)] for convenience of explanation. We enter a ramp S = f (t) = x, where x is zero volts at the beginning, and x is five volts at the end. The paper size of the emitter coupled pair (ECP) array is applicable to the Chinese family standard (CNS) of 8 4 squares (2ϊ〇 × 297 first) — in n ^ i— Λ ^^^^ 1 tt _-country n si (诗 先Read the notes on the back and fill in this page.) Order 443038 C7 D7 Printed by the quasi-residential shellfish consumer cooperative in the Ministry of Economic Affairs. Fifth, a folder consisting of the instructions for creation (7). Fold this oblique wave into two: Folding waves of three approximate cosine waves, such as four, four, and eighty folds, are approximated by F 2, F, and SF, respectively, as shown in Figure 2A, expressed as F: = c 〇s Θ j where ㊀ ′ = J = 2,4,8 Use comparators to digitize analog signals, that is, if A > 0, let "A" = 0; if A < 0, let "A" = l: In theory, if we digitize F 2, F 4, Fs, you can get the higher three bits 値 Μ 3: M3 = 22-Us + 2'-U7 + 2 ° -U6 where = "F2"; υ7 "F4"; U6 = "Fs". However, The corresponding inputs of U8, U7, and 116 state transitions are different. This will result in an error code. Therefore, this system uses a dual-track reading method to eliminate this phenomenon by using double sets of folding and simple logic circuits. There is only a slight logical delay between the reading time and the original time, and it is almost an instant signal. The description of the above dual-track reading method is as follows: Referring to FIG. 4, a data chart of the dual-track reading according to the present invention. Reduce the reference voltage of the original folder by (× γχ /) / 16 to get F2_ = Sin (e2-7i / 8); F4 '= sin (04-7r / 4); (Please read the precautions on the back first Fill in this page) i} | binding '1S line paper ruler t ®) Λ4 ^ {210 × 297Γ *) C7 D7 < 4303β 5. Creation instructions (?) Where X ^ is the maximum ADC input 输入, and X i Enter the minimum 値 Ρ8 '= 5ΐη (θ8-π / 2) for the ADC; digitize to obtain the second track 値 M 3 _: Μ 3' = Ug '* 2 2 + U 7' * 21 + U 6 · 2 U8 "F〆"; '= "F4_"; ΐν = "FS'" Today, U 6 is subdivided into four phases: a. For the second and third phases, take the first track, that is, the correct three bits [BSB7B6] = [USU7U6]; T3 = M3. B 'When the first phase, take the second track' that is the correct high three bits [BSB7B6] = [US, U7, U, 6]; Τ3 = Μ3 ·. C 'Fourth phase At the time, take the second track, that is, the correct upper three bits [B8B7B6] = [IVU / U6 • Bu1; Τ3 = Μ3 ·· 1. The correct upper three bits, 値 Τ3, walk between the two tracks to avoid misunderstanding. Points to get eight large grids, eliminating misunderstandings, and encoding into high three bits [BSB7B6]. The system then cuts each large grid Μη (η = 0 ~ 7) , Into sixteen small grids k (k = 0 ~ 15), the method is as follows: Referring to FIG. 5, according to the present invention, the? 8 is shifted from eleven twenty-five degrees to thirty-two phases for a total of thirty-one times. Fold the waveform. Fs is shifted by k7t / 16 intensity, and k = 0 ~ 31 to obtain thirty-two curves Fsk (k = 0 ~ 31) 'The thirty-two curves form sixteen equidistant on the X axis Grid mt The size of this paper is applicable to China National Tifeng (CNS) A4 grid (210X297 ^ cent) (read the notes on the back first and then fill out this page)-installed ---- in-1— Central Ministry of Economic Affairs # Associate bureau employee consumer cooperative prints 443038 employee consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs. Du Yince C7 D7 V. Creative Instructions (Qi), which will be proved later: FSk = si η (θ8-k7i / 1 6) = sin08 · cos (ku / 16) + cosGs-sin (kn / 16) = AkFg + BkFg '(k = 〇, 1,2 ... 7 keN) where Av = cos (k7t / 16); Bt = sin (kTW16) Therefore, F8k can be synthesized according to the FS, F / two curves by the resistance voltage division method. This group of resistors is called equal phase shifter: k = 0: A〇 = 0; B〇 =: ri + r2 + r3 + r4 + r5 + r5 + r-j + rg k ~ l. A | = Γ]; Β] = Γ2 + Γ3 + Γ4 + γ5 + γ $ + Γ7 + γ8: A 2 = Γι + r2; B2 = r3 + r, + r5 + r6 + r7 + r8 k—3. A3 —Γ] + Γ2 + Γ3, B3— r4-i-r5 + r6 + r7 + ig k = 4: A4 = r] + r2 + r3 + i ^; B4 = r5 + r6 + r7 + rg k = 5: A5 = rt + r2-fr3 + r4 + r5; Bs = r6 + r-j + r8 k = 6: = Γ) + r2 + r3 + r ^ + r5 + r6; B6 = r7 + r8 k = 7: A7 = r! + r2 + r3 + r4 + r5 + r6 + r7; By = r8 We find the equivalent resistance 値 rk according to The ratio is the actual resistance 値 Rk (Ω): (as shown in Figure 7)
Rp3340, R 2= 2560, R 3= 2160, R 2000, R5=2000, R6=2l60 ,R7= 25 60 , Rf3340。 本紙張尺度通用中囤國家樣半（CNS ) A4洗格（2ΐ0χ297^β：) (請先閱讀背面之注意事項再填寫本頁) :裝 訂 4 4 3 0 3 8 C7 D7 __ 五、創作説明（f ) 此三.十二條曲線，在 X軸上之八大網格內’形成 —連串小網格 mj；(li = 〇~15)，各由 F8k，Fs(k + 】），F8(i； + 6) 翁· > F8E{): + ]7)四條曲線圍成，而每小網格再一分爲二1即 如果《F8k-F8(k+16)》=0 且《F8k-Fs(k + 17)》=1,則令 h = 0 ;如果《F8(k+1 >-F8(k + ]6>》=0 且《F8(k+i)-F8(k + 1”》=1 ’ 則令Bpl。故每大網格可被細分成三十二等分，將之編 碼成〔B 5HB 2B,〕。 以下證明此三十二細格在每大網格內等分 X軸，在b6=〇 時每一細格如下： A、當 θ= Q,時，Fsk = F8(k+16) sin(Qrk7r/16) = sin(Q丨-(k + 16) π/16) 得（^=：21ίπ/32 Β ® θ _ Q 2 時，F 8 k=F 8 (1； +") sin(Q2-kTt/I6) = sin(Q2-(k+17) π/16) 經濟部中央揉车局貝工消費合作杜印裳 C請先聞讀背面之注意事項再填寫本瓦) 得 Q2=(2k+1) τι/32 C、當 θ= Q3 時，Fm + fFm + w sin(Q3-(k+l) π / 1 6 ) = s i n ( Q3-( k+1 6 ) π/16) 得 Qi=(2k+1) π/32 =Q2 本紙張尺度( CNS ) A4iMM 210X297这釐） ^ 經濟部中央標隼局男工消费合作社印裝 Λ43038 C7 __D7___ 五、創作説明U ) D、當 h 時，Fso + udm+n) sin(Q4-(k+l) π / 1 6 ) = s i n ( Q4-( k+1 7 ) π/16) 得 Q4=(2k + 2) π/32 依據以上l 、Q2、Q3、Q4四點値，可得證每細格等距 /16 = (^-(33 = 7:/32 = 02-(^ Αθ = 8π· Ζ\χ/( 共八摺，每摺恰好1π) => Δχ = ( xH-Xi)/256 在B6=l時，因相位相反，每一細格如圖六所示。 同理可_證八3<:=( XwXiJ/256。故每細格寬皆爲全範圍 (Xh-xJ之二百五十六分之一，得證三十二細格在每大 網格內等分X軸。 在 X 軸附近，F8k = s i ne8k 三 08k (when 0<θ<π / 3 2 ) 我們觀察其中一細格： A、前半細格中，當ΒρΟ時，則以FSk爲上界， 爲下界（反之若B6=l時，以FEk下界’ Fs(k + 1>爲上 界）。求得 AF8=F8k- FMk + 1) = sin(9 -kn/]6)-(sin(9-(k+] )π/16)) =(Θ -k^/16)-(6-(k+l 本紙乐尺度適用中國圉家樣率（CNS ) A4洗格（_ 210Χ29·?β釐1 y;r 裝---1. J ^' /·' (請先閱讀背面之注意事項再填寫本頁) 訂 )u-n 443 03 8Rp3340, R 2 = 2560, R 3 = 2160, R 2000, R5 = 2000, R6 = 2l60, R7 = 25 60, Rf3340. This paper is standard in the national standard half (CNS) A4 wash case (2ΐ0χ297 ^ β :) (Please read the precautions on the back before filling this page): Binding 4 4 3 0 3 8 C7 D7 __ V. Creation Instructions ( f) The three twelve curves are formed in the eight major grids on the X axis-a series of small grids mj; (li = 0 ~ 15), each of which is F8k, Fs (k +)), F8 ( i; + 6) Weng · F8E {): +] 7) Four curves are enclosed, and each small grid is further divided into two 1 if "F8k-F8 (k + 16)" = 0 and "F8k -Fs (k + 17) '' = 1, then let h = 0; if `` F8 (k + 1 > -F8 (k +) 6 > '' = 0) and `` F8 (k + i) -F8 (k + 1 ”》 = 1 'makes Bpl. Therefore, each large grid can be subdivided into thirty-two equal parts and encoded as [B 5HB 2B,]. The following proves that the thirty-two fine grids are within each large grid Divide the X axis equally, and each cell is as follows when b6 = 〇: A. When θ = Q, Fsk = F8 (k + 16) sin (Qrk7r / 16) = sin (Q 丨-(k + 16) π / 16) gives (^ =: 21ίπ / 32 Β ® θ _ Q 2, F 8 k = F 8 (1; + ") sin (Q2-kTt / I6) = sin (Q2- (k + 17 ) π / 16) Du Yinshang C, Shellfish Consumer Cooperative of the Central Rubbing Bureau of the Ministry of Economy, please read the note on the back first (Fill in the tile again for the matter) We get Q2 = (2k + 1) τι / 32 C. When θ = Q3, Fm + fFm + w sin (Q3- (k + l) π / 1 6) = sin (Q3- ( k + 1 6) π / 16) get Qi = (2k + 1) π / 32 = Q2 This paper size (CNS) A4iMM 210X297 this centimeter) ^ Printed by the Central Standards Bureau of the Ministry of Economic Affairs of the Male Workers Consumer Cooperative Λ43038 C7 __D7___ , Creation description U) D, when h, Fso + udm + n) sin (Q4- (k + l) π / 1 6) = sin (Q4- (k + 1 7) π / 16) gets Q4 = ( 2k + 2) π / 32 According to the above four points l, Q2, Q3, Q4, it can be proved that each cell is equidistant / 16 = (^-(33 = 7: / 32 = 02-(^ Αθ = 8π · Zn \ χ / (total 20%, each fold is exactly 1π) = > Δχ = (xH-Xi) / 256 When B6 = 1, each phase is shown in Figure 6 due to the opposite phase. Card 8 3 <: = (XwXiJ / 256. Therefore, the width of each cell is the full range (one-two-half of Xh-xJ, which proves that the thirty-two cells divide the X axis equally in each large grid. Near the X axis, F8k = si ne8k Three 08k (when 0 < θ < π / 3 2) We observe one of the cells: A. In the first half cell, when Bρ〇, then use Fsk as the upper bound and lower bound (or vice versa if B6 = l, use FEk) Lower bound 'Fs (k + 1 > is the upper bound). Find AF8 = F8k- FMk + 1) = sin (9 -kn /] 6)-(sin (9- (k +)) π / 16)) = ( Θ -k ^ / 16)-(6- (k + l) This paper music scale is applicable to China's family sample rate (CNS) A4 wash case (_ 210 × 29 ·? Β 厘 1 y; r pack --- 1. J ^ ' / · '(Please read the notes on the back before filling this page) Order) un 443 03 8
Cl D7 五、創作説明（\v ) =κ / 1 6 ; △ C 1 ~ F S k ' F 8 ( k+i6)= sinGsk -s i η Θ g (+ ] 6 } =sinGSJi -(-s i n0Sk ) =2 s i ηΘ8k =2 Θ g k > ( 〕 △ C2 =7r/16-20gk > 0 (因前半細格中6^ < π/32 ) 得知 F 8 k > F 8 { k + ] 6 ) > 即 F 8 ( k 4 1 6 ) 値 在Fs k ' F 8 C k + 1 ) 之間，以 Fs( k+l6) 爲快閃轉換器之輸 入値， 取 Fk、F: k+l爲上下邊界値，並 2L 等分之， 可 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貞工消費合作社印策 得 2L- 1個參考電壓値，可轉換出 L位元。本實施 例中L爲1，表示1位元快閃比較器，同理4位元快閃比 較器時，L爲4。 B、後半細格中，改以 Fg(t+m 爲快閃轉換器之輸入 値，亦可轉換出 L位元。 在此一系統中 L=l，故 2L等分之，而得一個參考 電壓 AVE=(F8k + Fs(k + ] , ) / 2，使用一個比較器（一位元快 閃轉換器），轉換出最小一位元〔BQ〕。 當 Β6 = 0·時，前半細格中，即 Β1 = 0時， B〇=《A、iE-Fs(1:+16)》. 後半細格中，即 1 時， B(丨=《AVE-Fs(t：+i：M》， 本紙沬尺度適用中國囷家標準（〇奶）八4規格（21〇><2970釐） 443038 C7 D7 經濟部中央揉準局員工消費合作社印製 五、創作説明U巧） 當.B6=l時 ，刖半細格中，即B1 = 0 時 B〇=- +丨 6广 Av£》， 後半細格中 ，即B】: =1 時， B〇- 《Fs(V+17)' Ave》， 取後以九位元問鎖器，將攫取以上九位元資料。若 在輸入値小於中央參考電壓値，卻讀取到〔〗FF〕碼， 則判定超出下界，閂鎖器輸出碼〔〇〇〇〕；若在輸入値大 於中央參考電壓値’卻讀敢到碼〔〇〇〇〕，則判定超出上 界’輸出碼〔IFF〕；其餘則輸出所攫取之九位元資料碼 〇 由於以三段式編碼，大大減少比較器及放大器等大 面積元件之使用。所以本系統線路佈局面積小（約1 . 7mm: )。實際測試結果中，THD約爲-60 dB = 所以，利用快閃，摺疊偏移，以及分段分時轉換技 .術，將輸入的類比信號快速的轉換成數位信號，尤其是 使用雙軌式摺疊處理器取得高位元資料，消彌閃爍現象 ，提高信號品質，且整體電路具有較小的晶片面積，較 低的消耗功率，適於視訊頻率的應用。 綜上所述，當知本案發明具有實用性與新穎性，且 本紙張尺度適用中國國家榇率（CNS )六4况格（210><297适瘦） -------V /1 裝-- 〕 .. V . (請先閲讀背面之注意事項再填寫本頁) 訂 -VJ線 443038 C7 _____D7_ 五、創作説明（Vk ) 本發明未見之於任何刊物，當符合專利法規定。 唯以上所述者.，僅爲本發明之一較佳實施例而已， 當不能以之限定本發明實施之範圍。即大凡一本發明申 請專利範圍所作之均等變化與修飾，皆應屬本發明專利 涵蓋之範圍內。 II -. I !|I--- - Ϊ - - 11 m> 1 I I 1 -- - n^i d . /_-... * - .-. (請先閱讀背面之注意事項1填寫本頁) ---訂 經濟部中央摞準局員工消费合作社印策 [i.!----· 本紙張尺度適用中國國家標準（〇^)六4规格（2]0><：297这釐)Cl D7 V. Creation Instructions (\ v) = κ / 1 6; △ C 1 ~ FS k 'F 8 (k + i6) = sinGsk -si η Θ g (+) 6) = sinGSJi-(-si n0Sk) = 2 si ηΘ8k = 2 Θ gk > () △ C2 = 7r / 16-20gk > 0 (because 6 ^ < π / 32 in the first half of the cell) we know that F 8 k > F 8 {k +] 6) > That is, F 8 (k 4 1 6) 値 is between Fs k 'F 8 C k + 1), and Fs (k + l6) is the input of the flash converter 转换 器, take Fk, F: k + l is the upper and lower boundary 値, and it is divided into 2L. (Please read the precautions on the back before filling this page.) The Central Standards Bureau of the Ministry of Economic Affairs, Zhengong Consumer Cooperative, printed 2L-1 reference voltage 値, which can be converted into L bit. In this embodiment, L is 1, which indicates a 1-bit flash comparator. Similarly, when a 4-bit flash comparator is used, L is 4. B. In the second half of the grid, change Fg (t + m as the input of the flash converter, and also convert the L bit. In this system, L = l, so 2L is divided equally, and a reference is obtained. The voltage AVE = (F8k + Fs (k +],) / 2), using a comparator (1-bit flash converter), converts the smallest bit [BQ]. When B6 = 0 ·, the first half of the cell In the middle, that is, when B1 = 0, B0 = "A, iE-Fs (1: +16)". In the second half of the cell, that is, at 1, B (丨 = "AVE-Fs (t: + i: M" The standard of this paper is applicable to China's family standard (0 milk) 8 4 specifications (21〇 > < 2970%) 443038 C7 D7 Printed by the Central Consumers ’Bureau of the Ministry of Economy Staff Consumer Cooperatives Co., Ltd. V. Creation Instructions U)) B6 = 1, in the semi-small cell, that is, when B1 = 0, B〇 =-+ 丨 6Av £》, in the second half of the cell, that is, B]: when = 1, B〇- 《Fs (V + 17) "Ave", after taking the nine-bit interlock, the above nine-bit data will be fetched. If the input 値 is smaller than the central reference voltage 却, but reads the [〖FF] code, it is determined that the lower limit is exceeded, and the latch Output code [〇〇〇]; if the input 値 is greater than the central reference voltage値 'but read the dare code [〇〇〇], it is judged that the upper bound is exceeded [IFF]; the rest outputs the 9-bit data code that was taken. Because of the three-stage encoding, the comparator and amplifier are greatly reduced Use of large-area components. Therefore, the layout area of this system is small (about 1.7mm:). In actual test results, THD is about -60 dB = so, using flash, folding offset, and segmented time-sharing conversion Technology. Quickly convert the input analog signal into digital signal, especially using dual-track folding processor to obtain high-bit data, eliminate flicker phenomenon, improve signal quality, and the overall circuit has a smaller chip area and lower The power consumption is suitable for the application of video frequency. In summary, when this invention is known to have practicability and novelty, and this paper scale is applicable to China National Standard (CNS) sixty-four cases (210 > < 297) Thin) ------- V / 1 installed-] .. V. (Please read the precautions on the back before filling out this page) Order-VJ line 443038 C7 _____D7_ V. Creative Instructions (Vk) The present invention Seen in any publication, when patented The provisions of the law are the only ones described above. They are only one of the preferred embodiments of the present invention. When the scope of implementation of the present invention cannot be limited by this, that is, all equal changes and modifications made in the scope of the patent application for the present invention should be It is within the scope of the invention patent. II-. I! | I ----Ϊ--11 m > 1 II 1--n ^ id. / _-... *-.-. (Please first Read the note on the back 1 Fill out this page) --- Order the policy of the Consumers' Cooperatives of the Central Procurement Bureau of the Ministry of Economic Affairs [i.! ---- · This paper size applies to the Chinese National Standard (〇 ^) 6 4 specifications (2 ] 0 > <: 297 this cent)