JP2006262001A - Ad converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve converting capability by dispersing all over conversion errors generated exclusively to specific codes by relative errors of an internal circuit. <P>SOLUTION: An input analogue signal VIN and a plurality of reference voltages generated in a reference voltage generating unit 10 are amplified by a preamplifier 20 to be input to a replicate unit 30. There, a plurality of replicate signals is generated and then is sequentially and circularly switched by a switch unit 110 to be each amplified by a buffer unit 40, being input to a interpolation unit 50. Here, a plurality of interpolation signals is produced to compare relatively the interpolation signals and the replicate signals in a low-order comparator 60, then encoding the results compared in a low-order comparator 70 to produce low-order bits. Further, the input analogue signal VIN and the plurality of the reference voltages generated in the reference voltage generating unit 10 are compared by a high-order comparator 80 to encode the results compared in a high-order encoder 90 to produce high-order bits. Then, the low-order bits produced in the low-order comparator 70 and the high-order bits produced in the high-order encoder 90 are coupled in an output unit 100. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a folding / interpolating (folding / interpolating) type AD converter.

  FIG. 5 shows a schematic configuration of a folding / interpolating AD converter (see, for example, Patent Documents 1 to 3). This AD converter amplifies the input analog signal VIN and a plurality of reference voltages generated by the reference voltage generation unit 10 by the preamplifier unit 20 and inputs them to the folding unit 30, where the folding signals F0P, F0M, F1P, and F1M are input. Are generated and amplified by the buffer unit 40 having the buffers 41 to 44 and input to the interpolating unit 50, where a plurality of interpolated signals are generated and compared by the lower comparing unit 60, and the comparison result Is encoded by the lower encoder 70 to generate lower bits. Further, the input analog signal VIN and a plurality of reference voltages generated by the reference voltage generation unit 10 are compared by the upper comparison unit 80, and the comparison result is encoded by the upper encoder 90 to generate upper bits. Then, by combining the lower bits created by the lower encoder 70 and the upper bits created by the upper encoder 90 at the output unit 100, a converted digital signal is output. In this folding / interpolating AD converter, the interpolation signal is generated by the interpolation unit 50, so that the requirement of the input dynamic range of the comparator is alleviated, and as a result, high-speed AD conversion becomes possible.

  FIG. 6 shows characteristics of four return signals F0P, F0M, F1P, F1M output from the return unit 30 and a plurality of interpolation signals obtained by the interpolation unit 50 in the case of 6 bits (upper 3 bits, lower 3 bits) output. Show. By the reference voltages Vref1 to Vref8 generated by the reference voltage generation unit 10, the input voltage VIN is converted into the folding signals F0P and F0M having a complementary relationship and the folding signals F1P and F1M having a complementary relationship in the folding unit 30. . Note that the folding signals F0P and F1P have a phase difference of 90 degrees.

  The ranges (1) to (8) between the reference voltages Vref1 to Vref8 are identified by the upper 3 bits obtained by the upper comparison unit 80 and the upper encoder 90. One range identified by the upper 3 bits is identified as 8 levels by the lower 3 bits, which are four folding signals F0P, F0M, F1P, F1M output from the interpolation unit 50 in the next stage. The interpolation signals VR01P to VR07P, VR11P to VR17P, VR01M to VR07M, and VR11M to VR17M are compared by the lower comparison unit 60 and encoded by the lower encoder 70.

As shown in FIG. 7, the interpolating unit 50 includes a plurality of resistors R connected in a ring shape, and inputs folding signals F0P, F0M, F1P, and F1M to the four connection points, and the folding signals F0P, Signals VR01M to VR07M, VR11M to VR17M, VR01P to VR07P, and VR11PM to VR17P at the common connection points of F0M, F1P, F1M and each resistor R are input to the lower comparison unit 60. In the lower comparison unit 60, as shown in FIG. 8, the comparison is performed by 16 comparators 601 to 616, and the comparison result is input to the lower decoder 70 to obtain lower 3-bit conversion data.
Japanese Patent Application Laid-Open No. 08-274641 JP-A-11-251907 JP 2003-273657 A

  However, since this folding / interpolating AD converter processes the input signal VIN internally (folding and interpolation), an error occurs in the conversion result when the internal relative accuracy is low. For example, when there is a relative error in the interpolation unit 50, a conversion error is concentrated on a specific code.

  FIG. 9 is a diagram showing an interpolation characteristic having an error in the interpolation unit 50, and the upper bit ranges (1), (2), (4), (5), (6), (8) represented by 3 bits. The conversion characteristics of the lower-order bits in () are ideal characteristics, but there is an error in the conversion characteristics in the ranges (3) and (7).

  In the upper bit ranges (1), (2), (4), (5), (6), and (8), the conversion characteristics of the lower bits with respect to the input voltage VIN are linear as shown in FIG. The bit width (= appearance probability) of all the codes of the lower bits represented by 3 bits is an ideal state of 1/8. However, in the upper bit ranges (3) and (7), as shown in FIG. 10 (b), the conversion characteristics of the lower bits with respect to the input voltage VIN have an extremely narrow bit width of the code “011”. There is only 32, and the bit width of the code “100” is 7/32 which is extremely wide, and with this as it is, an error of ± 75% with respect to 1/8 which is an ideal bit width (see FIG. 11). ). When expressed in terms of linearity error of the AD converter, this corresponds to ± 0.75 LSB. As a result, among the digital values output from the output unit 100, the codes “010011”, “010100”, “110011”, and “110100” always have a large conversion error.

  An object of the present invention is a folding interpolating type AD conversion in which the conversion error generated only in a specific code due to the relative error of the internal circuit as described above is dispersed throughout to improve the conversion performance. Is to provide a vessel.

  In order to solve the above-mentioned problem, the invention according to claim 1 includes a reference voltage generating unit and a folding unit that generates a plurality of folding signals by comparing a plurality of reference voltages generated by the reference voltage generating unit and an input voltage. An interpolation unit that simultaneously inputs each folding signal created by the folding unit to create an interpolation signal, a lower comparison unit that mutually compares the interpolation signal created by the interpolation unit and each folding signal, and the lower level A lower encoder that encodes the comparison result of the comparison unit, an upper comparison unit that compares the input voltage with a plurality of reference voltages generated by the reference voltage generation unit, and an upper encoder that encodes the comparison result of the upper comparison unit And a folding interpolator comprising: an output unit that combines the output of the higher-order encoder and the output of the lower-order encoder and outputs a digital signal of a predetermined bit. In the AD conversion of the ring type, between the interpolation unit and the folded portion, characterized in that a switching unit for inputting to the interpolation unit switches the respective folding signals created by the folded portion.

  According to a second aspect of the present invention, in the AD converter according to the first aspect of the present invention, the switching unit sequentially switches the return signals cyclically at a predetermined cycle.

  According to a third aspect of the present invention, in the AD converter according to the first or second aspect, a buffer unit for amplifying each folding signal is provided between the switching unit and the interpolation unit.

  According to the present invention, since conversion errors that are likely to occur regularly in a specific code due to the relative error of the circuit are dispersed throughout, the performance of the AD converter can be improved.

  Embodiments of the folding / interpolating AD converter of the present invention will be described below. FIG. 1 is a block diagram showing an embodiment of the present invention, in which 10 is a reference voltage generator, 20 is a preamplifier having a plurality of preamplifiers for sampling and amplifying the reference voltage and the input voltage VIN, and 30 is a plurality of A folding unit that generates folding signals F0P, F0M, F1P, and F1M from the reference voltage and the input signal VIN, 40 is a buffer unit that includes buffers 41 to 44 that amplify the folding signals F0P, F0M, F1P, and F1M, and 50 is a folding signal F0P. , F0M, F1P, and F1M, an interpolation unit that generates an interpolation signal, 60 is a lower comparison unit that mutually compares the interpolation signal obtained by the interpolation unit 50 and the return signal, and 70 is a comparison result of the lower comparison unit 60 A low-order encoder, 80 is a high-order comparison unit that inputs and compares a reference voltage generated by the reference voltage generation unit 10 with an input signal 90 the upper encoder for encoding the comparison results of upper comparison portion 80, 100 is an output unit for outputting the synthesized output code of the lower encoder 70 and the upper encoder 90.

  In the present embodiment, a switching unit 110 for switching the folding signal is newly provided between the folding unit 30 and the buffer unit 40 in such a basic configuration. The switching unit 110 includes selectors (MUX) 111 to 114 that receive four return signals F0P, F0M, F1P, and F1M and output one of them according to the switching signal.

  FIG. 2 is an explanatory diagram of the switching operation of the switching unit 110. When the switching signal S1 is input, the signals VA, VB, VC, VD output from the buffers 41 to 44 are used as they are as the folding signals F0P, F0M, F1P. , F1M, but when the switching signal S2 is input, the return signals are F1M, F0P, F0M, and F1P. When the switching signal S3 is input, the return signals are F1P, F1M, F0P, and F0M, and the switching signal S4 is input. In some cases, the return signals F0M, F1P, F1M, and F0P.

  Therefore, when the switching signal is cyclically switched in the order of S1 → S2 → S3 → S4 → S1 → S2 →... (For example, switching for each sampling clock for sampling the input signal VIN), the upper 3 bits, In the case of performing conversion with the lower 3 bits, as described with reference to FIGS. 9 to 11 in the interpolation unit 50, for example, even when a conversion error occurs in the ranges (3) and (7) in FIG. The probability that the conversion error is diffused to other ranges and the conversion characteristics (B) of the codes “011” and “100” of the lower bits shown in FIG. 10B is ¼ in each range. .

  For this reason, the probability that the conversion characteristic (B) is in the state increases to the bit width of the code “010” of the lower 3 bits up to 13/128 and the bit width of the code “100” down to 19/128. This means that the linearity error is improved to an error of ± 18.75%, that is, ± 0.1875 LSB with respect to the ideal bit width 1/8.

  In this embodiment, since the buffers 41 to 44 of the buffer unit 40 are also switched, this can be mitigated even when a relative error occurs in the buffer unit 40.

  FIG. 4 is a block diagram showing another embodiment of the folding interpolating AD converter of the present invention. Here, the switching unit 110 is inserted between the buffer unit 40 and the interpolation unit 50 so that the folding signals F0P, F0M, F1P, and F1M are sequentially switched and input to the interpolation unit 50.

  Thus, even if the switching unit 110 is inserted between the buffer unit 40 and the interpolation unit 50, if a relative error occurs in the interpolation unit 50, this can be mitigated.

It is a block diagram of a folding interpolating type AD converter of an embodiment of the present invention. It is switching explanatory drawing of a present Example. It is explanatory drawing of the conversion error improvement of a low-order bit. It is a block diagram of the folding interpolating type AD converter of another Example of this invention. It is a block diagram of a conventional folding and interpolating AD converter. It is a characteristic view of a return signal and an interpolation signal. It is a circuit diagram of an interpolation part. It is explanatory drawing of a low-order comparison part. It is a characteristic diagram of a return signal and an interpolation signal when there is an error. It is explanatory drawing of the conversion characteristic of a low-order bit. It is explanatory drawing of the conversion error of a low-order bit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10: Reference voltage generation part 20: Preamplifier part 30: Loop-back part 40: Buffer part 50: Interpolation part 60: Lower order comparison part 70: Lower order encoder 80: High order comparison part 90: High order encoder 100: Output part 110: Switching part

Claims (3)

A reference voltage generation unit, a folding unit that creates a plurality of folding signals by comparing a plurality of reference voltages generated by the reference voltage generating unit and an input voltage, and each folding signal created by the folding unit are simultaneously input. An interpolation unit that creates an interpolation signal, a lower comparison unit that mutually compares the interpolation signal created by the interpolation unit and each folding signal, a lower encoder that encodes the comparison result of the lower comparison unit, and the reference voltage A high-order comparison unit that compares the input voltage with a plurality of reference voltages generated by the generation unit, a high-order encoder that encodes the comparison result of the high-order comparison unit, and an output of the high-order encoder and an output of the low-order encoder In a folding interpolating AD conversion comprising an output unit that outputs a digital signal of a predetermined bit
An AD converter characterized in that a switching unit is provided between the folding unit and the interpolating unit to switch the respective folding signals created by the folding unit and input the signals to the interpolation unit. The AD converter according to claim 1,
The AD converter is characterized in that the switching unit sequentially and cyclically switches the return signals at a predetermined cycle. The AD converter according to claim 1 or 2,
An AD converter comprising a buffer unit for amplifying each folding signal between the switching unit and the interpolation unit.

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