KR101200942B1 - Analog-digital converter and method thereof - Google Patents

Abstract

PURPOSE: An analog-digital converter and a method thereof are provided to increase accuracy by using folding and interpolation. CONSTITUTION: An upper signal processing part(120) generates an upper analog signal by amplifying an analog signal in a preset amplification ratio. A lower signal processing part(130) generates a lower analog signal by amplifying and folding the analog signal through an amplification line including an odd number of amplifiers. A comparison part(140) generates a comparison signal by comparing the upper analog signal and the lower analog signal according to a preset reference voltage. An encoding part(150) generates an upper digital signal by the upper analog signal and a lower digital signal by the lower analog signal according to the comparison signal. The encoding part generates an output signal by adding the upper digital signal and the lower digital signal. [Reference numerals] (110) Input part; (120) Upper signal processing part; (130) Lower signal processing part; (140) Comparison part; (150) Encoding part

Description

ANALOG-DIGITAL CONVERTER AND METHOD THEREOF

The present invention relates to an analog-to-digital conversion technology, and more particularly, to a technology for monitoring by photographing the surrounding conditions of a vehicle with a camera.

With the recent growth of the digital broadcasting market and the increase of high-performance multimedia devices such as HDTVs, digital set-top boxes (D-STBs), and Blu-ray players, medium-resolution (7 ~ 10b) analogs with high conversion speeds of several hundred MHz to several GHz The demand for digital converters is increasing. In the past, such high-speed analog-to-digital converters were mostly implemented using a flash structure, but the power consumption and area of the converter increases depending on the resolution. Accordingly, there is a growing interest in a folding-interpolation method that can reduce power consumption and area while satisfying a fast change speed of a flash-to-analog converter. In the folding-interpolation method, an odd number of input analog signals is an even higher accuracy of analog-to-digital conversion than an even number. Offset errors that occur during pre-amplification or folding signal processing of the original analog input signal are a major cause of degrading overall ADC performance. Therefore, if the number of pre-processing amplifiers is set to an even number, current averaging for the analog inputs received at the highest and lowest points of the reference voltage string is not symmetric, and thus, effective averaging is not possible. However, with conventional encoders, in an analog-to-digital converter including an odd number of preprocessing amplifiers, encoding is not possible in the encoding stage, which is the final stage of the folding-interpolation scheme.

The present invention proposes a folding-interpolation analog-to-digital converter capable of forming an odd number of input analog signals.

According to an aspect of the present invention, an upper signal processor for amplifying an analog signal at a predetermined amplification ratio to generate an upper analog signal; A lower signal processor configured to amplify the analog signal through an amplifier string including an odd number of amplifiers and to fold the analog signal to generate a lower analog signal; A comparator configured to compare the upper analog signal and the lower analog signal according to a predetermined reference voltage to generate a comparison signal; And an encoding unit configured to generate an upper digital signal according to the upper analog signal and a lower digital signal according to the lower analog signal according to the comparison signal, and add the upper digital signal and the lower digital signal to generate an output signal. An analog-to-digital converter is provided.

The encoding unit may include one or more half-adders for receiving a carry from one of the bits of the upper digital signal and another adder, and one of the bits of the upper digital signal and one of the bits of the lower digital signal and the other adder. It may include a full adder for receiving a carry.

The encoding unit includes: a first adder configured to add a third bit of the lower digital signal and a first bit of an upper digital signal; A second adder for adding a fourth bit of the lower digital signal, a second bit of the upper digital signal, and a carry output from the second adder; A third adder for adding a fifth bit of the lower digital signal, a third bit of the upper digital signal, and a carry output from the second adder 320; A fourth adder for adding a sixth bit of the lower digital signal, a first bit of the upper digital signal, and a carry output from the third adder 330; A fifth adder for adding a carry output from the second bit of the upper digital signal and the fourth adder; And a sixth adder configured to add a carry output from the third bit and the fifth adder of the upper digital signal.

The comparator may classify the level value of the upper analog signal into levels of eight sections, and classify the level value of the lower analog signal into levels of 26 sections.

The difference between the maximum value of the voltage levels of the reference voltage and the maximum voltage level that can be converted into the upper analog signal may be smaller than the reference voltage interval.

According to the present invention, it is possible to provide an analog-to-digital converter using a highly accurate folding interpolation scheme.

1 shows a simplified illustration of an analog-to-digital converter.
2A is a diagram illustrating a level value over time of an upper analog signal input to a comparator of an analog-digital converter.
2B is a diagram illustrating a level value with time of a lower analog signal of the analog-to-digital converter.
3 is a diagram illustrating an encoding unit of an analog-digital converter.

The present invention may be variously modified and have various embodiments, and specific embodiments will be illustrated in the drawings and described in detail with reference to the accompanying drawings. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Further, in this specification, when an element is referred to as " transmitting " a signal to another element, the element can be directly connected to the other element to transmit a signal, It should be understood that the signal may be transmitted by mediating another component in the middle.

1 is a view schematically illustrating an analog-to-digital conversion device.

Referring to FIG. 1, an analog-to-digital converter includes an input unit 110, an upper signal processor 120, a lower signal processor 130, a comparator 140, and an encoder 150.

The input unit 110 receives an analog input signal from the outside. The input unit 110 transmits an analog input signal to the upper signal processor 120 and the lower signal processor 130.

The upper signal processor 120 generates a discrete signal by sampling an analog input signal, amplifies the discrete signal according to a predetermined amplification ratio, and generates a higher analog signal and transmits the upper analog signal to the comparator 140. For example, the upper signal processor 120 generates eight discrete signals by sampling an analog input signal, and generates an upper analog signal obtained by amplifying the discrete signals through an amplifier string including eight amplifiers. 140).

In addition, the lower signal processor 130 generates an abnormal signal by sampling an analog signal, and generates a lower analog signal by folding, interpolating, and amplifying the discrete signal. That is, the lower signal processor 130 includes at least one amplifier string, a folding block, and an interpolation block. The lower signal processor 130 transmits the lower analog signal to the comparator 140. In this case, the lower signal processor 130 includes an odd number of amplifiers for generating the lower analog signal. That is, the lower signal processor 130 may reduce the boundary condition asymmetry error by enabling symmetrical current distribution by amplifying the discrete signal sampling the analog signal with an odd number of amplifiers. For example, the lower signal processor 130 may include one or more amplifier strings including 27 amplifiers, and amplify the discrete signals sampled from the analog signal into 27 amplifiers.

The comparator 140 compares the upper analog signal and the lower analog signal received from the upper signal processor 120 and the lower signal processor 130 with a predetermined reference voltage to obtain a comparison signal corresponding to the upper analog signal or the lower analog signal. Include one or more comparators to output. At this time, the comparison unit 140 generates a comparison signal according to a reference voltage for dividing the lower analog signal into a level equal to a natural number rather than 2 ⁿ (n is an integer of 0 or more).

FIG. 2A is a diagram illustrating a level value over time of a higher analog signal input to a comparator of an analog-digital converter, and FIG. 2B is a diagram illustrating a level value over time of a lower analog signal of an analog-digital converter. to be. The horizontally parallel lines illustrated in FIGS. 2A and 2B mean voltage levels of reference voltages input to the comparators included in the comparator 140.

Referring to FIG. 2A, the comparator 140 receives an upper analog signal and measures the level value of the upper analog signal at the present time into 8 levels based on a predetermined voltage level value. That is, the comparator 140 includes seven comparators for measuring the voltage level of the upper analog signal. In this case, each reference voltage may be applied to each comparator, and a voltage level difference (hereinafter, referred to as a reference voltage interval) between the reference voltages adjacent to each other may be constant. In addition, the difference between the minimum value of each reference voltage voltage level and the minimum voltage level that can be converted into a higher analog signal is equal to the reference voltage interval. In addition, the difference between the maximum voltage level that can be converted into the upper analog signal and the maximum value among the voltage levels of the reference voltage may be smaller than the reference voltage interval. As illustrated in FIG. 2A, when the voltage levels of the upper analog signals are measured by seven comparators, the difference between the maximum voltage level that can be converted to the upper analog signal and the maximum value among the reference voltage levels is 6 of the reference voltage interval. It can be a minute.

 At this time, the comparator 140 may designate sections corresponding to levels 1 to 7 equally, and specify sections corresponding to 8 levels narrower than sections corresponding to levels 1 to 7. That is, the section corresponding to the eighth level in FIG. 2A may be set in the range of 25% of the section of the first to seventh levels.

Referring to FIG. 2B, the comparator 140 measures the level value of the lower analog signal to be divided into levels of 26 sections. At this time, the lower signal processor 130 generates a lower analog signal in which a signal corresponding to one section of the upper analog signal is normalized to the entire section as shown in FIG. 2B. Therefore, the lower analog signal is a signal generated to measure the detailed voltage level of the signal corresponding to one section of the upper analog signal.

The comparison unit 140 generates a comparison signal by measuring the voltage levels of the upper analog signal and the upper analog signal as described above, and transmits the comparison signal to the encoding unit 150.

Referring back to FIG. 1, the encoding unit 150 outputs a data signal including a predetermined bit according to the comparison signal. Hereinafter, the encoding unit 150 will be described in detail the structure and operation process.

3 is a diagram illustrating an encoding unit of an analog-digital converter.

Referring to FIG. 3, the encoder 150 of the analog-to-digital converter includes a binary converter 210 and an adder 220.

The binary converter 210 receives a comparison signal of an upper analog signal and a comparison signal of a lower analog signal to generate a binary digital signal for each. The binary converter 210 may include an exclusive OR gate and a ROM. For example, when the comparator 140 generates a comparison signal according to a higher analog signal using seven comparators, the binary converter 210 may convert the seven corresponding comparison signals into binary digital signals (3 bits). Hereinafter referred to as an upper digital signal).

In addition, the comparison unit 140 may generate a binary digital signal according to the comparison signal of the lower analog signal. For example, when the comparator 140 generates a comparison signal of a lower analog signal using 35 comparators, the binary converter 210 may convert a 35 corresponding comparison signals into binary digital signals including 6 bits ( A lower digital signal).

The adder 220 adds a binary digital signal received from the binary converter 210 to generate and output an output signal. The adder 220 includes one or more adders and latches 230. For example, (hereinafter, each bit is referred to as a first bit to an nth bit in the order of the least significant bit to the most significant bit of the binary digital signal), the adder 220 may add to the first bit and the second bit of the lower digital signal. And a latch 230 for receiving a signal from each adder and generating an output signal. In this case, the adder 220 may include the first adder 310 to the sixth adder 360. The first adder 310 may be a full adder that adds the third bit of the lower digital signal and the first bit of the upper digital signal. The second adder 320 may be a full adder that adds a fourth bit of the lower digital signal, a second bit of the upper digital signal, and a carry output from the second adder 320. The third adder 330 may be a full adder that adds a fifth bit of the lower digital signal, a third bit of the upper digital signal, and a carry output from the second adder 320. The fourth adder 340 may be a full adder that adds a sixth bit of the lower digital signal, a first bit of the upper digital signal, and a carry output from the third adder 330. The fifth adder 350 may be a half adder that adds a second bit of the upper digital signal and a carry output from the fourth adder 340. Also, the sixth adder 360 may be a half adder that adds a third bit of the upper digital signal and a carry output from the fifth adder 350.

So far I looked at the center of the embodiment for the present invention. Many embodiments other than the above-described embodiments are within the claims of the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The disclosed embodiments should, therefore, be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

Claims (5)

An upper signal processor configured to generate an upper analog signal by amplifying the analog signal at a predetermined amplification ratio;
A lower signal processor configured to amplify the analog signal through an amplifier string including an odd number of amplifiers and to fold the analog signal to generate a lower analog signal;
A comparator configured to compare the upper analog signal and the lower analog signal according to a predetermined reference voltage to generate a comparison signal; And
An analog unit which generates an upper digital signal according to the upper analog signal and a lower digital signal according to the lower analog signal according to the comparison signal, and adds the upper digital signal and the lower digital signal to generate an output signal -Digital converter.
The method according to claim 1,
The encoding unit may include one or more half-adders for receiving a carry from one of the bits of the upper digital signal and another adder, and one of the bits of the upper digital signal and one of the bits of the lower digital signal and the other adder. Analog-to-digital conversion device comprising a full adder for receiving a carry The method of claim 2,
The encoding unit
A first adder for adding the third bit of the lower digital signal and the first bit of the upper digital signal;
A second adder for adding a fourth bit of the lower digital signal, a second bit of the upper digital signal, and a carry output from the second adder 320;
A third adder for adding a carry output from the fifth bit of the lower digital signal, the third bit of the upper digital signal, and the second adder;
A fourth adder for adding a carry output from the sixth bit of the lower digital signal, the first bit of the upper digital signal, and the third adder;
A fifth adder for adding a carry output from the second bit of the upper digital signal and the fourth adder; And
A sixth adder for adding a carry output from the third bit and the fifth adder of the upper digital signal;
Analog-to-digital conversion device comprising a.
The method according to claim 1,
The comparing unit divides the level value of the upper analog signal into levels of eight sections, and divides the level value of the lower analog signal into levels of 26 sections.
5. The method of claim 4,
The difference between the maximum value of the voltage level of the reference voltage and the maximum voltage level that can be converted into the upper analog signal is smaller than the reference voltage interval.

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