TW442962B - Manufacturing method of non-collapsing capacitor - Google Patents

Abstract

The present invention discloses a manufacturing method of non-collapsing capacitor by forming a concave spacer in the integrated circuit process. The present invention comprises the following steps: at first, providing a semiconductor substrate, forming a semiconductor structure on top of it, and forming an insulating layer covering on the global surface of the semiconductor structure; secondly, depositing a first conductive layer on the insulating layer; then, etching the pattern of the first conductive layer and the insulating layer to define an opening; afterwards, forming a spacer on the inner wall of the opening, and etching the spacer, the insulating layer and the semiconductor layer immediately to form a contact hole and expose the semiconductor substrate; furthermore, depositing a second conductive layer on the first conductive layer, and filling said opening; finally, etching the pattern of the second conductive layer and the first conductive layer to form a lower electrode plate of capacitor.

Description

4429 6 2 V. Description of the invention (1) 5-1 FIELD OF THE INVENTION The present invention relates to a method for manufacturing a sublime thunder-can «,!« Μ ^ ί, Ι-^ manufacturing method of an integrated circuit element, and its characteristics Tongguan: In the process of manufacturing integrated circuit components, II is formed by a recessed gap i, a method of manufacturing a capacitor without a backrest. -2 BACKGROUND OF THE INVENTION The body circuit of the technology has a large trench and a deep trench. Firstly, there is no semiconductor on the coating or hardening, and the super large area is relatively large. Its depth is a mask to form a channel. It is coated on the wafer mask. This resists to soften and etch the wafer. Development has reduced the geometry to continue the trench depth-to-width ratio, which has traditionally been the first to expose a photoresist layer using a wafer using ultraviolet light. Many semiconductors that are protected by photoresistive shrinkage, which in this case refers to the use of a wide groove pattern light that contains a channel resistance, a pair of channels that contains light > depending on the precise area of the final device, which removes the light area. Sensitive trench pattern is removed by positive photoresist softening. With the small size of the lithographic material, the lithographic resistance or negative light part of the case, the photoresist step usually uses the last name engraving process to form a trench, the conductor structure to the area where the circuit is connected. Under the m, the j is connected to a half via hole, and the circuit connection area is usually: the belonging channel is the moving area Uctiv ... a, AA). However, the electrical contact area is generally a small contact point that is one of the seven

4429 62 V. Description of the invention (2) The formation of a node contact is generally a polycrystalline / amorphous dream gap wall process that lacks advanced lithography imaging technology. For example, the interlayer dielectric of the first silicon layer has a polycrystalline ra ti 〇) electrical contact contact area is small, easy to visualize, and even the memory access of the motor under the container will be shown in a picture, in a dielectric layer (IPDl) ll layer (IPD2) 13 ^ and then point the window 1 4 and the electrode plate 16 of the broken / amorphous broken gap container 16 window 14 and the aspect ratio will produce the aspect ratio as shown in the figure In the memory system process of the collapse of the electrode plate 16b, a large number of semiconductors will be produced, and one of them will be formed on the contact wall 15 to form a lower substrate 10 which is caused by the occurrence of electrical deterioration under the capacitor container. There is a first complex line 12 and a bit line above the bit line and the bit contact window 14 and a height-to-aspect ratio contact contact window 1 4 The electrode plate 16 of the lower electrode plate 16 has the condition of peeling the lower electrode plate of the container, Therefore, it is formed on both sides of the shape end of the second polycrystalline silicon element line in the state random access memory. Because of the contact surface separation and collapse 1 6 a toward the entire dynamics of the electrical body, the memory cell is missing 5_3 Object and Summary of the Invention: In the background of the moon, the traditional high-aspect-ratio capacitor is powered off; and: There are many disadvantages caused by the connection between the two. The present invention provides a method for manufacturing a capacitor with no collapse in the integrated circuit component manufacturing process. The contact area between them prevents the capacitor from collapsing.

Page 5 442962

Five 'invention description (3)

Another object of the present invention is to provide a method for manufacturing a capacitor without collapse, which will not change the aspect ratio of the capacitor, and will not affect the storage space of the capacitor = the size of the charging space in the capacitor; It is used to enlarge the contact area between the lower electrode plate of the capacitor and the point contact window. The enlargement of the contact area is to expand the contact window of the contact contact window by using the available space of the interlayer dielectric layer. Therefore, the size of the semiconductor element manufactured by the present invention is not affected, and it will not increase. Big. Therefore—According to the above-mentioned object, the present invention provides a method for manufacturing a non-collapsed electric current state by using the shape of a recessed partition wall in the integrated circuit assembly process. The method includes the following steps: first, a semiconductor substrate is provided, and a semiconductor structure 6 is formed thereon; second,

W covers the entire surface of the semiconductor structure and deposits a first conductive insulating layer. Then, the pattern touches the first conductive layer and the insulating layer to define an opening. Furthermore, a gap wall is formed on the inner side wall of the opening, and then the spacer, the insulating layer and the semiconductor structure are etched, thereby forming a contact window and exposing the semiconductor substrate. This contact window provides a larger contact window, that is, a larger contact area is provided to prevent the capacitor from collapsing. After that, a second conductive layer is deposited on the first conductive layer and fills the opening. Finally, the second conductive layer and the first conductive layer are pattern-etched to form a capacitor lower electrode plate.

Page 6 442962 V. Description of the invention ¢ 4) 5-4 schematic illustration: The first one shows that the traditional method of producing polycrystalline silicon / amorphous silicon spacers produces peeling and collapse of the electrode plate under the high aspect ratio capacitor. Sectional views; and FIGS. 2A to 2G are cross-sectional views illustrating main steps of a process according to an embodiment of the present invention. Main symbols: 1 0 semiconductor substrate 1 1 polycrystalline silicon interlayer dielectric (IPD) 12 bit line 13 polycrystalline silicon interlayer dielectric (IPD) 1 4 contact window 15 polycrystalline silicon / amorphous silicon gap Wall 16a, 16b Capacitor lower electrode plate 200 Semiconductor substrate 2 0 1 bit line 2 0 2 polycrystalline silicon interlayer dielectric layer (I PD 1) 203 polycrystalline silicon interlayer dielectric layer (IPD2) 2 04 polycrystalline silicon / amorphous silicon Layer 2 0 5 Opening 2 0 6 Insulation layer (silicon dioxide layer)

^ 42962 V. Description of the invention (5) " — 1 " ----- 207 recessed partition wall 2 () 8 contact contact window 2 〇9 Rong Yue ... Xixi Silicon / Amorphous Silicon Layer 21 〇 Photoresist curtain cover 211 Capacitor lower electrode plate 5-5 Detailed description of the invention: It is easy to make the above and other objects, features, and advantages of the present invention clearer. "" "A preferred embodiment is given below and cooperated with The attached drawings (the second A picture to the flute, and the first b circle) are described in detail below. These drawings show only the key steps in the process steps 'as shown in the second A picture', a semiconductor substrate 2 is provided. 〇, and a semiconductor structure is formed thereon. This semiconductor substrate is particularly preferably silicon-containing, and contains at least one atom having a roll of less than about 1 · 0E1 per cubic centimeter. The above-mentioned semiconductor structure includes at least one transistor structure (not shown) (In the figure), a bit line 201 and a polycrystalline silicon interlayer dielectric layer 02. As for how to form a transistor structure, the bit line and the polycrystalline silicon interlayer dielectric layer can be formed by conventional semiconductor processes It is understood in the steps, and the details are not described in the present invention. Part. Therefore, only the characteristics of the present invention will be described in detail. First, 'form a blanket-type polycrystalline silicon interlayer dielectric layer 203 to cover the entire exposed surface of the semiconductor structure. The polycrystalline silicon interlayer dielectric layer 2 3 to

4429 6 2 V. Description of the invention (6) Deposited by low pressure chemical vapor deposition (LPCVD) technology, which includes a silicon dioxide layer (SiO2) using ethyl orthosilicate (TEOS) as a source gas, or Silicon nitride layer (S i3 N4). The polycrystalline silicon interlayer dielectric layer 203 can also be deposited by atmospheric pressure chemical vapor deposition (APCVD) technology, which includes a scale; a glass layer (PSG) or a borosilicate glass layer (BPSG). After the polycrystalline silicon interlayer dielectric layer 203 is formed, a first silicon layer 204 is then deposited on the polycrystalline silicon interlayer dielectric layer 203. The first silicon layer 204 is an amorphous layer deposited by using low pressure chemical vapor deposition (LPCVD) technology using si lane as a source gas at a temperature of less than approximately 575 degrees Celsius; or It is a polycrystalline silicon layer deposited at a temperature between about 575 and 650 degrees Celsius. Thereafter, as shown in FIG. 2B, using the conventional lithography imaging technology, the first silicon layer 204 and the polycrystalline silicon interlayer dielectric layer 203 are pattern-etched to define an opening 205. This opening is the preset position of the contact window between the lower electrode plate of the capacitor and the interface of the capacitor. The depth of the opening 205 is approximately half the thickness of the polycrystalline interlayer dielectric layer 203 on the bit line 201. The dielectric layer between the patterned first silicon layer and the polycrystalline silicon layer includes at least a mixed solution of nitric acid and hydrofluoric acid. The principle is to use oxidic acid to oxidize the surface of the stone to the dioxide, and then use hydrofluoric acid to remove the resulting silicon dioxide layer. "Nevertheless, other conventional etchant or etching methods can also be used use. Immediately afterwards, as shown in FIG. 2C, a uniform covering insulating layer 206 is deposited on the first silicon layer 204 and the opening 205. This insulating layer is used for

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It is a silicon dioxide (Si02) layer or a silicon nitride (s-team) layer for the spacer. Thereafter, the wafer with the insulating layer 206 (e.g., the Si 02 layer) is fed into a dry etching machine ', and the spacer is etched by anisotropic etching (anisotropic etching). The purpose of this step is to use the anisotropy specific to dry etching to remove most of the SiO2 layer deposited on the wafer based on its deposited thickness. Because the thickness of the SiO2 layer on the inner side wall of the opening 205 is higher than that of other parts, after the anisotropic dry etching, the 'partially attached si on the inner side wall of the opening 205 The 02 layer will not be completely removed, but forms a recessed partition wall 207 as shown in the second D diagram. As a result, as shown in the second E diagram, at least a reactive ion etching (RIE) technology using c η f3 as an etchant is used to selectively etch the interstitial spacer and the polycrystalline silicon interlayer dielectric layer 203. And the polycrystalline silicon interlayer dielectric layer 202 = to form a contact window 208 with a wide upper width and a narrow lower width under the opening 205, and expose the semiconductor substrate 200. The cross-sectional view of the contact window of the upper wide lower narrow contact mentioned above has the shape of " Y ". Taking the plasma of CHF3 as an example, the etching selectivity of Si 02 and Si is about 10 or more. Secondly, in the second F-picture, a second silicon layer 209 is deposited on the first stone layer 204 and fills the contact window and the opening. Like the first silicon layer, the second silicon layer 20 9 is also formed by using low pressure chemical vapor deposition (LPCVD) technology using silicon methane (si 1 an e) as a source gas at a temperature of less than about 575 degrees Celsius. An amorphous stone layer, or a polycrystalline silicon layer deposited at a temperature between about 575 and 650 degrees Celsius. Also formed in the second f circle

Page 10 0 442962 V. Description of the invention (8) There is a photoresist mask 210 on the second silicon layer 209, which is used to define the formation position of the electrode plate under the capacitor. Finally, as shown in the second figure G, a photoresist mask is used as an etching mask and a dry etching method including gas atoms is used to etch the second silicon layer and the first silicon layer to form a capacitor lower electrode plate 211 on Where the opening is in contact with the contact. The end of the embodiment of the present invention is the use of sulfuric acid (

HzS04) solution after removing the photoresist mask. According to the embodiment of the present invention, by forming the recessed gap wall, the contact area between the lower electrode plate of the capacitor and the contact contact window is enlarged, thereby preventing the collapse of the valley Is. It will not change the two width ratios of the capacitor β, nor will it affect the size of the charging space stored in the capacitor. The enlargement of the contact area is to expand the contact window of the contact contact window by using the available space of the polycrystalline silicon interlayer dielectric layer. Therefore, the size of the semiconductor device manufactured by the present invention will not be affected by this, let alone Increase. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application. *

Claims (1)

442962 VI. Application for patent scope 1. A method for manufacturing a capacitor, the method includes at least the following steps: providing a semiconductor substrate and forming a semiconductor structure thereon; forming an insulating layer covering the entire surface of the semiconductor structure; The first conductive layer is on the insulating layer; the first conductive layer and the insulating layer are etched to define—the opening 9 forms a gap wall on the inner side wall of the opening; and the gap wall, the An insulating layer and the semiconductor structure, thereby forming a contact window and exposing the semiconductor substrate; depositing a second conductive layer on the first conductive layer and filling the contact window and the opening; and pattern etching the second The conductive layer and the first conductive layer form a capacitor lower electrode. 2 _ The method according to item 1 of the scope of patent application, wherein the above-mentioned semiconducting Zhao structure includes at least a transistor structure, a bit line, and a polycrystalline interlayer dielectric layer. The method according to item 1 of the scope of patent application, wherein the above-mentioned semiconductor includes at least-Han degrees less than about 15 uE per cubic centimeter substrate. 4. If the polycrystalline silicon interlayer dielectric layer of item 1 of the scope of patent application, At least TEOS is used as a method, wherein the above-mentioned insulating layer is a layer containing silicon oxide (Si02 ~), and the source gas is deposited in a low-pressure chemical vapor phase. 442962 6. Deposited by patent application area (LPCVD) technology. 5. The method according to item 1 of the patent application, wherein the above-mentioned insulating layer is a polycrystalline silicon interlayer dielectric layer, which includes at least a silicon nitride layer (S i3 n4), and uses low pressure chemical vapor deposition (LPCVD). ) Technology deposited. 6. The method according to item 1 of the patent application range, wherein the above-mentioned insulating layer is a polycrystalline silicon interlayer dielectric layer, which includes at least one phosphorus-silicon-glass-glass layer (pSG), and uses atmospheric pressure chemical vapor deposition ( APCVD) technology. 7. The method of item 1 in the scope of claim 1 wherein the above-mentioned insulating layer is a polycrystalline silicon interlayer dielectric layer, which includes at least a borophosphosilicate glass layer (BpSG), and uses atmospheric pressure chemical vapor deposition. (APCVD) technology. 8. The method according to item 1 of the patent application range, wherein the first conductive layer includes at least an amorphous silicon layer, which uses silicon methane (si 1 ane) as a source gas, and is used for low pressure chemical vapor deposition (LPCVD). Technology, deposited at a temperature of less than 5 ... 5 ° C. 9. The method according to item 1 of the patent application, wherein the first conductive layer includes at least a polycrystalline silicon layer, which uses si 1 ane as a source gas and uses a low pressure chemical vapor deposition (LPCVD) technology. , Deposited at a temperature between about 575 to 650 degrees Celsius. Page 13 442962 VI. Application scope of patent 10. The method according to item 丨 of the scope of patent application, wherein the above-mentioned second conductive layer includes at least an amorphous silicon layer, which uses silicon methane (si 1 ane) as a source gas 'It is formed by low pressure chemical vapor deposition (LPCVD) technology at a temperature of less than about 575 degrees Celsius. 11_ The method according to item 1 of the patent application range, wherein the second conductive layer includes at least a polycrystalline silicon layer, which uses silicon fane as a source gas, and uses low pressure chemical vapor deposition (LPCVD) technology. , Deposited at a temperature between about 575 and 650 degrees Celsius. 1 2. The method according to item 1 of the patent application, wherein the pattern etching of the first conductive layer and the insulating layer includes at least a mixed solution of nitric acid and hydro fluoric acid. 1 3 · The method according to item 1 of the scope of patent application, wherein the above-mentioned spacer comprises at least silicon dioxide (Si02). 14. The method according to item 1 of the scope of patent application, wherein the above-mentioned etching of the spacer, the insulating layer and the semiconductor structure includes at least a reactive ion etching (RIE) technique using CHF3 as an etchant. 15. The method according to item 1 of the scope of patent application, wherein in the above pattern, the second conductive layer and the first conductive layer are at least dry-etched with a gas atom. Page 4429 62 Six 'patent applications include at least the following steps: a semiconductor structure; a semiconductor structure as a whole 16. A method of manufacturing a capacitor, the method provides a semiconductor substrate, and a polycrystalline silicon interlayer dielectric is formed thereon A layer covers the surface; a first stone layer is deposited on the polycrystalline stone interlayer dielectric pattern engraved with the first stone layer and the polycrystalline stone layer M * on 'η gold. To define the middle; the uniform layer covering layer is engraved on the edge layer and the opening, so that the inner side wall of the opening is engraved; The semiconductor structure is formed and the semiconductor substrate is exposed; a second silicon layer is deposited on the first opening; the gap wall, the passivation layer is a silicon-on-silicon interlayer dielectric layer and the current contact window is on the opening On a Shi Xi layer 'and fill the contact window and form a photoresist curtain cover on the second silicon layer; the second Shi Xi layer and the first-Shi Xi layer are engraved by the photo resist curtain. To form a capacitor lower electrode at the opening The windows of the contact; curtain and removing the photoresist mask. 17. The method according to item 16 of the scope of patent application, wherein the above-mentioned semiconductor structure includes at least a transistor structure, a bit line, and a polycrystalline silicon interlayer. Page 15 4429 62 VI. Scope of Patent Application 1-Electrical layer. 18. The method of claim 16 in the scope of patent application, wherein the above-mentioned semiconductor substrate contains at least a concentration of less than about 5 atoms per cubic centimeter. 19. The method according to item 16 of the patent application, wherein the above-mentioned intercrystalline silicon interlayer dielectric layer includes at least a silicon oxide layer (SiO2), which uses orthosilicate (TEOS) as a source gas, and Deposited by low pressure chemical vapor deposition (LpcvD) technology. 20. The method according to item 16 of the scope of patent application, wherein the above-mentioned polycrystalline interlayer dielectric layer includes at least one nitride layer (Sn4), which is deposited using a low pressure chemical vapor deposition (LPCVD) technique. '21. The method according to item 16 of the scope of patent application ', wherein the polycrystalline interlayer dielectric layer described above includes at least one phosphosilicate glass layer (pSG), which is deposited using atmospheric pressure chemical vapor deposition (APCVD) technology and to make. 22. The method according to item 16 of the patent application range, wherein the polycrystalline interlayer dielectric layer described above comprises at least one borophosphosilicate glass layer (BPSG), which is deposited using Changli Chemical Vapor Deposition (APCVD) technology and to make" Page 16 4429 62 6. Scope of patent application The body is deposited by low pressure chemical vapor deposition (LPCVD) technology at a temperature of less than about 575 ° C. 2 4. The method according to item 16 of the scope of patent application, wherein the first sand layer includes at least a polycrystalline silicon layer, which uses si lane as a source gas and uses low pressure chemical vapor deposition (LPCVD) technology. It is deposited at a temperature between about 575 and 650 degrees Celsius. 25. The method according to item 16 of the scope of patent application, wherein the second stone layer includes at least an amorphous silicon layer, which uses si lane as a source gas and uses low pressure chemical vapor deposition (LPCVD). ) Technology, deposited at a temperature of less than about 575 degrees Celsius. 26. The method according to item 16 of the patent application, wherein the second silicon layer includes at least one polycrystalline silicon layer, which uses siiane as a source gas and uses low pressure chemical vapor deposition (LPCVD) technology. A temperature of about 575 to 650 degrees Celsius. 2 7. The method according to item 16 of the scope of patent application, wherein the pattern etching of the interlayer dielectric layer between the first stone layer and the polycrystalline silicon layer includes at least the use of nitric acid and hydrofluoric acid. 28. The method according to item 16 of the patent application, wherein the above-mentioned uniform coverage Page 17, 4429 6 2 6. Scope of patent application The insulation layer contains at least silicon dioxide (Si 02). 2 9. The method according to item 16 of the scope of patent application, wherein the etching of the uniform covering insulating layer is completed by an anisotropic surname (anis 〇tr 〇picetch) e 3 0, such as the scope of patent application 16. The method according to item 16, wherein the selective etching of the recessed spacer, the polycrystalline silicon interlayer dielectric layer, and the semiconductor structure include at least a reactive ion etching (RiE) technology using CHF3 as an etchant 31. Such as The method of claim 16 in the patent application range, wherein the above-mentioned etching of the second stone layer and the first silicon layer uses at least a dry etching method including a gas atom. 32. If the method according to item 16 of the patent application scope, wherein the removal of the photoresist curtain green at least includes the use of a solution of H2S04.