TW442958B - Method of fabricating a semiconductor memory device - Google Patents

Abstract

Disclosed is an improved method of fabricating a semiconductor memory device wherein passivation layer is advantageously deposited at low temperature less than 200 DEG C as to prevent H2 infiltration, minimize stress during deposition thereof, and prevent reaction between metal contact and capacitor electrode, and thereby preventing degrading of capacitor characteristics. The method includes forming a first insulating layer over a semiconductor substrate having a device isolation layer, forming a capacitor made of a lower electrode, a dielectric film, and an upper electrode over the first insulating layer, forming a second insulating layer over the first insulating layer and on the capacitor, forming first metal contacts to the to the semiconductor substrate and the lower electrode respectively through the second and first insulating layers, and the second insulating layer, forming a third insulating layer over the second insulating layer and on the first metal contacts, forming a second metal contact to the upper electrode through the third and second insulating layers, and forming a passivation layer over the third insulating layer and on the second metal contact at a temperature lower than reaction temperatures between the first metal contact and the lower electrode, and between the second metal contact and the upper electrode.

Description

V. Description of the Invention (I) Field of the Invention The present invention relates to a method for manufacturing a ferroelectric random access memory (FRAM), and in particular, forming a protective layer (Passivation Layer) does not make capacitors Degraded characteristics. Description of the Invention Ordering a modern data processing system requires determining that information can be quickly accessed. This data processing system has a real portion of data stored in its memory, which can be easily and randomly accessed. Because high-speed memory is implemented in semiconductor technology, ferroelectric random access memories (FRAMs) have been developed, and the performance of ferroelectric random access memories is nonvolatile, which can be achieved. Take advantage of facts. That is, a ferroelectric capacitor includes a pair of capacitor plates with a ferroelectric material between them. This ferroelectric material has two different states of stable polarization (Polarization), which can be defined as A hysteresis loop. This hysteresis loop is drawn to map its polarization, corresponding to its applied voltage. The protective layer and package process are unavoidable, and are used in the practical application of the manufacturing process of the ferroelectric random access memory. However, in the protective layer and packaging process, H2 infiltration and stress are significant obstacles to the characteristics of the capacitor and its reliability. FIG. 1 is a schematic cross-sectional view showing a conventional semiconductor memory device. A semiconductor memory device as shown in Fig. 1 is manufactured through the following steps. First, a field oxide layer is formed on a semiconductor substrate 2 (Field 5 (NS > Λ4ϋ (210X297mm) 'a', 4429 5 8 422 2pir.doc / 0〇8 A 7 ______ _ B7 5 2. Description of the invention (b) ..----------------- {1¾Please read the back of the note before writing the philosopher)

Oxide Layer) 4 'This semiconductor substrate 2 defines Active and Inactive Regions. A gate electrode 6 is formed on the active region of the semiconductor substrate 2 '. A first interlayer insulating layer 8 is formed on the semiconductor substrate 2 'including this alarm electrode 6. A capacitor 14 includes a platinum lower electrode (Platinum Lower EIectrode) 10, a ferroelectric film (Ferroelectric Film), and a platinum upper electrode (Platinum Upper Electrode) 12 are formed on the first inner insulating layer 8 . In order to protect the unwanted reactants between the ferroelectric film 11 of the capacitor 14 and the surrounding material, a capping layer 9 composed of 1 ^ 02 is formed and coated on the capacitor I4. A second inner-layer insulating layer 16 is formed on the first inner-layer insulating layer 8 and includes a capacitor 14. The first metal contact (Contact) is composed of brocades 18a and 18b, which are formed in the second inner insulating layer 16 and the first inner insulating layer 8, and the capping layer 9b, and are electrically connected to the semiconductor substrate. The active area of the material 2 and the lower electrode 10. A third inner-layer insulating layer 20 is formed on the second inner-layer insulating layer 16 'including first metal contacts ISa and 18b. A second metal contact 22 is composed of aluminum and is formed on the third inner insulating layer 20 and the second inner insulating layer 16 'to the upper electrode 12. A protective layer 24 is formed on the third inner layer insulating layer 20 and includes a second metal contact 22. The protective layer 24 is made of an oxide layer. It uses the Electron Cyclotron Resonance (ECR) technology or plasma enhanced tetraethylene-o-silicate (PE-TE0S) chemical vapor phase. Deposition (CVD) technology. Traditionally, the above-mentioned oxide layer is deposited in a temperature range of 300 to 400 ° C. If the oxidation protective layer is deposited above 200 ° C, the platinum electrode and aluminum gold 6 paper ift scale said Chuanxiong} eight heart brother (210X297 male) A7 B7 Λ4Z958 4222pit'.d〇c / 008 5. Description of the invention ( ^) It is a contact reaction, which causes the degradation of capacitor characteristics. It will be shown in Figures 2A to 2D below. (Please read the note f of the back first, and then click this page) Figures 2A to 2D are photographs of a scanning electron microscope (SEM) showing the temperature at the annealing temperature (protective layer deposition) The relationship between temperature) and the reaction of aluminum to the platinum electrode. As shown in Figure 2A, the reaction products will not be generated (no reaction occurs between platinum and aluminum) if tempering is not performed. Referring to Fig. 2B ', if the tempering temperature (protective layer deposition temperature) is about 200 ° C, a platinum-aluminum reaction product layer is generated. The platinum-aluminum reaction product increases as the tempering temperature increases, as shown in Figure 2C (tempering temperature is about 300 ° C) and Figure 2D (tempering temperature is about 400 ° C). To solve the above problem, a diffusion barrier layer (such as a titanium nitride (TiN) layer) is formed at the interface between the capacitor electrode and the metal contact. As a result, H2 penetration and stress are generated in front of the diffusion barrier layer. Due to the high deposition temperature of the protective layer, the sensed charge is reduced significantly. Figure 3 shows the hysteresis loop of a ferroelectric material without a capacitor (25 ° C) and the hysteresis loop of a capacitor covered with a protective layer (relatively deposited at 200 ° C, 300 ° C and 40 (TC). As shown in Figure 3, the induced charge gradually decreases, and as the tempering temperature increases, from 200 ° C, 300 ° C '400 ° C when compared with room temperature 25 ° C (before tempering).

if t 灼 1 in 1V From Figures 2 and 3 above, it can be concluded that a lower deposition temperature is needed to avoid degradation of the ferroelectric characteristics. Comprehensive description Since the present invention has been created as described above, the purpose of the present invention is to improve the paper recognition of the inner city of the city of Shichuan (榡, NS) A4 (2 丨 0X297 mm)

I 4222pif'.d〇c / 0〇8 4 429 5 8 A7 B7 Five η 't Jth ii .1 in fc A i'l Print invention description ((/) Provide a manufacturing method for ferroelectric capacitors, without using Degradation of the characteristics of the ferroelectric film 'deposits a protective layer at low temperature. The main feature of the present invention is to deposit a protective layer at a low temperature below 20 CTC. The protective layer is selected from at least one P-sandyl PECVD oxide layer, PE -TEOS oxide layer, PSG layer, BPSG layer and USG layer. Due to these low temperature protective layers, the reaction between the capacitor electrode and the metal wire can be avoided, and h2 penetration and stress can be minimized. The above and other objects can be understood in accordance with the present invention to form a first insulating layer on a semiconductor substrate having an element isolation layer thereon: forming a capacitor, the capacitor being formed by a lower electrode ' A dielectric film and an upper electrode are formed on the first insulating layer; a second insulating layer is formed on the first insulating layer and the capacitor: a first metal contact is formed from the second insulating layer to the first insulating layer Layers, and from the Forming a second insulating layer to the lower electrode; forming a third insulating layer on the second insulating layer in contact with the first metal; forming a second metal contact from the third insulating layer to the upper electrode; and forming a protection Layer, on the third insulation and second metal contact, at a temperature lower than the reaction temperature between the first metal contact and the lower electrode, and the reaction temperature between the second metal contact and the upper electrode. The above and other objects, features, and advantages of the invention can be more clearly understood, and a preferred embodiment is given below in conjunction with the accompanying drawings to explain in detail as follows: Brief description of the drawings: Figure 1 is a drawing A schematic cross-sectional view of a conventional semiconductor memory element

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/ 1 :, 4 42 9 5 8 4222pil'.doc / 00S A7 B7 Description of the invention (t) Figures; Figures 2A to 2D are photographs of a scanning electron microscope showing the tempering temperature (protective layer deposition temperature) and Relationship between the reaction of aluminum to a platinum electrode; Figure 3 shows the hysteresis loop of a ferroelectric material without a capacitor (25 ° C) and a protective layer (relatively deposited at 200 ° C, 300 ° C and 400 ° C) The hysteresis loop of the covered capacitor; Figures 4A to 4D are schematic cross-sectional views showing the flow of a method for manufacturing a semiconductor memory device according to the present invention; and Figure 5 is a SEM after depositing a protective layer according to the present invention Photographs; and Figure 6 is a graph showing the relationship between the induced charge and the temperature of the protective layer deposition (Xu first read the note f and then write this page),? Τ state, ι · 4 '. A 心 η ; η 合 ίΐ η Printed mark description of the pattern: 2: semiconductor substrate 4: field oxide layer gate electrode first inner insulating layer 9 = capping layer 10: lower electrode 11: ferroelectric film 12: upper Electrode 14: Capacitor I6: Second Insulation Layer, Paper, Paper Size, In this Example, You Zuo You Jin (&lt;, NS &gt; Λ4 gauge you (2 丨 0 X297 公 漦} Γ 4429 5 8 4222pif.doc / 008 Λ Β7__ V. Description of the invention 18a, 18b: first metal contact 20: third inner insulating layer 2 ?: second metal contact 24: protective layer 100 : Semiconductor substrate 102: element isolation layer 104: smell electrode structure 106: first inner insulating layer 107a, 107b: capping layer 108: lower electrode 109: ferroelectric film 110: upper electrode 112: ferroelectric capacitor 114: Second inner insulating layers 116a, 116b: first metal contact 118: third inner insulating layer 120: second metal contact 122: protective layer embodiment The preferred embodiment of the present invention will be explained, please refer to the drawings. The invention relates to a method for manufacturing a semiconductor memory element, and particularly to a method for forming a ferroelectric capacitor with a low-temperature protective layer. A field oxide layer and a field effect transistor structure are formed. The current process is actually short for the manufacture of DRAM cells. This paper is only a 10-sheet ifc-scale threshold. <TNsTa4> (2 丨 0X297 mm) ^ (-Read the precautions before filling this page)-4429 5 8 4222pi f.doc / 008 A7 _______B7 _____ V. Description of the invention (9) is explained in order to understand the present invention. Please refer to FIG. 4A, a device isolation layer (Device Isolati ON layer); 102 is formed on a semiconductor substrate 100 Specific areas to define active and inactive areas. A field effect transistor is formed on an active region of a semiconductor substrate 100. As is known in the art, this field-effect transistor includes a gate oxide layer (not labeled), and a gate electrode structure 104 is protected by a silicon nitride hard mask (not shown). (Labeled) and silicon nitride sidewall spacers (spacers) (not labeled) and-the source / drain region (source / drain region) (not marked) are aligned with the sidewall spacers. A first inner insulating layer 106 is formed on the semiconductor substrate 100 and includes a transistor. • 1T Please refer to FIG. 4B. A ferroelectric capacitor 112 is composed of a lower electrode 108, a ferroelectric film 109, and an upper electrode 110. The ferroelectric capacitor 112 is formed on the first inner insulating layer 106. The lower electrode and the upper electrode are made of platinum and relatively have a thickness of about 2300 ~ 2000A. The ferroelectric film 109 is made of PZT (Lead Zinconate Titanate) or PLZT (Lead Lanthanum Zinconate Titanate), and in this embodiment, PZT has a thickness of about 2500 Å. A capping layer 107a such as titanium dioxide (Ti02) is formed to cover the ferroelectric capacitor gas 112. The capping layer 107a serves as a reaction protection between the ferroelectric film 109 and a subsequent formation material. Another capping layer 107b may be formed at the interface between the first inner insulating layer 106 and the lower electrode 108. Referring to FIG. 4B, a second inner-layer insulating layer 114 is formed. On the first inner-layer insulating layer 106, a capacitor 112 is included. First contact hole (First-/!! | 11 i paper scale (rNS) (2 丨 0X297 mm)

Decay .. ,, '', &quot;.; Doudou Du T.i / ifr combined Μ 衩 印 V U29 5 8 4222pit'd〇c / 008 A 7 B7 V. Description of the invention (?)

Contact hole) is opened, in the second inner insulating layer 114 and the first inner insulating layer 106, and in the second inner insulating layer 114 and the capping layer 107b to expose the ttji source / drain region and the lower electrode *relatively. A first metal such as aluminum is deposited on the contact holes and on the second inner insulating layer 114, and is defined to form the first metal contacts 116a and 116b. Referring to FIG. 4C, a third inner-layer insulating layer Π8 is formed, and the second inner-layer insulating layer 114 includes first metal contacts 116a and 116b. A second contact hole is opened in the third inner insulating layer 118 and the capping layer 107b to the upper electrode 110. A second metal such as aluminum is deposited on the second contact hole and on the third inner insulating layer 118, and is defined to form the second metal contact 120. The brocade is deposited using a sputtering technique. The next process is an important process of the present invention. A protective layer 122 is deposited on the third inner insulating layer 118 and includes a second metal contact 120, as shown in FIG. 4D. The protective layer 122 is deposited at a low temperature of less than 250 ° C, where the capacitor electrode material (platinum) does not react with the metal material (aluminum). The preferred deposition temperature is below 200 ° C. For this low temperature protective layer 112, at least one P · silyl PECVD oxide layer, PE-TEOS oxide layer, PSG layer, BPSG layer and USG layer may be selected. Fig. 5 is a SEM photograph after depositing a protective layer according to the present invention, wherein the protective layer is made of PE-TEOS oxide layer, at a temperature lower than 200 ° C, and Fig. 6 shows induced charges and the protective layer The relationship between the deposition temperature and the applied voltage is 3V. As shown in Figure 5, no reaction products are produced between the electrode and metal contact at such a low deposition temperature. Refer to Figure 6, (11 · Read the precautions before writing this page) Binding Paper Music Scale Po Chuan Min Min U10X297 mm &gt; Five A7 B7 4429 5 8 4222pil'.dt &c; c / 〇〇 8 Description of the invention (f) The induced charge (// m / cm2) of a capacitor without a cover (before the protective layer is deposited) is about 9 // m / cm2. The traditional ECR oxide layer's induced charge (which is deposited above 200 | ° C) is approximately 1 // m / cm2. On the other hand, the induced charge of the P-silyl oxide layer (deposition temperature is about 190 ° C) and the PE-TEOS oxide layer (deposition temperature is about 200 ° C) according to the present invention is 9 / zm / cm2 and the protection is The same as before the layer was deposited. Here a diffusion layer such as TiN is formed, in the case of an ECR oxide layer 'but not in the case of a PE-TEOS oxide layer and a P-silyl oxide layer. It can be inferred from Fig. 6 that the present invention provides a ferroelectric capacitor 'which has an excellent ferroelectric characteristic, although a protective layer is deposited there so that the protective layer deposition temperature is lower than 200X :. Finally, the low temperature (preferably below 200 ° C) is lower than the deposition temperature of the protective layer ', which can eliminate the damage caused during deposition (stress and H2 penetration to minimize ferroelectric characteristics). Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in the art is entitled to make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. Read the back note 4 ^, then continue to write this page) * 1Τ

I Ιί I ft. 13 paper sizes Chengchuan '丨, SjdiTt'NS) (210X297 mm

Claims (1)

The Central Government Bureau of the Ministry of Economic Affairs, the Consumer Cooperative Cooperative, 4429 5 8 Ag B8 4222pii'.doc / 008 6. Application for a patent 1. A method for manufacturing a semiconductor memory device, including the following steps: forming a first insulating layer On a semiconductor substrate, the semiconductor substrate has an element isolation layer; forming a capacitor, the capacitor is composed of a lower electrode, a dielectric film and an upper electrode, on the first insulating layer; forming a first Two insulating layers on the first insulating layer and the capacitor; forming a first metal contact from the second insulating layer to the first insulating layer, and from the second insulating layer opposite to the semiconductor substrate To the lower electrode; forming a third insulating layer and contacting the first metal on the second insulating layer: forming a second metal contact from the third insulating layer and the second insulating layer to the upper electrode And forming a protective layer, on the third insulating layer and the second metal contact, at a temperature lower than the reaction temperature between the first metal contact and the lower electrode, and on the second metal The reaction temperature and the contact between the upper electrode ° 2. The method of manufacturing a semiconductor memory device of the application of paragraph 1 patentable scope, wherein the step of forming the protective layer is performed at a temperature below about 250 ° C. 3. The method for manufacturing a semiconductor memory device according to item 1 of the scope of patent application, wherein the protective layer is composed of a P-silyl oxide layer, a PE-TEOS oxide layer, a PSG layer, a BPSG layer, and a USG layer. At least one compound selected from the group. The size of this paper is in Chinese National Standard (CNS) A4 * L &lt; 210X2 »7mm) (Please read the precautions on the back before filling this page) 'IT