JP2000091516A - Semiconductor device - Google Patents

Semiconductor device

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JP2000091516A
JP2000091516A JP18167899A JP18167899A JP2000091516A JP 2000091516 A JP2000091516 A JP 2000091516A JP 18167899 A JP18167899 A JP 18167899A JP 18167899 A JP18167899 A JP 18167899A JP 2000091516 A JP2000091516 A JP 2000091516A
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film
dielectric
semiconductor
gate
oxide
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JP3449298B2 (en )
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Akira Fujisawa
Kazuhiro Takenaka
計廣 竹中
晃 藤沢
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Seiko Epson Corp
セイコーエプソン株式会社
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Abstract

PROBLEM TO BE SOLVED: To improve residual dielectric polarization and a dielectric constant by forming a capacitor on a local oxide film in a semiconductor device. SOLUTION: A gate insulating film 2 and a local oxide film (LOCOS) 6, which are to partition and form a MOS active region, are formed on the surface of a p-type semiconductor substrate 1. A transfer transistor T is composed of a polycrystalline silicon-gate 3, formed through the gate insulating film 2 and source drain regions 4, 5 as high-concentration n-type regions formed on the surface side of the p-type semiconductor substrate 1 through self-alignment, while using the polycrystalline silicon-gate 3 as a mask. A storage capacitor C is constituted of the LOCOS 6 as a field oxide film. Accordingly, characteristic deterioration such as residual dielectric polarization of a ferroelectric, lowering of a dielectric constant, etc., can by avoided.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、半導体装置及びその製造方法に関し、特に、PZT(Pb(Ti x Zr y The present invention relates to relates to a semiconductor device and a manufacturing method thereof, in particular, PZT (Pb (Ti x Zr y)
3 )などの強誘電体膜を用いたキャパシタ構造を有する半導体メモリや多結晶シリコン・ゲートを用いたCM O 3) CM using a semiconductor memory or a polysilicon gate having a capacitor structure using a ferroelectric film, such as
OS半導体集積回路における保護膜構造及びその成膜法に関するものである。 It relates the protective film structure and film forming method in OS semiconductor integrated circuit.

【0002】 [0002]

【従来の技術】従来、強誘電体を用いたストレージ・キャパシタ構造を有する半導体不揮発性メモリ・セルは、 Conventionally, a semiconductor nonvolatile memory cell having a storage capacitor structure using ferroelectric,
例えば図6に示す構造を備えている。 For example, with the structure shown in FIG. このメモリ・セルは、単一の転送ゲート・トランジスタ(MOSトランジスタ)Tに強誘電体膜を用いたストレージ・キャパシタ(コンデンサ)Cを直列接続したものである。 The memory cell is one in which the storage capacitor (capacitor) C using a ferroelectric film on a single transfer gate transistor (MOS transistor) T connected in series. 転送ゲート・トランジスタTは、p型半導体基板1の上にゲート絶縁膜2を介して形成されて多結晶シリコン・ゲート3 The transfer gate transistor T is, p-type on the semiconductor substrate 1 is formed via a gate insulating film 2 polysilicon gate 3
と、この多結晶シリコン・ゲート3をマスクとしてp型半導体基板1の表面側にセルフアラインで形成された高濃度n型領域たるソース・ドレイン領域4,5とから構成されている。 When, and a polycrystalline silicon gate 3 is formed in self-alignment on the surface side of the p-type semiconductor substrate 1 as a mask the high-concentration n-type region serving as source and drain regions 4 and 5 Prefecture. なお、ソース・ドレイン領域4はビット線に、多結晶シリコン・ゲート3はワード線にそれぞれ接続されている。 The source-drain regions 4 to the bit line, polysilicon gate 3 is connected to the word line. 一方、ストレージ・キャパシタCはフィールド酸化膜たるLOCOS(局所酸化膜)6上に溝成されている。 On the other hand, the storage capacitor C is made grooves on the field oxide film serving as LOCOS (local oxide film) 6. LOCOS6,多結晶シリコン・ゲート3の上には、例えばCVDによりSiO 2又はスパッタ法によるSiNの第1の層間絶縁膜7が形成され、この層間絶縁膜7のうちLOCOS6の真上にスパッタ法で白金(Pt)の下部平板電極8が形成される。 LOCOS6, on the polycrystalline silicon gate 3, for example, the first interlayer insulating film 7 of SiN by SiO 2 or the sputtering method is formed by CVD, by sputtering directly above the LOCOS6 of the interlayer insulating film 7 lower plate electrode 8 of platinum (Pt) is formed. この下部平板電極8上の一部にはスパッタ法又は塗布法により強誘電体たるPZT(Pb(Ti x Zr y )O 3 )の誘電体膜9が形成され、またこの誘電体膜9の上にはスパッタ法で白金の上部平板電極10が形成される。 The dielectric film 9 of the portion of the lower plate electrode 8 serving ferroelectric by a sputtering method, a coating method, or PZT (Pb (Ti x Zr y ) O 3) is formed, also on the dielectric film 9 upper plate electrode 10 of platinum is formed by sputtering on. 次に、第1の層間絶縁膜7の上には例えばCVDによるSiO 2又はスパッタ法によるSiNの第2の層間絶縁膜11が形成され、この層間絶縁膜11の上にスパッタ法によりAl Next, on the first interlayer insulating film 7 is formed a second interlayer insulating film 11 of SiN by SiO 2 or sputtering by CVD for example, Al by a sputtering method on the interlayer insulating film 11
配線が形成される。 Wirings are formed. Al配線12aはソース・ドレイン領域5と上部平板電極10とをコンタクト穴を介して導通させるセル内部配線で、Al配線12bは下部平板電極8と図示しないパッド部とを導通させる接地配線である。 Al wiring 12a is a cell interior wiring for electrically connecting the source and drain regions 5 and the upper plate electrode 10 via the contact hole, Al wiring 12b is an earth wiring for electrically connecting the pad portion (not shown) and the lower plate electrode 8. なお、図6には示されていないが、多結晶シリコン・ゲート3に導通するワード線及びソース・ドレイン領域4に導通するビット線は上記Al配線と同一層に形成されている。 Although not shown in FIG. 6, the bit line electrically connected to the word line and the source-drain regions 4 electrically connected to the polycrystalline silicon gate 3 is formed in the same layer as the Al wiring. Al配線12a,12bの上にはスパッタ法によるSiNのパッシベーション膜13が形成されている。 Al wirings 12a, the passivation film 13 of SiN is formed by sputtering on top of 12b.

【0003】 [0003]

【発明が解決しようとする課題】誘電体膜9に使用される強誘電体たるPZT(Pb(Ti x Zr y )O 3 )は電界に対してヒステリシス曲線を持ち、書き込み電圧を取り除くと、残留分極を保持し続けるため、上述のような不揮発性メモリとして利用されたり、また比誘電率が約1000程度の値でSiO 2膜と比較して2桁以上も大きいので、ダイナミックRAMのキャパシタとしても利用される。 Serving ferroelectric is used in the dielectric film 9 [0005] PZT (Pb (Ti x Zr y ) O 3) has a hysteresis curve to an electric field, when removing the write voltage, the residual to continue holding the polarization, or is used as a nonvolatile memory such as described above, and since the value of the relative dielectric constant of about 1000 SiO 2 film 2 digits or more is also large in comparison with, also as a capacitor of a dynamic RAM It is used.

【0004】しかしながら、水素に晒されると残留分極の値が減少してしまい、記憶機能に必要な2値論理の幅(マージン)が狭くなる。 However, the value of the residual polarization when exposed to hydrogen would decrease, binary logic of width required memory function (margin) is narrowed. また比誘電率の値も低下する。 The relative dielectric constant values ​​is also reduced. このような特性劣化は歩留りの低下を招くので、誘電体膜9の形成工程の後においては水素を誘電体膜9に晒さないような成膜法に顧慮する必要がある。 Since such characteristics degradation lowering the yield, after the step of forming the dielectric film 9 is required to regard the film forming method which does not expose the hydrogen in the dielectric film 9.

【0005】プラズマCVD法によるSiNや常圧又は減圧CVD法によるSiO 2の形成にあっては成膜中水素雰囲気にあるため、これらの膜を誘電体膜9の上部に形成すると、水素が誘電体膜9へ侵入し、その特性を劣化させてしまうので、これらの成膜法を採用することはできない。 [0005] Since SiN or atmospheric pressure or by plasma CVD method to In the formation of the SiO 2 by low pressure CVD method in a hydrogen atmosphere in the deposition, the formation of these films on top of the dielectric film 9, hydrogen dielectric It penetrates into the body membrane 9, so deteriorates the characteristics thereof, it is impossible to adopt these film forming methods. そこで、上記従来の不揮発性メモリの構造においては、第2の層間絶縁膜11とパッシベーション膜13はスパッタ法の成膜によるSiN膜とされる。 Therefore, in the above-described structure of the conventional nonvolatile memory, the second interlayer insulating film 11 and the passivation film 13 is a SiN film formed by deposition of sputtering. これは水素不放出の工程による成膜だからである。 This is because the film formation by the process of hydrogen not release. 一方、パッシベーション膜13は本来的に耐湿性の緻密な膜質が要求されるが、スパッタ法によるSiN膜は膜質の稠密性に欠け、耐湿性に劣るので、パッシベーション膜としては不向きである。 On the other hand, although dense film quality of inherently moisture resistance is required passivation film 13, SiN film by a sputtering method lacks dense film quality, since poor moisture resistance, is not suitable as a passivation film. 本発明は上記問題点を解決するものであり、その課題は、強誘電体膜の上部にこの強誘電体膜への水素侵入を防止する成膜法を採用することにより、残留分極及び比誘電率の高い強誘電体膜を要素とする半導体装置及びその製造方法を提供することにある。 The present invention has been made to solve the above problems, and an object thereof is, by adopting a film formation method for preventing hydrogen penetration into the ferroelectric film on the ferroelectric film, the remnant polarization and dielectric to provide a semiconductor device and a manufacturing method thereof and the rate of high ferroelectric film element.

【0006】 [0006]

【課題を解決するための手段】殊にPZTなどの耐水素性に乏しい強誘電体を用いたキャパシタ構造を有する半導体装置において、本発明の講じた手段は、例えばスパッタ法又は塗布法により形成された強誘電体膜の上部に水素不放出性の成膜法による耐湿性の水素バリア膜を設けたものである。 SUMMARY OF THE INVENTION In particular the semiconductor device having a capacitor structure using poor ferroelectric water resistance feature, such as PZT, means taken in the present invention are for example formed by a sputtering method or a coating method strength is provided with a moisture-resistant hydrogen barrier film by dielectric top hydrogen non-release of the film formation method of the membrane. この水素バリア膜の被覆範囲は全面に限らず、キャパシタ構造を覆う範囲にあれば良い。 Coverage of this hydrogen barrier film is not limited to the entire surface, it may be in a range that covers the capacitor structure. この水素バリア膜としてはスパッタ法によるTiN膜でも良いし、また酸素侵入型のTiONでも良い。 It this may be a TiN film by sputtering method as a hydrogen barrier film, also it may be TiON oxygen invasive. TiON膜の成膜法としては、TiN膜の酸素雰囲気でのプラズマ処理又は熱処理、窒素及び酸素雰囲気中でのTiターゲットによるスパッタ法やTiONのスパッタ法である。 The film formation method of TiON film, plasma treatment or heat treatment in an oxygen atmosphere of the TiN film, a sputtering sputtering or TiON by Ti target in nitrogen and oxygen atmosphere.
TiONは酸素含有率が小さいときは導電性で、酸素含有率が大きいときは絶縁性である。 TiON is conductive when the oxygen content is small, when the oxygen content is large is insulating. また酸素含有率の高いTiON膜は水素阻止能が高くなる。 The high TiON film having oxygen content of hydrogen stopping power is high.

【0007】この水素バリア膜の上に直接又は層間絶縁膜を介して腐食防止膜(プラズマCVD法によるSiN [0007] SiN by corrosion film (plasma CVD method directly or via an interlayer insulating film on the hydrogen barrier film
や常圧又は減圧CVD法によるSiO 2など)を被着させた構造も採用される。 And normal pressure or was deposited and SiO 2) by reduced pressure CVD method structure is also employed.

【0008】 [0008]

【作用】水素不放出性の成膜法による耐湿性の水素バリア膜を強誘電体膜の上部に覆うと、強誘電体膜の形成後において、プロセス中で発生する水素の当該強誘電体膜の侵入を防止することができ、残留分極や比誘電率の低下を回避できる。 [Action] Covering moisture resistance of the hydrogen barrier film by hydrogen non-release of the film formation method on top of the ferroelectric film, after formation of the ferroelectric film, the ferroelectric film of the hydrogen generated in the process can be prevented from entering, it is possible to avoid the deterioration of the residual polarization and dielectric constant. それ故、残留分極や比誘電率の高い強誘電体膜を有する半導体装置を得ることができる。 Therefore, it is possible to obtain a semiconductor device having a high ferroelectric film residual polarization and dielectric constant. 水素バリア膜の上部に腐食防止膜を形成した構造においては、水素バリア膜の腐食を防止できる。 In the structure formed of the corrosion prevention film on the hydrogen barrier film can prevent corrosion of the hydrogen barrier film. この腐食防止膜は膜質の緻密性を必要とするので、主にCVD法による成膜で、水素放出の成膜法に依らざる得ない。 Since the corrosion prevention film requires a dense film quality, mainly in film formation by a CVD method, forced obtained it does not depend on the film formation method of the hydrogen release. しかし、 But,
下層には水素バリア膜が存在するので、強誘電体への水素侵入の問題は発生しない。 Since the lower layer there is hydrogen barrier film, the problem of hydrogen penetration into the ferroelectric does not occur.

【0009】上記の製造方法は汎用的な手段であるが、 [0009] While the above manufacturing method is versatile means,
水素バリア膜として絶縁性(酸素含有率が大)のTiO TiO hydrogen barrier film as an insulating (oxygen content large)
N膜を成膜する場合には、上述の腐食防止膜の成膜工程を削減できる。 In the case of forming the N film can reduce the film forming process of the corrosion preventing film described above.

【0010】 [0010]

【発明の実施の形態】次に、本発明の実施例を添付図面に基づいて説明する。 DETAILED DESCRIPTION OF THE INVENTION will be described with reference to embodiments of the present invention in the accompanying drawings.

【0011】[第1実施例]図1は本発明の第1実施例に係る半導体メモリの構造を示す断面図である。 [First Embodiment] FIG. 1 is a sectional view showing a structure of a semiconductor memory according to the first embodiment of the present invention.

【0012】p型半導体基板1の表面には熱酸化によるゲート絶縁膜2とMOSのアクティブ領域を区画形成すべき厚い酸化膜のLOCOS(局所酸化膜)6が形成される。 [0012] p-type semiconductor substrate 1 of the surface of the thick oxide film is to be defined and formed an active region of the gate insulating film 2 and the MOS by thermal oxidation LOCOS (local oxide film) 6 is formed. 転送トランジスタTはゲート絶縁膜2を介して形成された多結晶シリコン・ゲート3と、この多結晶シリコン・ゲート3をマスクとしてp型半導体基板1の表面側にセルフアラインで形成された高濃度n型領域たるソース・ドレイン領域4,5とから構成されている。 The transfer transistor T is a polysilicon gate 3 formed through a gate insulating film 2, a high concentration n formed by self-alignment on the surface side of the p-type semiconductor substrate 1 of the polycrystalline silicon gate 3 as a mask and a type region serving as the source and drain regions 4 and 5 Metropolitan. 一方、ストレージ・キャパシタCはフィールド酸化膜たるLOCOS(局所酸化膜)6上に構成されている。 On the other hand, the storage capacitor C is constructed on the field oxide film serving as LOCOS (local oxide film) 6.

【0013】先ず、LOCOS6,多結晶シリコン・ゲート3の上にはCVDにより緻密な第1の層間絶縁膜(SiO 2又はSiN)7が全面形成される。 [0013] First, LOCOS6, dense first interlayer insulating film by CVD on top of the polycrystalline silicon gate 3 (SiO 2 or SiN) 7 is formed over the entire surface. 次に、この層間絶縁膜7のうちLOCOS6の真上にスパッタ法で白金(Pt)の下部平板電極8が形成される。 Then, lower plate electrode 8 of platinum (Pt) is formed by sputtering directly above the LOCOS6 of the interlayer insulating film 7. 次に、この下部平板電極8上の一部にはスパッタ法又は塗布法により強誘電体たるPZT(Pb(Ti x Zr y )O 3 )の誘電体膜9が形成される。 Next, the dielectric film 9 of this part of the lower plate electrode 8 serving ferroelectric by a sputtering method, a coating method, or PZT (Pb (Ti x Zr y ) O 3) is formed. また次に、この誘電体膜9の上にはスパッタ法で白金の上部平板電極10が形成され、ストレージ・キャパシタCが得られる。 Also then, this on the dielectric film 9 upper plate electrode 10 of platinum is formed by sputtering, the storage capacitor C is obtained.

【0014】次に、第1の層間絶縁膜7の上にはスパッタ法によるSiNの第2の層間絶縁膜(下部層間絶縁膜)11が形成される。 [0014] Next, first second interlayer insulating film on the interlayer insulating film 7 of SiN by a sputtering method (lower interlayer insulating film) 11 is formed. そして、ソース・ドレイン領域5,上部平板電極10,下部平板電極8の部位にコンタクト穴が窓明けされる。 Then, the source-drain region 5, the upper plate electrode 10, a contact hole in a portion of the lower plate electrode 8 is Apertures.

【0015】次に、この層間絶縁膜11の上にはスパッタ法によりAl配線が形成される。 [0015] Next, Al wiring is formed by sputtering on the interlayer insulating film 11. Al配線12aはソース・ドレイン領域5と上部平板電極10とをコンタクト穴を介して導通させるセル内部配線で、Al配線12 Al wiring 12a is a cell interior wiring for electrically connecting the source and drain regions 5 and the upper plate electrode 10 via the contact hole, Al wiring 12
bは下部平板電極8と図示しないパッド部とを導通させる接地配線である。 b is a ground wiring for electrically connecting the pad portion (not shown) and the lower plate electrode 8. なお、図1には示されていないが、 Although not shown in FIG. 1,
多結晶シリコン・ゲート3に導通するワード線及びソース・ドレイン領域4に導通するビット線は上記Al配線と同一層に形成されている。 Bit lines electrically connected to the word line and the source-drain regions 4 electrically connected to the polycrystalline silicon gate 3 is formed in the same layer as the Al wiring.

【0016】次に、Al配線12a,12bの上にはスパッタ法によるSiNの第3の層間絶縁膜(上部層間絶縁膜)13'が形成されている。 [0016] Next, Al wiring 12a, the third interlayer insulating film of SiN by a sputtering method (upper interlayer insulating film) 13 'is formed on the 12b. 勿論、この工程中では水素不放出であることから、誘電体膜9の特性劣化の問題は発生しない。 Of course, since in during the process is hydrogen not release, problems characteristic deterioration of the dielectric film 9 does not occur. 第3の層間絶縁膜13'の膜質は緻密性に欠けるがので、パッシベーション膜としての意義は少なく、後述するように、導電性で耐湿性の水素バリア膜14とAl配線12a,12bとの層間絶縁膜たる意義を有する。 Since Although quality of the third interlayer insulating film 13 'lacks denseness less significance as a passivation film, as described later, the moisture resistance of the hydrogen barrier film 14 and the Al wirings 12a with a conductive interlayer between 12b an insulating film serving significance.

【0017】次に、第3の層間絶縁膜13'の上にスパッタ法でTiN膜を耐湿性の水素バリア膜14として形成する。 [0017] Then, a TiN film as a hydrogen barrier film 14 of the moisture resistance by sputtering on the third interlayer insulating film 13 '. この成膜過程においては水素の発生がないため、誘電体膜9の特性劣化の問題は発生しない。 Therefore there is no generation of hydrogen in the film forming process, the problem of characteristic degradation of the dielectric film 9 does not occur. 本発明者は水素バリア膜14としてこのTiN膜が好適であるを見出した。 The present inventors have this TiN film is found to be suitable as a hydrogen barrier film 14. 一般に半導体技術においてTiN膜はシリコンとAlのバリアメタルとして知られているが、このTiN膜は緻密性に富み、導電性の膜であるため、耐湿性で水素非透過性の保護膜であると共に、電磁シールド機能をも果たす。 Although the TiN film in general semiconductor technology known as barrier metal of silicon and Al, the TiN film is rich in denseness, since a conductive film, as well as a hydrogen non-permeable protective film moisture resistance , also plays an electromagnetic shielding function. この窒化チタン(TiN;チタンナイトライド)は酸化して酸素侵入型のTiONとなり易い。 The titanium nitride (TiN; titanium nitride) is easy TiON next oxygen interstitial oxidized. 酸素含有率の高いTiONは水素非透過性がより高くなり、水素バリア膜として優れている。 High oxygen content TiON is impermeable becomes higher hydrogen, it is excellent as a hydrogen barrier film. したがって、 Therefore,
この水素バリア膜14としてはTiON膜であっても良い。 It may be a TiON film as the hydrogen barrier film 14. TiON膜の成膜法としては次のいずれかの方法を採用する。 The film formation method of TiON film adopts one of the following methods.

【0018】 TiN膜の酸素雰囲気でのプラズマ処理法 TiN膜の酸素雰囲気での熱処理法 N 2 ,O 2雰囲気中でのTiターゲットによるスパッタ法 TiONのスパッタ法 なお、水素バリア膜が酸素含有率の高いTiONである場合には、導電性でないから層間絶縁膜13'の形成は不要である。 The sputtering TiON by Ti target at heat treatment process N 2, O 2 atmosphere in an oxygen atmosphere plasma treatment TiN film in an oxygen atmosphere TiN film sputtering Incidentally, the hydrogen barrier film is an oxygen content If it is high TiON, the formation of the interlayer insulating film 13 'do not electrically conductive is not required.

【0019】ところで、水素バリア膜14はTiN膜又TiON膜であるので、一般に導電性を有しているが、 By the way, since the hydrogen barrier film 14 is a TiN film or TiON film, but generally has conductivity,
酸素侵入型のTiONは酸素含有率が小なるときは導電性を帯び、酸素含有率が大なるときは絶縁性となる。 TiON oxygen intrusive when oxygen content is small is tinged conductivity becomes insulating when the oxygen content becomes large.

【0020】[第2実施例]図2は本発明の第2実施例に係る半導体メモリの構造を示す断面図である。 [0020] [Second Embodiment] FIG. 2 is a sectional view showing a structure of a semiconductor memory according to the second embodiment of the present invention. なお、 It should be noted that,
図2において図1に示す部分と同一部分には同一参照符号を付し、その説明は省略する。 2 are denoted by the same reference numerals, the same parts as the parts shown in FIG. 1, a description thereof will be omitted.

【0021】この実施例においては、水素バリア膜14 [0021] In this embodiment, the hydrogen barrier film 14
の上にプラズマCVD法によるSiN膜や常圧又は減圧CVD法によるSiO 2膜の腐食防止膜15を形成する。 The SiN film or atmospheric pressure or by plasma CVD on the forming corrosion preventing film 15 of SiO 2 film by low pressure CVD method. この膜は緻密性に富み湿気の侵透を阻止するので、 This film prevents the 侵透 moisture rich in denseness,
水素バリア膜14の腐食を防止することができる。 It is possible to prevent corrosion of the hydrogen barrier film 14. プラズマCVD法によるSiN膜や常圧又は減圧CVD法によるSiO 2膜の成膜法は、水素の発生又は水素雰囲気中でのプロセスであるが、その水素侵入は既に形成された水素バリア膜14によって阻止されるため、誘電体膜9への影響を惹起させることはない。 Method of forming the SiO 2 film SiN film or atmospheric pressure or by low pressure CVD method by a plasma CVD method is the process in generating or hydrogen atmosphere at a hydrogen, the hydrogen barrier film 14 that hydrogen penetration is already formed to be blocked, it is not possible to elicit the effect on the dielectric film 9.

【0022】[第3実施例]図3は本発明の第3実施例に係る半導体メモリの構造を示す断面図である。 [0022] [Third Embodiment] FIG. 3 is a sectional view showing a structure of a semiconductor memory according to the third embodiment of the present invention. なお、 It should be noted that,
図3において図2に示す部分と同一部分には同一参照符号を付し、その説明は省略する。 Denoted by the same reference numerals, the same parts as the parts shown in FIG. 2 in FIG. 3, a description thereof will be omitted.

【0023】この第3実施例の第2実施例に対して異なる点は、TiN膜又はTiON膜の水素バリア膜14' [0023] This is different from the second example of the third embodiment, the hydrogen barrier film 14 of TiN film or TiON film '
の形成領域をストレージ・キャパシタ構造を覆う範囲に限定したところにある。 Certain areas of the formed were limited to a range covering the storage capacitor structure. 水素バリア膜14'の意義は、 The significance of the hydrogen barrier film 14 ',
耐湿性のあることは勿論のこと、その成膜中では水素不放出性で且つ水素非透過性であれば良い。 Of course be a moisture resistance, it may be any and hydrogen non-permeable hydrogen non-release property in the film formation. 水素バリア膜牒14'の上に形成するプラズマCVD法によるSiN SiN by plasma CVD method to be formed on the hydrogen barrier Maku牒 14 '
膜や常圧又は減圧CVD法によるSiO 2膜の腐食防止膜15は、その成膜中に水素の発生を招くが、積層構造の下層へ水素が侵入しても誘電体膜9へ到達しないよう水素バリア膜14'が水素侵入を遮蔽すれば充分である。 SiO 2 film corrosion film 15 due to the film or atmospheric pressure or reduced pressure CVD method, but leads to the generation of hydrogen during the deposition, so as not to reach the dielectric film 9 also hydrogen into the underlying laminate structure penetrates hydrogen barrier film 14 'is sufficient to shield the penetration of hydrogen. 水素バリア14'はストレージ・キャパシタ構造を覆う範囲で水素の侵入を遮蔽する。 Hydrogen barrier 14 'shields hydrogen penetration within a range covering the storage capacitor structure. 横方向からの水素の侵入到達距離が長いことから殆ど問題とはならない。 Intrusion reach of the hydrogen from the lateral direction does not become little problem since a long time.

【0024】ところで、第1実施例や第2実施例において、全面的に形成される水素バリア膜14がTiN膜や酸素含有率の小なるTiON膜の場合は導電性を有するので、Al配線12bと同一層に形成されるパッド部とこれに接続すべきボンディング・ワイヤとの接続方法について検討する必要がある。 By the way, in the first embodiment and the second embodiment, since if the hydrogen barrier film 14 is entirely formed of small becomes TiON film of TiN film and oxygen content has conductivity, Al wiring 12b it is necessary to consider a method of connecting a pad portion and a bonding wire to be connected thereto are formed in the same layer as the. 一般的な接続方法を図4に示す。 The typical connection methods shown in FIG. 先ず、図4(A)に示すように、第2の層間絶縁膜の上にAlパッド部12cをAl配線12bと同一層で形成した後、第2の層間絶縁膜13',導電性の水素バリア膜14及び腐食防止膜15を順次形成し、次に、 First, as shown in FIG. 4 (A), after forming the Al pad portion 12c with the Al wiring 12b and the same layer on the second interlayer insulating film, the second interlayer insulating film 13 ', a conductive hydrogen sequentially forming a barrier film 14 and the anti-corrosion film 15, then,
図4(B)に示す如く、Alパッド部12cの真上の3 As shown in FIG. 4 (B), 3 just above the the Al pad portion 12c
層をエッチング処理で除去してコンタクト穴16を形成してから、図4(C)に示すように、ボンディング・ワイヤ17をAlパッド部12cの露出領域に対し圧着する。 After forming the contact holes 16 to remove the layer by etching process, as shown in FIG. 4 (C), crimping the bonding wires 17 to the exposed region of the Al pad portion 12c. かかる接続法によれば、ボンディング・ワイヤ17 According to such a connection method, the bonding wire 17
の圧着によってAlパッド部12cのみならずコンタクト穴の側壁に望む導電性の水素バリア膜14にもボンディング・ワイヤ17が導通してしまう。 Crimping will also conduct bonding wire 17 to the Al pad portion 12c electrically conductive hydrogen barrier film 14 wishing to side walls of the contact holes not only by the. これは他のボンディング・ワイヤとのショートを引き起こす。 This causes a short circuit between the other bonding wire.

【0025】図5は、上記問題点を解決するため、パッド部とボンディング・ワイヤとの改善接続方法を示す工程図である。 [0025] Figure 5, in order to solve the above problems, is a process diagram showing an improved connecting method of a pad portion and a bonding wire.

【0026】先ず、図5(A)に示すように、第2の層間絶縁膜の上にAlパッド部12cをAl配線12bと同一層で形成し、この上に第2の層間絶縁膜13'及び導電性の水素バリア膜14を順次形成する。 [0026] First, as shown in FIG. 5 (A), the Al pad portion 12c on the second interlayer insulating film formed in the same layer as the Al wiring 12b, the second interlayer insulating film 13 on the ' and sequentially forming a hydrogen barrier film 14 of the conductive.

【0027】次に、図5(B)に示す如く、腐食防止膜15の形成の前に、Alパッド部12cの真上の3層をエッチング処理で除去して窓明け部16aを形成して一旦Alパッド部12cを露出させる。 Next, as shown in FIG. 5 (B), prior to the formation of corrosion film 15, to form the Al pad portion Apertures portion 16a by removing the three layers in the etching process immediately above the 12c once exposing the Al pad portion 12c. その露出領域をX The exposed area X
とする。 To.

【0028】次に、図5(C)に示すように、上記露出領域Xをも含めて水素バリア膜14の上に腐食防止膜1 Next, FIG. 5 (C), the corrosion film 1 on the hydrogen barrier film 14, including the exposed region X
5'を形成する。 5 'are formed. ここではコンタクト穴16a内も腐食防止膜15'で覆われる。 Here also the contact hole 16a is covered with a corrosion prevention layer 15 '.

【0029】次に、図5(D)に示すように、Alパッド部12cの真上の1層の腐食防止膜15をエッチング処理で除去してコンタクト穴16bを形成する。 Next, as shown in FIG. 5 (D), to remove the corrosion preventing film 15 of one layer just above the Al pad portion 12c by etching to form a contact hole 16b. Alパッド部12c表面に形成すべき露出領域の広さ範囲Yは上記露出領域の広さ範囲Xに比して狭く設定する。 Al breadth range Y of the exposed region for forming the pad portion 12c surface is set to be narrower than the breadth range X of the exposed area.

【0030】次に、図5(E)に示すように、ボンィング・ワイヤ17をAlパッド部12cの露出領域Yに対し圧着する。 Next, as shown in FIG. 5 (E), crimping the Boningu wire 17 to the exposed region Y of the Al pad portion 12c.

【0031】このような接続方法を採用すると、ボンディング・ワイヤ17がAlパッド部12cにのみ導通し、導電性の水素バリア膜14には導通しない。 [0031] By adopting such a connecting method, the bonding wire 17 becomes conductive only to the Al pad portion 12c, and does not conduct in the hydrogen barrier film 14 of the conductive. 水素バリア膜14とボンディング・ワイヤ17とは腐食防止膜15で絶縁されているからである。 The hydrogen barrier film 14 and the bonding wire 17 is because it is insulated by the corrosion preventing film 15. なお、Alパッド部12cとボンディング・ワイヤ17との接続に限らず、 The present invention is not limited to the connection of the Al pad portion 12c and the bonding wire 17,
Alパッド部12cとバンプとの接続、Al配線と上層のAlの接続(スルーホール接続)にも上記接続方法を適用できる。 Connection between the Al pad portion 12c and the bump, to connect the Al wiring and an upper Al (through hole connection) can be applied the connection method.

【0032】水素侵入による特性劣化の問題は、強誘電体膜に限らず、多結晶シリコン・ゲートを有するCMO The problem of property deterioration by hydrogen penetration is not limited to a ferroelectric film, CMO with polysilicon gate
S集積回路等においても問題となる。 Also a problem in S integrated circuits and the like. 多結晶シリコン・ Polycrystalline silicon
ゲートが水素に触れると、しきい値の変動を招き、歩留まりの悪化要因となる。 When the gate touches hydrogen, it leads to variation in the threshold, a worsening factor for yield. それ故、耐湿性の水素バリア膜を強誘電体膜の保譲だけでなく、多結晶シリコン・ゲートの保覆膜をしてその上部に形成しておくことは、多結晶シリコン・ゲートの特性の安定性に寄与する。 Therefore, not only TamotsuYuzuru ferroelectric film moisture resistance of the hydrogen barrier film, to be formed thereon by the coercive Kutsugaemaku polysilicon gate is polysilicon gate characteristics It contributes to the stability of.

【0033】 [0033]

【発明の効果】以上説明したように、本発明は、強誘電体又は多結晶シリコン・ゲートを要素とする半導体装置において、強誘電体又は多結晶シリコン・ゲートの上部に水素不放出性の成膜法によりなるTiN膜やTiON As described above, according to the present invention, the strength in the semiconductor device as a dielectric or polysilicon gate elements, ferroelectric or polysilicon gate upper hydrogen non-release configuration of TiN film or a TiON made by the membrane method
膜等の耐湿性の水素バリア膜を形成した点に特徴を有するものである。 And it has a feature in that to form a moisture-resistant hydrogen barrier film film. 従って以下の効果を奏する。 Thus the following effects.

【0034】 水素バリア膜の形成自体が水素を発生しないので、強誘電体又は多結晶シリコン・ゲートヘの水素侵入の影響がない。 [0034] Since the formation itself of the hydrogen barrier film does not generate hydrogen, there is no influence of hydrogen penetration of the ferroelectric or the polycrystalline silicon Getohe. また水素バリア膜の形成後に水素放出性の成膜法が使用された場合や水素雰囲気に半導体装置自身が置かれた場合でも水素バリア膜がその水素の侵入を阻止する。 The hydrogen barrier film even when the semiconductor device itself is placed in the case or hydrogen atmosphere hydrogen release of deposition method is used after the formation of the hydrogen barrier film prevents the penetration of the hydrogen. 従って、強誘電体の残留分極や比誘電率の低下、多結晶シリコン・ゲートのしきい値の変動等のような水素侵入による特性劣化の問題を回避できる。 Therefore, reduction of the residual polarization and the dielectric constant of the ferroelectric, the problem of characteristic degradation due to hydrogen penetration, such as the fluctuation of the threshold of the polycrystalline silicon gate can be avoided.

【0035】 腐食性の水素バリアの場合、その上に腐食防止膜を形成した構造を採用すると、水素バリアの腐食を防止できることは勿論、その腐食防止膜の形成が水素放出性の成膜法による場合であっても、強誘電体又は多結晶シリコン・ゲートヘの水素の侵入の問題は生じさせない。 In the case of a corrosive hydrogen barrier, when adopting the structure of forming the corrosion preventing film thereon, it can be prevented the corrosion of the hydrogen barrier well, formation of the corrosion preventing film by hydrogen release of the film formation method even if, ferroelectric or polycrystalline silicon Getohe hydrogen penetration problems are not caused.

【0036】 絶縁性のあるTiON膜を耐湿性の水素バリア膜として形成した場合には、水素阻止能が高い構造を得ることができる。 [0036] in the case of forming a TiON film having insulating properties as moisture resistance of the hydrogen barrier film may be hydrogen stopping power to obtain a high structural. また層間絶縁膜も削減することができる。 Also it is possible to reduce even interlayer insulating film.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】 本発明の第1実施例に係る半導体メモリの構造を示す断面図である。 1 is a cross-sectional view showing a structure of a semiconductor memory according to the first embodiment of the present invention.

【図2】 本発明の第2実施例に係る半導体メモリの構造を示す断面図である。 2 is a sectional view showing a structure of a semiconductor memory according to the second embodiment of the present invention.

【図3】 本発明の第3実施例に係る半導体メモリの構造を示す断面図である。 3 is a cross-sectional view showing a structure of a semiconductor memory according to the third embodiment of the present invention.

【図4】 (A)乃至(C)は同半導体メモリにおけるパッド部とボンディング・ワイヤとの一般的な接続方法を示す工程図である。 [4] (A) to (C) are views showing steps of a general method of connecting the pad portion and a bonding wire in the same semiconductor memory.

【図5】 (A)乃至(E)は同半導体メモリにおけるパッド部とボンディング・ワイヤとの改善された接続方法を示す工程図である。 [5] (A) to (E) are process diagrams showing an improved connecting method of a pad portion and a bonding wire in the same semiconductor memory.

【図6】 従来における半導体メモリの構造の一例を示す断面図である。 6 is a sectional view showing an example of a structure of a semiconductor memory in the prior art.

【符号の説明】 DESCRIPTION OF SYMBOLS

1・・・p型半導体基板 2・・・ゲート絶縁膜 3・・・多結晶シリコン・ゲート 4、5・・・高濃度n型のソース・ドレイン領域 6・・・LOCOS(局所酸化膜) 7・・・第1の層間絶縁膜 8・・・白金の下部平板電極 9・・・強誘電体たるPZT(Pb(Ti x Zr y 1 ... p-type semiconductor substrate 2 ... gate insulating film 3 ... polysilicon gate 4,5, ... high concentration n-type source and drain regions 6 ... LOCOS (local oxide film) 7 ... first interlayer insulating film 8 ... platinum lower plate electrode 9 ... ferroelectric serving PZT (Pb (Ti x Zr y )
3 )の誘電体膜 10・・・白金の上部平板電極 11・・・第2の層間絶縁膜 12a,12b・・・Al配線 12c・・・Alパッド部 13'・・・第3の層間絶縁膜 14、14'・・・水素バリア膜(スパッタ法等によるTiN膜やTiON膜) 15・・・腐食防止膜 16a・・・窓明け部 16b・・・コンタクト穴 17・・・ボンディング・ワイヤ T・・・転送トランジスタ C・・・ストレージ・キャパシタ X,Y・・・露出領域の広さ範囲 O 3) of the dielectric film 10 ... platinum upper plate electrode 11 ... second interlayer insulating film 12a, 12b ... Al wiring 12c ... Al pad portion 13 '... third interlayer insulating film 14, 14 '... hydrogen barrier film (TiN film or TiON film by a sputtering method, or the like) 15 ... corrosion film 16a ... window drilling unit 16b ... contact hole 17 ... bonding wire T · · · transfer transistor C · · · storage capacitor X, wide range of Y · · · exposed region

───────────────────────────────────────────────────── ────────────────────────────────────────────────── ───

【手続補正書】 [Procedure amendment]

【提出日】平成11年7月12日(1999.7.1 [Filing date] 1999 July 12 (1999.7.1
2) 2)

【手続補正1】 [Amendment 1]

【補正対象書類名】明細書 [Correction target document name] specification

【補正対象項目名】発明の名称 [Correction target item name] name of the invention

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【発明の名称】 半導体装置 [Name of the invention a semiconductor device

【手続補正2】 [Amendment 2]

【補正対象書類名】明細書 [Correction target document name] specification

【補正対象項目名】特許請求の範囲 [Correction target item name] the scope of the appended claims

【補正方法】変更 [Correction method] change

【補正内容】 [Correction contents]

【特許請求の範囲】 [The claims]

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl. 7識別記号 FI テーマコート゛(参考) H01L 27/092 H01L 29/78 301N 27/108 21/8242 29/78 ────────────────────────────────────────────────── ─── of the front page continued (51) Int.Cl. 7 identification mark FI theme Court Bu (reference) H01L 27/092 H01L 29/78 301N 27/108 21/8242 29/78

Claims (9)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 強誘電体膜又は多結晶シリコン・ゲートを要素とする半導体装置であって、該要素の上部において少なくとも該要素を覆う範囲に、水素不放出性の成膜法によりなる耐湿性の水素バリア膜を具有することを特徴とする半導体装置。 1. A semiconductor device for a ferroelectric film or a polycrystalline silicon gate elements, in a range covering at least the elements in the upper part of the element, moisture resistance comprising a hydrogen non-release of the film formation method wherein a is androgynous a hydrogen barrier film.
  2. 【請求項2】 請求項第1項記載において、前記水素バリア膜の上部にはこれを覆う腐食防止膜を具有することを特徴とする半導体装置。 2. A semiconductor device according to claim any preceding claim, characterized in that the upper portion of the hydrogen barrier film for androgynous corrosion film that covers it.
  3. 【請求項3】 請求項第1項又は第2項記載において、 3. A first claims or paragraph 2, wherein,
    前記バリア膜がTiN膜であることを特徴とする半導体装置。 Wherein a said barrier layer is a TiN film.
  4. 【請求項4】 請求項第1項又は第2項記載において、 4. A first claims or paragraph 2, wherein,
    前記水素バリア膜がTiON膜であることを特徴とする半導体装置。 Wherein a said hydrogen barrier film is a TiON film.
  5. 【請求項5】 請求項第2項乃至第4項記載のいずれか一項記載において、前記腐食防止膜はSiN膜であることを特徴とする半導体装置。 5. A according to any one of claims second term to described item 4, wherein a said anti-corrosion film is SiN film.
  6. 【請求項6】 請求項第1項ないし第5項のいずれか一項記載の半導体装置を用いた半導体メモリ。 6. A semiconductor memory using a semiconductor device of any one of claims the first term through the fifth term.
  7. 【請求項7】 請求項第1項ないし第5項のいずれか一項記載の半導体装置を用いたCMOS半導体集積回路。 7. A CMOS semiconductor integrated circuit using a semiconductor device of any one of claims the first term through the fifth term.
  8. 【請求項8】 強誘電体膜又は多結晶シリコン・ゲートを要素とする半導体装置の製造方法において、該強誘電体膜又は多結晶シリコン・ゲートを形成した後に水素不放出性の成膜法により層問絶縁膜を形成する工程と、該要素の上部で少なくとも該要素を覆う範囲に、水素不放出性の成膜法により耐湿性の水素バリア膜を形成する工程と、を有することを特徴とする半導体装置の製造方法。 8. A strong manufacturing method of a semiconductor device as a dielectric film or a polycrystalline silicon gate elements, by hydrogen non-release of the film formation method after forming the ferroelectric film or a polycrystalline silicon gate forming a Sotoi insulating film, in a range covering at least the element at the top of the element, and characterized by having the steps of forming a moisture-resistant hydrogen barrier film by hydrogen non-release of the film formation method the method of manufacturing a semiconductor device to be.
  9. 【請求項9】 請求項第8項に記載の製造方法において、前記水素バリア膜の形成工程の後、該水素バリア膜の上に腐食防止膜を覆う工程、を有することを特徴とする半導体装置の製造方法。 9. The method according to claim Section 8, after the hydrogen barrier film formation step, the semiconductor device characterized by having a step, which covers the corrosion film on the hydrogen barrier film the method of production.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7750485B2 (en) 2005-07-05 2010-07-06 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7750485B2 (en) 2005-07-05 2010-07-06 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same
US8076212B2 (en) 2005-07-05 2011-12-13 Fujitsu Semiconductor Limited Semiconductor device and method for manufacturing the same

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