TW442753B - Data processor system having branch control and method thereof - Google Patents

Data processor system having branch control and method thereof Download PDF

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Publication number
TW442753B
TW442753B TW088108747A TW88108747A TW442753B TW 442753 B TW442753 B TW 442753B TW 088108747 A TW088108747 A TW 088108747A TW 88108747 A TW88108747 A TW 88108747A TW 442753 B TW442753 B TW 442753B
Authority
TW
Taiwan
Prior art keywords
instruction
branch
address
input
output
Prior art date
Application number
TW088108747A
Other languages
English (en)
Chinese (zh)
Inventor
Lea Hwang Lee
William C Moyer
Jeffrey W Scott
John H Arends
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of TW442753B publication Critical patent/TW442753B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
TW088108747A 1998-06-19 1999-05-27 Data processor system having branch control and method thereof TW442753B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/100,669 US6401196B1 (en) 1998-06-19 1998-06-19 Data processor system having branch control and method thereof

Publications (1)

Publication Number Publication Date
TW442753B true TW442753B (en) 2001-06-23

Family

ID=22280928

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088108747A TW442753B (en) 1998-06-19 1999-05-27 Data processor system having branch control and method thereof

Country Status (7)

Country Link
US (1) US6401196B1 (ko)
EP (1) EP0965910B1 (ko)
JP (1) JP2000029700A (ko)
KR (1) KR100597328B1 (ko)
CN (1) CN1189816C (ko)
DE (1) DE69919081T2 (ko)
TW (1) TW442753B (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8055885B2 (en) 2004-03-29 2011-11-08 Japan Science And Technology Agency Data processing device for implementing instruction reuse, and digital data storage medium for storing a data processing program for implementing instruction reuse

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JP3470948B2 (ja) * 1999-01-28 2003-11-25 インターナショナル・ビジネス・マシーンズ・コーポレーション 動的コンパイル時期決定方法、バイトコード実行モード選択方法、及びコンピュータ
EP1163577B1 (de) * 1999-03-17 2003-11-26 Infineon Technologies AG Cachen kurzer programmschleifen innerhalb eines instruktions-fifos
US6539541B1 (en) * 1999-08-20 2003-03-25 Intel Corporation Method of constructing and unrolling speculatively counted loops
US6604163B1 (en) * 2000-05-16 2003-08-05 Koninklijke Philips Electronics N.V. Interconnection of digital signal processor with program memory and external devices using a shared bus interface
EP1369774A1 (fr) * 2002-06-06 2003-12-10 CSEM Centre Suisse d'Electronique et de Microtechnique SA Recherche et Développement Dispositif d'élaboration d'adresses pour un processeur de signaux numériques
US20040003210A1 (en) * 2002-06-27 2004-01-01 International Business Machines Corporation Method, system, and computer program product to generate test instruction streams while guaranteeing loop termination
US7130963B2 (en) * 2003-07-16 2006-10-31 International Business Machines Corp. System and method for instruction memory storage and processing based on backwards branch control information
US7269710B1 (en) 2004-07-23 2007-09-11 Zilog, Inc. Program memory space expansion for particular processor instructions
US7415599B1 (en) * 2005-11-01 2008-08-19 Zilog, Inc. Instruction operation and operand memory location determined based on preceding instruction operation and operand memory location
US7475231B2 (en) * 2005-11-14 2009-01-06 Texas Instruments Incorporated Loop detection and capture in the instruction queue
TW200723094A (en) * 2005-12-01 2007-06-16 Ind Tech Res Inst Dynamic branch prediction system and method
US20080040590A1 (en) * 2006-08-11 2008-02-14 Lea Hwang Lee Selective branch target buffer (btb) allocaiton
US20080040591A1 (en) * 2006-08-11 2008-02-14 Moyer William C Method for determining branch target buffer (btb) allocation for branch instructions
ATE466331T1 (de) * 2006-09-06 2010-05-15 Silicon Hive Bv Datenverarbeitungsschaltung mit mehreren anweisungsarten, verfahren zum betrieb einer solchen datenschaltung und scheduling-verfahren für eine solche datenschaltung
US20090182984A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Execute Relative Long Facility and Instructions Therefore
CN102369941B (zh) * 2010-08-20 2014-04-23 海利尔药业集团股份有限公司 一种含有联苯肼酯和溴虫腈的杀虫杀螨组合物
JPWO2013069551A1 (ja) * 2011-11-09 2015-04-02 日本電気株式会社 デジタル信号プロセッサ、プログラム制御方法、および制御プログラム
US20120185714A1 (en) * 2011-12-15 2012-07-19 Jaewoong Chung Method, apparatus, and system for energy efficiency and energy conservation including code recirculation techniques
US9436473B2 (en) * 2013-10-08 2016-09-06 Arm Limited Scheduling program instructions with a runner-up execution position
CN107580700B (zh) * 2015-09-29 2020-10-09 华为技术有限公司 一种生成地址的方法及数据处理设备
US10846097B2 (en) * 2018-12-20 2020-11-24 Samsung Electronics Co., Ltd. Mispredict recovery apparatus and method for branch and fetch pipelines
CN112988233B (zh) * 2021-02-06 2024-03-26 江南大学 一种面向分支指令预测的偏差矫正器及方法

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Publication number Priority date Publication date Assignee Title
US3573854A (en) * 1968-12-04 1971-04-06 Texas Instruments Inc Look-ahead control for operation of program loops
US4566063A (en) * 1983-10-17 1986-01-21 Motorola, Inc. Data processor which can repeat the execution of instruction loops with minimal instruction fetches
US4755966A (en) * 1985-06-28 1988-07-05 Hewlett-Packard Company Bidirectional branch prediction and optimization
EP0374419A3 (en) * 1988-12-21 1991-04-10 International Business Machines Corporation Method and apparatus for efficient loop constructs in hardware and microcode
US5778423A (en) * 1990-06-29 1998-07-07 Digital Equipment Corporation Prefetch instruction for improving performance in reduced instruction set processor
US5920713A (en) * 1995-10-06 1999-07-06 Advanced Micro Devices, Inc. Instruction decoder including two-way emulation code branching
US5893142A (en) * 1996-11-14 1999-04-06 Motorola Inc. Data processing system having a cache and method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8055885B2 (en) 2004-03-29 2011-11-08 Japan Science And Technology Agency Data processing device for implementing instruction reuse, and digital data storage medium for storing a data processing program for implementing instruction reuse

Also Published As

Publication number Publication date
US6401196B1 (en) 2002-06-04
CN1240279A (zh) 2000-01-05
EP0965910A3 (en) 2000-05-24
CN1189816C (zh) 2005-02-16
DE69919081T2 (de) 2005-01-27
KR100597328B1 (ko) 2006-07-10
DE69919081D1 (de) 2004-09-09
KR20000006302A (ko) 2000-01-25
JP2000029700A (ja) 2000-01-28
EP0965910A2 (en) 1999-12-22
EP0965910B1 (en) 2004-08-04

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