TW441018B - Manufacturing method for etching off the sidewall structure in a self-aligned process - Google Patents

Abstract

There is provided a manufacturing method for etching off the sidewall structure in a self-aligned process, which can increase the gate space thereby reducing the design specification. The method comprises the steps of: (i) depositing gate material on a substrate, defining a gate area, lightly doping the drain, and growing an oxide; (ii) forming a separation layer on two sides of the gate, and performing a source and drain implantation; (iii) forming a self-aligned contact etching stop layer; (iv) forming an inter-layer of dielectric material, using the etching back or chemical mechanical polishing process to flatten the surface, and defining the self-aligned area; (v) performing a self-aligned contact etching process and removing etching stop layer of the self-aligned contact; (vi) removing the separation object in the self-aligned contact; (vii) forming a thin dielectric layer by depositing, and forming a thin separation object on the sidewall of the gate by etching back; and (viii) finally, forming a tungsten plug by depositing. In addition, the above method can be performed by using compound separation object to achieve the object of forming thin separation object. Accordingly, it is able to increase the etching margin of the self-aligned contact, and also increase the contact area of the self-aligned contact, thereby decreasing the contact resistance.

Description

4 410 18 V. Description of the invention (1) The present invention relates to a manufacturing method of a structure in which a side ridge layer is etched away in a self-alignment process. Among all semiconductor memories, SRAM (Static Random Access Memory) is one of the fastest processing types of memory. It is mainly based on the conductive state of the transistor in the memory cell to store data. In general, the most commonly used SRAM architecture includes six transistors, as shown in Figure 1, 'that is, the enhanced NM0S transistor 10' as a stimulator 12 ', which is used to access the data in the SRAM. The reinforced NMOS transistor 14'16 is used, and the empty NMOS transistor 18,20 is used as a load. That is, because each of the memory cells requires six transistors, the density of SRAM will be lower ', so it will be more expensive ^ In order to increase the density of SRAM with six transistors, the layout of the memory cells The size must be minimized. However, in the conventional self-alignment process, ‘the gap between the gate electrodes is difficult to be narrowed because the sidewall layer has a certain thickness and the self-aligned contact window ’s engraved boundary is required. Please refer to FIG. 2a to FIG. 2f. 'The traditional process system includes the following steps: 0) As shown in the figure,' deposit polycrystalline or polycrystalline metal / polycrystalline silicon on the substrate 30 'to As the material of the gate, and then depositing SiO 2 (SisN4) or silicon oxynitride (Si ON) 32 on it, as a mask layer, define Open electrode 34, followed by shallow doping, and then gate annealing, to grow an oxide with a thickness of about 100 ~ 200A, or directly deposit an oxide 36 with a thickness of about 100 ~ 300A; (ii) such as As shown in Fig. 2b, silicon nitride 'is deposited on the above oxide 36 and etched back to form a spacer layer 3 8' and source and non-electrode implantation is performed; (iii) Please refer to Fig. 2c, deposition Thick

4 4 10 18

V. Description of the invention (2) '100 ~ 400 A silicon nitride' as a self-aligned contact window etch stop layer iv) Refer to Figure 2d for a month to deposit a thickness of about 1000 ~ 200qa PETE0S 40 and BPTEOS with a thickness of about 3000 ~ 12000 A are used as the inner dielectric material (I LD) 42 and then etched back or chemical mechanical plane is used to form a photoresist layer 44 to define a self-regulating area ( vU see Figure 2e 'to etch the self-aligned contact window and remove the silicon nitride in it; (vi) Please refer to Figure 2f, and finally deposit a tungsten plug (W-plug) 46. As shown, the components using the conventional process have a smaller contact area in the contact window, so the contact resistance is larger, and the etch margin is smaller. In addition, poor self-alignment of the contour of the contact window can cause gaps. Damage to the object prevents it from achieving the barrier function. In order to overcome the problems in the conventional art, the object of the present invention is to provide a structure for etching away the sidewall layer in the self-aligning process, which is provided in the gate. There is only a thin spacer layer on the side wall of the electrode, which can increase the space of the gate. The design specifications can be further reduced. Since the structure of etching the sidewall layer in the self-alignment process of the present invention can increase the contact area of the self-aligned contact window, the contact resistance can be reduced, and the etching margin of the self-aligned contact window can be increased. ^ In order to further clarify the method, architecture, and characteristics of the present invention, the preferred embodiments of the present invention will be described below with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram showing a conventional SRAM memory cell. Figures 2a to 2f This is a side view drawing showing the manufacturing process of the self-aligning contact window in the conventional manufacturing process.

First

Hi V. Description of the invention (3) Figures 3a to 3h are cross-sectional views showing a process of etching away the structure of the sidewall layer in the self-alignment process according to an embodiment of the present invention. 4a to 4h are cross-sectional views illustrating a process of etching away the structure of the sidewall layer in the self-alignment process according to another embodiment of the present invention. Explanation of reference numerals: reinforced NMOS transistors ~ 10, 12, 14, 16; empty NMOS transistors ~ 18, 20; broken substrates ~ 30, 50 '80; photomask layers ~ 32, 52, 82; gate electrodes ~ 34, 54, 84; oxides ~ 36, 56; spacers ~ 38, 58, 96; self-aligned contact window engraved stop layers ~, 60; inner dielectric materials ~ 42, 62, 100; photoresist layers ~ 44, 64, 102; thin dielectric layer ~ 66; thin spacers ~ 68, 110; tungsten plugs ~ 46, 70, 112; gasified stone layer ~ 90; dielectric layer ~ 92; nitride Evening ~ 94; Dielectric layer ~ 96. For description of the embodiment, please refer to FIGS. 3a to 3h. According to an embodiment of the present invention, the process of etching away the structure of the sidewall layer in the self-alignment process includes the following steps: (i) as shown in FIG. 3a On the substrate 50, polycrystalline silicon or polycrystalline metal silicide / polycrystalline silicon is deposited as the material of the gate electrode, and then silicon nitride (Si3N4) or silicon oxynitride (Si⑽) having a thickness of 1,000 to 2500 0 a is deposited thereon. 52, as the mask layer 'define the gate 54' and then do shallow dopant doping, and then perform gate annealing to grow oxides with a thickness of about 100 to 2000, or to deposit An oxide 56 having a thickness of about 100 to 300 Å; (; [1) As shown in FIG. 31;), polycrystalline stone was deposited on the above oxide, and then etched back to form a spacer layer ^, and a source electrode was performed. (Ili) Please refer to the second figure with the drain electrode. The thickness is about 4G0A, which is used as the self-aligned contact window.

Page 7 4410 18 V. Description of the invention quot " Stop layer 60; (ιν) Please refer to Figure 3d, depositing PETEOS with a thickness of about 1000-2000A and BPTEOS with a thickness of about 3000-2000A As the inner dielectric material (ILD) 62, and then use etch back or chemical mechanical polishing to level the surface, and then use the photoresist layer 64 to define the self-aligned area; (v) please refer to Figure 3e, Etch the self-aligned contact window and remove the silicon nitride in it. (Vi) Please refer to Figure 3f. Remove the polycrystalline silicon spacer 58 in the self-aligned contact window. (Vii) Please refer to Figure 3g. A thin dielectric layer 66 is deposited, such as argon fossil or hafnium oxide, and the button is engraved to form a thin spacer 68 on the side wall of the gate; (vii i) Please refer to FIG. 3h, and finally deposit a tungsten plug Plug 70. 'Please refer to FIG. 4a to FIG. 4h' According to another embodiment of the present invention, the process of etching away the structure of the sidewall layer in the self-alignment process includes the following steps: Ci) As shown in FIG. 4a, Polycrystalline silicon or polycrystalline silicon silicide / polycrystalline silicon 'is deposited on the substrate 80 as the material of the gate, and then a silicon nitride (Si3N4) or silicon oxynitride (SiON) of 100 to 250 0 A is deposited thereon. 82, as the mask layer 'defines the gate electrode 84; (ii) as shown in FIG. 4b, a silicon nitride layer is deposited on it 90: (Ui) Please refer to FIG. On the layer 90, a dielectric layer 92, such as an oxide layer (TEOS), is deposited. (Iv) Please refer to FIG. 4d. A composite spacer is formed on the side, and the composite spacer system includes silicon nitride 94 and a dielectric layer 96; (v) Please refer to FIG. 4e, and deposit a thickness of about 1000-2000a ££ 丁 £ 05 and thickness of about 30 00 ~ 1 2000 people 8? 1 £ 03, as the inner dielectric material (ILD) 1 0 0 'and then use the back-etching or chemical mechanical grinding method to make

Page 8 V. Description of the invention (5) Leveling, and then using the photoresist layer 102 to define a self-aligned area · = Figure 4f 'for self-aligned contact window ㈣ y) of the dielectric spacer 96; (vi i) Please refer to the first step to form a liner, such as forming a thin spacer 11 on the nitrided wall. (vii 丄 If and etch back to form tungsten on the closed electrode side. Plug 112. "Refer to Figure 4h for the last month. Finally, use the contact area in the windows of the above two physical architectures of the present invention, such as Figures 3h and 4h, in addition to the empty embodiment to further reduce the component size. The manufacturing method, the obtained indication is that it can increase self-aligned contact, can reduce contact resistance, and also provides time.

$ 9 pages

Claims (1)

441018 VI. Method of applying for a patent, including =: The structure of the sidewall layer is etched away in the self-alignment process. The fabrication of the structure includes the following steps: Domain, depositing interlayer material on the substrate, and then defining the interpolar region. Connected to the electrode = do shallow shallow electrode doping, and then grow the oxide wheel; implantation of the electrode; formation of a spacer layer on both sides of the gate; and source and drain (iij) to form a self-aligned contact window etching stop layer; mechanical research :: Ϊ :: Dielectric material 'Then use etch back or chemical mechanical polishing to flatten the surface, and then define the self-aligned area; For Wei Lian Xiao § ^ Align the ㈣ of the contact window and move In addition to the self-aligned contact * stoppage layer in the rest of the time; (vi) remove the spacers in the self-aligned contact window; (V ii) / products to form a thin dielectric layer, and etch back to the gate sidewalls Formation of thin spacers. 2. The manufacturing method according to item 丨 of the patent application scope, wherein the gate material in the above step (1) is polycrystalline silicon or polycrystalline metal silicide / polycrystalline silicon. 3. The manufacturing method according to item 丨 in the scope of the patent application, wherein the way to define the gate in step (1) above is to deposit 1 200,500 A silicon nitride or oxygen nitrogen on the gate material. Silicone is used as a mask layer. 4. The production method according to item 1 of the scope of patent application, wherein the oxide in the above step (1) is formed by gate annealing, and the thickness is about 100 ~ 200A. The method of claim 1, wherein the oxide in the step (i) may be an oxide having a thickness of about 1,000 to 300 A directly deposited. Page 10 4 410 18 6. Scope of patent application 6. The production method according to item 1 of the scope of patent application, wherein the spacers in the above step (i i) are formed by depositing polycrystalline silicon on the oxide and etching back. 7. The manufacturing method according to item 1 of the scope of patent application, wherein the self-aligned contact window in the above steps (i i i) is formed by depositing a nitride layer with a thickness of about 100-400 A. 8. The manufacturing method according to item 1 of the scope of the patent application, wherein the inner layer dielectric material in the above step (^) is deposited to a thickness of about 10,000 to 2,000 people] 丁 £ 0.00 and a thickness of about 3000 ~ 12000 A of BPTEOS. 9 · A manufacturing method of a structure for etching away a sidewall layer in a self-alignment process' includes the following steps: (i) depositing gate material on a substrate, and then depositing a photomask layer thereon to define the gate electrode ; (Ii) depositing a nitrided layer thereon; (iii) depositing a dielectric layer on the nitrided layer; (1v) etch back the silicon nitride layer and the dielectric layer, thereby Forming composite spacers on both sides of the gate; (v) depositing an inner layer of dielectric material, then flattening the surface, and then using a photoresist layer to define a self-aligned area; (VI) etching the self-aligned contact window, The dielectric layer spacers are removed therefrom; (V 1 1) is deposited thereon to form an inner liner layer, and etched back to form thin spacers on the gate sidewalls. 10. The method for making item 9 in the scope of patent application, wherein the above steps Page 11 6. Scope of Patent Application The gate material in step (i) can be polycrystalline silicon or polycrystalline metal silicide / polycrystalline silicon. 1 1. The manufacturing method according to item 9 of the scope of patent application, wherein the photomask layer in the above step (i) is formed by depositing silicon nitride (S i3 N4) of 100 to 250 people. Formed by oxynitridation (S i 0 N). 1 2. The manufacturing method according to item 9 of the scope of patent application *, wherein the dielectric layer in the step (iii) may be an oxide layer. 13. The manufacturing method according to item 9 of the scope of patent application, wherein the composite spacer system in the above step (i v) includes silicon nitride and a dielectric layer. 14. The manufacturing method according to item 9 of the scope of patent application, wherein the inner dielectric material in the step (v) is made of PETEOS with a thickness of about 1 0 0 0 to 2 0 0 0 A and a thickness of about 3000 to 12 0 0 0 A formed by BPTEOS. 1 5. The manufacturing method according to item 9 of the scope of patent application, wherein the inner lining layer in the step (vii) is silicon nitride. Page 12