TW441004B - Method for forming shallow trench isolation on semiconductor substrate - Google Patents

Abstract

A method for forming a shallow trench isolation (STI) on a semiconductor substrate comprises etching a semiconductor substrate to form a shallow trench on the semiconductor substrate; performing a thermal annealing process to the semiconductor substrate to repair the surface structure of the trench, into which oxygen is introduced to form a silicon oxide film on the surface of the shallow trench; and forming a STI in the shallow trench.

Description

4 4 1 Ο Ο 4 4. Description of the invention (ι) Field of the invention: The present invention relates to a process for forming a shallow trench isolation structure (STI) on a semiconductor substrate, especially a method using thermal tempering. Procedure for repairing lattice defects of shallow trenches to improve the yield of shallow trench isolation structures "BACKGROUND OF THE INVENTION: With the great progress of the semiconductor industry, the development and design of ultra-large integrated circuits (ULS I) _, In order to meet the design trend of high-density integrated circuits, the size of various components has been reduced to sub-micron. In addition, due to the shrinking component size, it has often encountered unprecedented difficulties when carrying out related semiconductor processes, and the complexity of various processes has continued to increase. Among them, due to the miniaturization of the product size, the operating voltage, current, and even the allowable relative resistance of various components have been greatly reduced. Therefore, many of the manufacturing defects that can be tolerated in the traditional technology, for the new generation of operating elements, the impact will often be intangibly magnified, resulting in a serious decline in the yield of the manufactured components. Please refer to the first figure, which shows the steps involved in forming a trench isolation structure on a semiconductor substrate in a conventional process. Among them, an etch mask layer 12 is first defined on the semiconductor substrate 10, and a shallow trench pattern for transferring to the semiconductor substrate 10 is formed on the etch mask layer 12.

IH Page 5 4 41 0 0 4 V. Description of the Invention Next, the semiconductor substrate 10 can be etched by using a dry etching process such as plasma etching technology 4 to form a shallow trench 15 thereon. However, it is worth noting that 'because the plasma etching process often uses high-energy particles to ion bombardment the semiconductor substrate 10. Therefore, when defining a shallow trench pattern, the semiconductor substrate is often caused. The material of the surface of the material 10 causes physical damage, and causes the defined surface of the shallow trench 15 to generate lattice defects such as dislocation, amorphzat ion, and 16 β. After the subsequent fabrication of the isolation structure, defects located on the surface of the shallow trenches 15 and 6 often lead to current leakage of the components defined later, which greatly reduces the yield of the integrated circuit. Purpose and summary of the invention: Shallow trench isolation structure on semiconductor The purpose of the present invention is to provide a method for making Zhao substrates.

The method of the present invention forms the required oxygen cut. A shallow trench isolation junction capable of simultaneously repairing the surface of a shallow trench. A shallow trench isolation structure capable of performing a silicon thin film on a semiconductor substrate.

441004 V. Description of the invention (3) Operation method ^ The present invention provides a method for forming a shallow trench structure on a semiconductor substrate. Among them, a pad oxide layer is first formed on the semiconductor substrate, then a nitride layer is formed on the pad oxide layer, and a shallow trench pattern is defined in the nitride layer and the pad oxide layer using an etching process. Then, using the nitride layer as an etching mask power layer, the semiconductor substrate is etched to form shallow trenches on the semiconductor substrate. Next, a thermal tempering sequence is performed on the semiconductor substrate in order to repair the surface structure of the shallow trench. Among them, the temperature of the semiconductor substrate is first raised to 1000 to 1300 ° C, and the flow rate is about 0, 05-1 (im). Oxygen and nitrogen at a flow rate of about 5-20 (1ηι) to form a first silicon oxide film layer on the surface of the shallow trench. Next, the temperature of the semiconductor substrate is lowered to about 85 (M 0 0 0 t;) while oxygen gas with a flow rate of about 5 20 (lm) is passed in order to form a second silicon oxide film layer on the surface of the first silicon oxide film layer and the shallow trench. Then, a shallow trench isolation structure is formed in the shallow Han trench. Detailed description of the invention: The present invention discloses a method for making a shallow trench isolation structure on a semiconductor substrate. By performing a thermal tempering process, the shallow trench is repaired. Ditch surface: When J is defective, when oxygen is simultaneously introduced, an oxide film can be simultaneously formed on the i 'surface. A detailed description of the present invention is as follows. 凊 Referring to the second figure, first according to a comparative embodiment of the present invention Provide noodles

Page 7 441 004 V. Description of the invention (4) '--Single crystal fragments with &lt; 1GG &gt; crystal orientation as semiconductor substrate 2Q ... In general, other types of semiconductor materials, such as galUum arsenide ), Germanium (germanium), or a broken substrate (sUicon insulator (SOI)) on the insulating layer can be used as the semiconductor substrate in the present invention. In addition, due to the characteristics of the surface of the semiconductor substrate, the present invention does not cause a special influence to the direction a, and it is also possible to select <丨 丨 〇 &gt; or <丨〗 丨 &gt; based on its crystal orientation. Next, a pad oxide layer 22 can be formed on the semiconductor substrate 20 'and a nitride layer 24 can be formed on the pad oxide layer 22'. Among them, the nitrided layer 24 can be used as an etching mask for etching the semiconductor substrate 20 when defining a shallow trench pattern. In addition, this I.G.24 can also be used as an anti-reflection coating (ARC) layer to greatly improve the lithographic resolution of subsequent shallow trench patterns. In a preferred embodiment, 'the nitride layer 24 can be deposited using any suitable process, as is familiar to those skilled in the art'. The nitride layer 24 can be made using low pressure chemical vapor deposition (LPCVD), plasma Enhanced chemical vapor deposition (pECVD) and other processes. Furthermore, the temperature at which the nitride layer 24 is formed is about 400-800 ° C. Moreover, SiH4 'NH3' N2, N2O or SiH2Cl2, NH3, N2, N20 can be selected as a reaction gas used for manufacturing the nitride layer 24. As for the above-mentioned pad oxide layer 22, in addition to being used as an etching mask for defining shallow trenches in subsequent etching processes, and because of its better interface properties with the semiconductor silicon substrate 20, it can be used for subsequent fabrication A buffer layer between the nitrided layer and the semiconductive Zhao Shixi substrate 20. In a preferred embodiment, the pad oxide layer 22 is at a temperature of about 800 to 1100 ° C.

Page 8 441004 V. Description of the invention (5) Oxide stone formed in an environment full of oxygen vapor. Similarly, the pad oxide layer 2 2 can also be formed by a suitable chemical combination and procedure of the oxide. For example, the pad oxide layer 22 may be silicon dioxide formed using a chemical vapor deposition method. The chemical vapor deposition method uses TEOS at a temperature of 600 to 800. (: Formed with a pressure of about 0.1 to 10 Torr. Then, a photoresist layer 26 having a shallow trench pattern can be formed on the nitride layer 24, and the nitride layer 24 and the pad oxide layer 22 can be etched to A shallow trench pattern is defined in the nitride layer 24 and the pad oxide layer 22. In a preferred embodiment, a reactive ion engraving (RIE) process can be used to etch the nitride layer 24 and the hafnium oxide layer 2 described above. 2. Among them, CF4 / H2, CHF3 4CH3CHF2 can be selected as the etching formula for the nitride layer 24, and CC12F2, chf3 / cf4 'chf3 / o2, CH3CHF2, cf4 / o2 can be selected as the etching formula for the oxide layer 22 of the etching pad. Next, referring to the third figure, after the shallow trench pattern is defined on the nitride layer 2 4 and the pad oxide layer 22, the photoresist layer 26 can be removed. The nitride layer 24 and the pad oxide layer 22 are used as etching. The mask is used to etch the semiconductor substrate 20 to form a shallow trench 25 on the semiconductor substrate 20. Generally speaking, the above-mentioned silver etching of the semiconductor substrate 20 can be performed using a dry etching process such as a plasma etching process. For example, in a preferred embodiment, this etching step can utilize non- # tropic reactive ions Lithography process (anisotr〇p ical reactive ion etch, RIE), to name engraved 2〇 for semiconductor substrates, and the selected etch recipe includes SiCl4 / Cl2, BCI3 / Cl2, HBr / Cl2 / 〇2,

004

B r / 02 Br2 / SF6 or SF6. However, it is worth noting that, as described above, when the shallow trench 25 is defined on the semiconductor substrate 20, the plasma etching process used will cause defects such as amorphization and lattice displacement on the surface of the shallow trench 25. . Please refer to the fourth figure. In order to repair the lattice defects on the surface of the shallow trench 25, a high temperature procedure such as thermal annealing is performed on the semiconductor substrate 20. In a preferred embodiment, the semiconductor substrate 'in the batch (10t) can be placed on the wafer boat 38, and the wafer boat 38 can be ioaded to a high-temperature heat by a robot arm. In the reaction chamber 32 of the tempering machine 30. Then, the semiconductor substrate 20 is heated by a heating device 36 located around the reaction chamber 32. In this way, the lattice of the surface of the shallow trench 25 on the semiconductor substrate 20 can be rearranged (recrystaiH-zat ion) through the high-temperature process to achieve the effect of repairing the surface structure of the shallow trench. It is worth noting that ‘general high-temperature thermal tempering procedures’ are often performed in a fully charged environment. However, the introduced nitrogen gas often reacts with the semiconductor bottom village 20, and an unnecessary nitride film (S i XN y) film is formed on the surface of the shallow trench 25. Therefore, in order to avoid the nitride film layer In the present invention, in the high temperature thermal tempering program order, oxygen and nitrogen are simultaneously introduced into the reaction chamber 32 through the input pipe 34 ', and the oxygen is more active than nitrogen to form the reactor. The required silicon oxide film is on the surface of the shallow trench 2 5. That is, in the present invention, the lattice junction on the surface of the shallow trench 25 can be repaired by introducing oxygen into the reaction chamber while performing the thermal tempering process.

Page 10 4 4 1 〇 4 V. Description of the invention (7) When the silicon film structure is formed, the required oxygen is formed simultaneously. Refer to Fifth Seoul, a fJ step. First, increase the above-mentioned thermal tempering procedure, including lower C, while passing in the temperature of the flowing substrate 20 to about] 000 ~ 1300 (") of nitrogen, at a temperature of = 0, 3 °, and oxygen at a flow rate of about 5 When the surface defect is 26, the shallow trench 25 can be effectively repaired. At the same time, a first silicon oxide film layer 42 is formed on the surface of the shallow trench. Then, the temperature of the semiconductor substrate 20 can be reduced to about 85 ° ~ 1000 ′ Simultaneously raise the oxygen flow rate to about 5 ~ 20 (lm), and stop the supply of nitrogen 'after about 3 to 15 minutes' to form the required second oxide film layer 44 to the first silicon oxide The lower surface of the membrane layer 42. In a preferred embodiment, the whole step configuration of the heat recovery sequence can be shown in the first table: Step) Star degree 丨 Oxygen (丨 m) • | 气 气 (1 m) Heating 1 1000 0.5 10 Stable 2 1. ϋ 0 | 0.5 10 Heating 2 i 100 j 0.5 1 10 Stable 3 1 100 0.5 10 Thermal tempering 1 1100 10 Cooling 1 920 10 Stable 4 920 10 Increasing the amount of oxygen 920 10 A table

Page 11 V. Description of the invention (8) Among them, when the high-temperature tempering process is performed on the semiconductor substrate 20, the first process is about 40 minutes, and the temperature of the semiconductor substrate 20 is increased to about C; and the stabilization is performed 2 The program was about 10 minutes to control the temperature and kept constant at about 1 000 aC. At this time ... As mentioned above, the nitrogen gas will directly react with the surface of the semiconducting heterogeneous substrate 20 and oxygen at the same time. Next, the temperature increase 2 procedure is performed for about 40 minutes, so that the temperature of the semiconductor substrate 20 is increased to about 1100t; and the stable ~ procedure is performed? 10 minutes' to control and maintain the temperature at u 〇 t, at this time; the oxygen of 疋 will react with the semiconductor substrate 20, and the second figure = 2 is generated. Then 'restart the thermal recovery for about 1 hour; after the tempering 1 process is completed, the temperature reduction process is then performed for about 90 minutes to reduce the temperature of the semiconductor substrate 20 to about 9 and the process is about 1 〇 Allow the temperature to stabilize for minutes. Then, ask the oxygen flow rate to 10 (m) to form the required second oxide sand layer 44 on the lower surface of the first oxygen cut film. # 此 ， 可以 可以 上 的 Silicon oxide film layer (42, 44). After that, as shown in the sixth figure, the shallow trench isolation structure 46 can be formed in the shallow trench 25 after the nitride layer 24 and the pad oxide layer 22 are removed. In a preferred embodiment, the above-mentioned shallow trench isolation structure 46 may be formed by filling an oxide material into the shallow trench 25 using a chemical vapor deposition (CVD) method. Ancient 5: The method provided by the present invention ′ 纟 makes shallow trench isolation structure, there are many advantages. First, by defining the etch in the shallow trench pattern

Surfaces Page 12 44 彳 004 V. Description of the invention (9) --- Engraving the Queen's semiconductor substrate by thermal tempering procedure can be immediate and effective, repairing lattice defects on shallow and canal surfaces. That is, the defects such as amorphization, lattice displacement, and the like can be removed, and the damaged region of the semiconductor substrate can be re-latticed. In this way, the leakage current at the edge of the shallow trench isolation structure can be more effectively controlled, and the purpose of improving component performance and yield can be achieved. For example, for a logic device process with a line width of 0. ΐδ, the yield rate can be improved by about 15 times. More than half of the method of the present invention ... In the process of thermal tempering to repair the silicon film on the surface of shallow trenches, the purpose is to save time, because the present invention will produce oxygen to achieve temperature-saving repair of semiconductor substrate There are two steps such as the surface of the material, and the film is completed from the south ... In the actual production line, it often equals the cycle time in the process stage. That is to say, under the condition of saving about 50% f, and passing oxygen into the milk, it will be effective to fossil evening film. What's more, access to form the required silicon oxide. In addition, 'because in the high temperature tempering process chamber', the oxygen is more active than nitrogen to prevent the formation of additional nitrogen on the surface of shallow trenches. The substrate reacts with a film. See the second table:

441004 V. Description of the invention (10) Batch 1 2 —. 3 4 5 6 7 8 9 10 11 12 Silica oxide (traditional) 氺 * * Water * 矽 Silica pus (invention) The umbrella * is not heated Tempering * Ben * 5k Hot Tempering * * Yield (%) irTT * · 40.40 44.20 &amp; 1.50 66.30 60.60 62.50 $ 5.80 S4.40 55.80 54.30 Average (¾) ”. 10 62.7 0 5 7.70 Good Car Changes (/ .) 7 2.50 4.50 In the second table, the semiconductor wafers in batches 1 to 4 are formed on the surface of shallow trenches according to the procedures in the conventional technology, and these batches have not been carried out. That is, the repair process of the surface material of the semiconductor substrate has not been performed; ^ The semiconductor wafers in the relative batches 5 to 8 are subjected to a high-temperature thermal tempering sequence using the method provided by the present invention. When the surface material of the wafer is repaired, the required silicon oxide film is formed simultaneously. As for the semiconductor crystal B1 in batches 9 to 12, after the silicon oxide film is formed, the temperature is about U 0 in a nitrogen-filled environment. The heat tempering process at 0 ° c is about 2 hours. It can be known from the second table that only the silicon oxide film is formed, and the batch of wafers that have not been subjected to the thermal tempering process will only have a yield of about 47. 10%; and after the stone oxide film is formed, the thermal recovery is performed. The wafer batch of the fire process will have a lower t

Page 14 4 41 0 0 4 V. Description of the invention (11) The yield is about 5 7.70%. However, it is worth noting that, using the method of the present invention, the wafer batches for simultaneous high temperature tempering and silicon oxide film fabrication will have a yield of 62.70%. And, the change in its yield is also low, only about 2.50%. Relative to 7% of batch Bu 4 and 4.50% of 9 to 12 times, obviously using the method of the present invention to make components, not only can greatly reduce the production time, but also can obtain a more stable and higher yield. Although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the inventive substance of the present invention, but only to this embodiment. Therefore, all modifications made without departing from the spirit and scope of the present invention should be included in the scope of patent application described below.

Schematic illustrations on page 15 Schematic descriptions: With the following detailed description combined with the attached drawings, the above content and the many advantages of this invention can be easily understood, of which: ,, · The first picture is a semiconductor wafer The cross-sectional view 'shows that shallow trenches are formed on a semiconductor substrate according to conventional techniques. The plasma etching used will cause defects in the surface lattice of the shallow trenches. The second figure is a cross-sectional view of a semiconductor wafer, showing the formation of a semiconductor wafer according to the present invention. An oxide layer and a nitride layer on a semiconductor substrate, and a step of defining a shallow trench pattern thereon; η, the first figure is a plan view of a semiconductor wafer, showing the formation of a shallow trench on a semiconductor substrate according to the present invention. Plasma etching caused by lattice defects on the surface of shallow trenches; Figure 4 shows the high temperature range of the semiconductor wafer = placement surface diagram 'can repair defects in shallow trenches according to the method of the invention · 1 day after day The grid shows that according to the present invention, a semi-silicon film layer can be formed. The fifth picture is a cross-sectional view of a semiconductor wafer. The conductor substrate is subjected to a high-temperature process containing oxygen. On the surface of the shallow trench; and FIG. 4 does not form the two U-M + pairs according to the present invention. The required isolation structure is shown in FIG. 6. The chemical vapor deposition method is performed on the surface of the conductor substrate of the semiconductor wafer. In.

Claims (1)

6. Scope of Patent Application 1. A method for forming a shallow trench isolation (STI) structure on a semiconductor substrate, the method includes at least the following steps: engraving a semiconductor substrate to form a shallow trench on the semiconductor substrate Performing a thermal tempering procedure on the semiconductor substrate to repair the surface structure of the shallow trench, wherein oxygen is passed in to form a silicon oxide film on the surface of the shallow trench; and a shallow trench isolation structure is formed in the shallow trench. For example, the method of claiming a patent scope item 1, before etching the conductor substrate, further includes the following steps: forming a pad oxide layer on the semiconductor substrate; forming a nitride layer on the pad oxide layer; The gasification layer and the pad oxide layer 'define a shallow trench pattern in the hafnium layer and the pad oxide layer. Λ, 3. The method according to item 2 of the scope of patent application, wherein the nitrided layer can be used as an etching mask for the semiconductor substrate. 4. The method according to item 1 of the scope of patent application, wherein the above-mentioned sequence of etching the semiconductor substrate is completed using a plasma etching process. 5. If the method of the scope of patent application is No. 4, its plasma etching process will cause lattice defects on the surface of the shallow trenches. Page 17 441 〇〇4. Patent application scope 6. The method of applying for the patent scope item 1 'where the above-mentioned thermal tempering procedure' includes at least the following steps: Raise the temperature of the semiconductor substrate to about 1000 ~ 1300 ° C 'At the same time, the oxygen of about 0'05 ~ i (im) and the nitrogen of about 5 ~ 20 (lm) are flown at the same time' in order to form a first oxide film layer on the surface of the shallow trench; and lower the semiconductor The temperature of the substrate is about 850 ~ 1000 ° C. At the same time, oxygen gas with a flow rate of about 5 ~ 20 (100) is introduced to form a second silicon oxide film layer on the lower surface of the first silicon oxide film layer. 7. The method of claim 1 in which the aforementioned shallow trench isolation structure is formed using a chemical vapor deposition method. 8. A method of forming a shallow trench isolation (STI) structure on a semiconductor substrate 'The method includes at least the following steps: etching a semiconductor substrate to form a shallow trench on the semiconductor substrate; and performing a first high temperature on the semiconductor substrate A procedure to repair the surface structure of the semiconductor substrate, in which oxygen and nitrogen are simultaneously input to form a first silicon oxide film on the surface of the shallow trench; a second high temperature procedure is performed on the semiconductor substrate, in which the supply of nitrogen is stopped, A second silicon oxide film is formed under the first silicon oxide film; and a shallow trench isolation structure is formed in the shallow trench. 4 41 0 04 VI. Patent Application ® 9. If the method of claim 8 is applied, before etching the conductor substrate, the method further includes the following steps: forming a pad oxide layer on the semiconductor substrate; forming nitride Layer on the pad oxide layer; and etching the nitride layer and the pad oxide layer to define a shallow trench pattern in the nitride layer and the pad oxide layer. 10. If the method according to item 9 of the patent application is applied, the nitrided layer can be used as an etching mask for etching the semiconductor substrate. 11. The method according to item 8 of the patent application, wherein the above-mentioned process for etching the semiconductor substrate is performed using a plasma etching process. 12. For the method according to item 11 of the scope of patent application, wherein the plasma etching process described above will cause lattice defects on the surface of the shallow trenches produced. 13. The method according to item 8 of the scope of patent application, wherein the temperature of the first high-temperature program is about 1 0 0 to 1 3 0 ° C, and the flow rate of oxygen is about 0.05 to 1 (lm), and the flow rate of nitrogen is The flow rate is about 5 ~ 20 (lm). 14. For the method of claim 8 in the scope of patent application, wherein the temperature of the above-mentioned second high temperature program is about 850 to 100 ° C, and the flow rate of the oxygen gas is about 5 to 20 (1 m) ° Page 19 441 004 6. Scope of patent application 15. The method according to item 8 of the scope of patent application, wherein the above-mentioned shallow trench isolation structure is formed using a chemical vapor deposition method. Page 20