經濟部智慧財產局員工消費合作社印製 1 0 2 4 A7 B7五'發明説明（） 發明領城： 本發明與一種形成超淺接面（ultra sha丨丨ow juncti〇n; US J)於半導體底材上之半導體製程有關，特別是一種在進行 快速熱回火程序（raPid thermal Process; RTP)以活化 (activate)超淺接面（US〗）之前，形成氮化材料作爲其蓋層 (cap layer)之方法。 發明皆署： 隨著半導體工業持續發展至線寬維度爲0.13〜0.15 y m 之相關製程時，在超大型積體電路（ULSI)的製造與設計中， 爲了符合高構裝密度晶圓之設計趨勢’各式元件之尺寸皆不 斷降低。並且，由於元件不斷的縮小，導致在進行相關半導 體製程時，也遭遇前所未有之困難。更者，所發展之製程， 其複雜程度亦不斷提高。其中，對於在半導體製程中常見之 離子植入程序而言，由於所需摻雜區域之誤差容忍度 (margin)，隨著元件尺寸的縮小而降低，是以在目前業界中 已廣泛使用低能量且高劑量之離子植入技術，以期在有效控 制摻雜區域之摻雜濃度與深度條件下，形成深度在450埃以 下，且電阻値在400(歐姆/平方英吋）內之超淺接面（ultra shallow junction; USJ)。如此，以便能符合半導體元件越趨 密集之設計要求》 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS).A4規格（ 210X297公釐） 經濟部智慧財產局員工消費合作社印製 461024 A7 _________ B7 五、發明説明（） —般而言’相較於不易精確控制之離子擴散（ion diffusion)法’離子植入法由於可藉著控制離子束電流量與 所施加之電壓，有效的決定摻雜濃度與深度，並精確的掌握 摻質在半導體晶圓中分佈情況。是以，在超淺接面（USj)的 相關製程中被廣泛的使用。並且，藉著決定摻質種類、濃度、 深度，可以有效的在半導體晶圓中，形成所需之各式元件。 在目前的ULSI相關製程中，常用之摻質源包括固態的磷及 砷，此外氣態的氫化砷（AsH3，Arsi.ne)，.氫化磷（PH3_， Phosphine)..，三氣化硼（BF3，Boron Trifluori.de)等等，亦被 用以作爲製作η型矽材料與p型矽材料所需之摻質來源。 請參照第一圖，該圖所顯示即爲應用離子植入法於金氧 半場效電晶體製程之一會意圖。其中，在所提供之半導體底 2上，首先形成了由導體材料所組成之閘極結構4，並且在 閘極結構4與半導體底材2之間，並形成閘極氧化層6以便 產生絕緣作用。另外，可在閘極結構4之側壁上，分別形成 側壁間隙壁（spacer)8。隨後，則可使用上述之離子植入程 序，在鄰接閘極結構4兩側之半導體底材2中，分別形成所 需之摻雜區域1 0，以作爲整個電晶體結構之源極與汲極使 用。 値得注意的是在進行離子植入程序後，往往需再對半導 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐) ---------^ 裝----丨—訂--------C /____- · / I (請先閱讀背面之注意事項再填寫本頁) 461024 A7 B7 五、發明説明（） 體底材2進行溫度約爲800至1 000 °C之熱回火（thermal annealing)程序，以有效活化（activate)所植入之摻質，並使 其發生導電作用。此外，所進行之熱回火程序，亦可用來修 復在進行離子植入程序時，對半導體底材2矽結構所造成之 破壞，而使排列順次錯亂之結晶矽，恢復其原來的結晶狀 態。但是要特別說明的是，在進行熱回火程序時，位於摻雜 區內之摻質，往往會產生擴散作用（diffusion)，而使摻雜區 域之分佈輪廓（profile)受到影響。 但是如同上述，由於半導體元件之尺寸日趨縮小，是以 在對摻雜區域中之摻質進行活化程序時，往往會導致摻質擴 散至其它元件中，從而導致整個積體電路之性質受到影響。 爲了克服此項問題，且最佳化所形成之超淺接面，使其具有 較低片電阻値，在傳統製程中往往在超淺接面上，形成厚度 約數十埃之氧化層以作爲蓋層（cap layer)，用以防止在進行 熱回火程序時，摻質產生外擴散效應，而滲入其它元件。 ϋ - —i In ———— — — I m ϋ n m 1— T ...、-* (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 値得注意的是在傳統製程中，使用快速熱回火程序 (rapid thermal procedure; RTP)或是爐.管（furnace).’ 製造作 爲蓋層之氧化層其溫度，往往高達800至900°C左右。是以 很容易造成位於摻雜區域中之摻質’產生擴散作用’從而造 成摻擁區域之輪廓產生改變’並造成所形成超淺接面具有極 不確定之電阻値與深度。甚至於造成鄰接摻雜區域之其它元 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 線 β 4 102 4 A7 ___ B7五、發明説明（） 經濟部智慧財產局員工消費合作社印製 件，導電性質發生改變。 發昍日的及槪沭： 本發明之目的爲一種可防止半導體底材中之摻質，在 零件製程中產生擴散之方法，用以避免因爲摻質擴散，而導 致半導體元件之性質受到影響。 本發明之再目的爲一種可有效防止超淺接面（USJ)中 摻質產生擴散效應之製造超淺接面的方法。 本發明之又一目的爲一種使用遠距電漿源（remote plasma source; RPS)形成氮化材料層於超淺接面上，以避免 超淺接面中摻質產生外擴散之方法。 本發明提供了 一種形成超淺接面（USJ)於半導體底材 上之方法。其中，首先對半導體底材進行濕式蝕刻程序，以 移除位於半導體底材表面之天然氧化層。接著，對半導體底 材進行離子植入程序，以形成作爲超淺接面之摻雜區域於半 導體底材中。然後，通入氣體至第一反應室中，並對其進行 電漿化程序，以產生高度活化之原子團或原子。再將所產生 之原子團導入第二反應室中。同時，半導體底材被置放於第 二反應室中，且加熱至溫度約350至500 °C。如此，將可形 (請先閱讀背面之注意事項再填寫本頁) •裝. 訂 ,.w 本紙浪尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 6 4 經濟部智慧財產局員工消費合作社印製 __________五、發明説明（） 成氮化材料層於半導體底材上，且覆蓋於超淺接面上以作爲 蓋層（cap layer)。接著，再對半導體底材進行快速熱回火程 序（RTP)，以活化位於超淺接面中之摻質，其中上述氮化材 料層可用以防止位於超淺接面中之摻質，產生外擴散效應。 値得注意的是藉著控制通入第一反應室中之氣體，可 以控制所形成之氮化材料層。其中，可先通入氧氣以形成氧 化物（RPO)於半導體底材上，接著停止供給氧氣，而以氮氣 通入，以形成氮化物（RPN)於上述RPO層之上；或著，也可 以在持續供給氧氣的情形下，提供氮氣至第一反應室中，以 生成氮化氧化物（RPNO)於上述RPO層上。另外，也可直接 形成RPNO層於半導體底材上；或是僅通入氮氣，以形成 RPN層於半導體底材上。 圖式簡罝說明： 藉由以下詳細之描述結合所附圖示，將可輕易的了解 上述內容及此項發明之諸多優點，其中： 第一圖爲半導體晶片之截面圖，顯示根據傳統技術形 成金氧半場效電晶體於半導體底材上之步驟； 第二圖爲半導體晶片之截面圖，顯示根據本發明形成 摻雜區域其蓋層於半導體底材上之步驟； 第三圖爲遠距電漿源裝置之截面圖，顯示根據本發明 (請先閲讀背面之注意事項再填寫本頁) 、--- •I—訂 .ILV/.W— 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 6 4 102 4 ΑΊ Β7 五、發明説明（） 經濟部智慧財產局員工消費合作社印製 使用遠距電漿源裝置，形成氮化材料層於半導體底材上之步 驟；及 第四圖爲半導體晶片之截面圖，顯示利用本發明所提 供之方法於金氧半場效電晶體製程中之步驟。 發明詳細說明： 本發明所揭示爲一種形成超淺接面（usj)於半導體底 材中之方法。其中藉著使用遠距電漿源方法，形成蓋層於半 導體底材上’且覆蓋於超淺接面之上，可有效避免在進行活 化超淺接面中摻質之熱回火程序中，摻質產生外擴散而影響 週圍其它元件之性質。有關本發明之詳細說明如下所述。 請參照第二圖，根據本發明所提供之實施例，首先提 供一具<100>晶向之單晶矽作爲半導體底材12。一般而言， 其它種類之半導體材料，諸如砷化鎵（gallium arsenide)、鍺 (germanium)或是位於絕緣層上之矽底材（suicon on insulator，SOI)皆可作爲半導體底材使用。另外，由於半導 體底材表面的特性對本發明而言，並不會造成特別的影晌， 是以其晶向亦可選擇<110>或<111>。. 接著可對半導體底材12進行離子植入（ion implant)程 序，以形成超淺接面（ultra shallow junction; USJ)14於半導 (請先閲讀背面之注意事項再填寫本頁) '.^衣 訂 . 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公潑） _____ B7___ 五、發明説明（) (請先閱讀背面之注意事項再填寫本頁) 體底材12中。在較佳之具體實施例中，可藉著使用低能量 及高劑量之離子植入進行此步驟，如此，則所形成之摻雜區 域會具有淺接面結構。在該步驟中，所使用之劑量及離子植 能量分別爲 5E15 至 1E12 atoms/cm2、200eV 至 5 KeV，且 最佳的能量約爲2 KeV左右。 値得注意的是，由於半導體底材12在室溫的環境中， 極容易在其表面上，形成一天然氧_化層（native silicon oxide layer)。是以在進行上述離子植入程序之前，往往可先對半 導體底材12進行一濕式蝕刻（wet etching)程序，以便移除 位於半導體底材12表面之天然氧化層（native, ox i.d e layer)。在一較佳實施例中，可將半導體底材12置於HF水 溶液中，以進行濕蝕刻程序。 經濟部智慧財產局員工消費合作社印製 在進行離子植入程序後，接著形成氮化材料層16於 半導體底材12上，且覆蓋於超淺接面14上，以作爲超淺接 面14之蓋層（〇3?1^^)。其中，値得注意的是此氮化材料 層14是使用.遠距電漿源（remote plasma so.urce; RPS)程序_， 在溫度S 500°C的環境中所形成。在一較佳實施例中，此氮 化材料層1 6可選擇氮化物、氮氧化物或其任意組合。亦即， 所形成之氮化材料層16，可選擇遠距電漿氮化物（remote plasma nitride; RPN)，或是遠距電漿氮化氧化物（remote plasma nitrided oxide; RPNO)。 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 6 4 1 0 24 A7. ______ B7五、發明説明（) 經濟部智慧財產局員工消費合作社印製 請參照第三圖，該圖所顯示即爲本發明中’用來形成 氮化材料層16之裝置。其中用以製造電漿之第一反應室 20，經由一連接管22，連接於用來進行沉積氮化材料層16 之第二反應室24。此第一反應室20 ’並具有一入射口 (inlet)26，用以輸入反應氣體。在本發明中，輸入第一反應 室20中之氣體，主要爲N2與02。另外，在第一反應室20 中，並提供約1 500至3000 Watt之微波28，以激發並解離 通入之氣體，使其形成包括原子團（radical)或原子之電漿 物，再經由上述連接管22,通入第二反應室24之中。至於 半導體底材12則被放置於第二反應室24中之加熱極板30 上，且藉著控制加熱極板30，而使半導體底材12之溫度， 維持在約350至500°C的溫度下。如此一來，所通入之原子 團等電漿物，將會在半導體底材12上，形成所需之氮化材 料層16。在一較佳實施例中，第二反應室24之壓力，維持 在0.1至10 Torr之間。 一般而胃，當通入第一反應室20之氣體爲氮氣時， 則可在半導體底材12上形成遠距電漿氮化物（remote plasma nitride; RPN)，以作爲所需之氮化材料層1 6。或著， 可同時通入氮氣與氧氣，以便於在半導體底材12上，生成 所需之遠距電獎氮化氧化物（remote plasma nitrided ox.ide; RPNO)，來構成氮化材料層16。其中，在較佳的實施例中， (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 461024 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 通入第一反應室20之氮氣與氧氣其流速爲0.5至5 slm(standard liter per minute)。並且所形成氮化材料層16 之厚度約爲40至90埃。 此外’也可先通入氧氣至第一反應室20中，以便在 半導體底材12上，形成遠距電漿氧化物（rem〇te plasma oxide; RP0);接著，停止輸入氧氣，而改以氮氣通入第一反 應室20中，以便在所形成之RP0薄膜上，再形成遠距電漿 氮化物（RPN)。如此，可在半導體底材1 2上形成由RP0與 RPN所構成之複合膜層，以作爲上述氮化材料層1 6。同理， 也可先通入氧氣，而形成RP0層於半導體底材12上，接著 再通入氮氣，以形成RPN0層於上述RP0層上。如此形成 由RP0與RPN0所構成之複合膜層，而作爲氮化材料層16。 接著，可對半導體底材12進行熱回火（thermal annealing)程序，以活化位於超淺接面14中之摻質，其中上 述氮化材料層16可用以防止位於超淺接面14中之摻質，產 生外擴散效應（out diffusion effect)。在一較佳實施例中， 此熱回火程序所進行時間約爲5至20秒，而溫度約950至 1100°C。其中，加熱速率約爲50°C/sec至25(TC/seC。如此 一來，除了可有效活化位於超淺接面14中之摻質，而使其 產生導電作用外，更可修復在進行離子植入程序時，對半導 體底材12所造成之傷害。 — 裝 訂f . / L, (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 46 102 4 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 請參照第四圖，該圖所顯示爲使用本發明所提供形成 超淺接面（USJ)方法，應用於金屬半場效電晶體製程中之實 施例。其中，..如同上述，首先提供一半導體底材42。接著’ 可依序在半導體底材42上，形成閛極氧化層46與閘極結 構44。在一較佳實施例中，可依序形成氧化層與導電層於 半導體底材42上，再使用相關的微影製程技術，而定義出 閘極氧化層46與閘極結構44。一般而言，此氧化層是在溫 度約800至1100°C充滿氧氣的環境中形成，且氧化層之厚 度大約爲1 5-250埃。此外，該氧化層亦可以其它合適氧化 物之化學組合及程序來形成，例如化學氣相沈積法。至於 用來定義閘極結構44之導電層，則可藉由熟知技術，如物 理氣相沈積法（PVD)、濺鍍法等類似製程在氧化層上沈積而 得。並且，此導電層之材料可以爲鋁、鈦、鎢、銅、金、 鈾' 合金或多晶矽等等。 接著，可形成側壁間隙壁48於閘極結構44之側壁上。 一般而言，可藉著先形成一介電層於半導體底材42上，且 覆蓋於聞極結構44上，再對所形成介電層進行非均向性蝕 刻，而形成側壁間隙壁48於閘極結構44側壁上。在較佳實 施例中，可使用氮化较來作爲上述介電層之材料。其中，氮 化矽層可使用任何適當之製程進行沈積，如同熟悉項技術者 所熟知’可以使用低壓化學氣相沈積法（LPCVD)，電漿增強 (請先閱讀背面之注意事項再填寫本頁) I------------{:裝----Printed by the Consumers 'Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 0 2 4 A7 B7 Five' Invention Description () Leading City of the Invention: The present invention forms a super shallow interface with ultra sha 丨 丨 ow juncti〇n; US J The semiconductor process on the substrate is related, in particular, a nitride material is formed as a cap layer (raPid thermal process; RTP) before activating the ultra shallow junction (US). layer). All inventions are signed: As the semiconductor industry continues to develop to the relevant process with a line width dimension of 0.13 to 0.15 ym, in the manufacturing and design of ultra large integrated circuit (ULSI), in order to meet the design trend of high-density wafers 'The size of various components is continuously reduced. In addition, due to the continuous shrinking of components, it has encountered unprecedented difficulties in carrying out related semiconductor system processes. What's more, the complexity of the processes being developed is increasing. Among them, for ion implantation procedures commonly used in semiconductor manufacturing processes, because of the error margin of the required doped region, the reduction in component size decreases with the shrinking of the element size, so low energy has been widely used in the current industry. And high-dose ion implantation technology, with a view to effectively controlling the doping concentration and depth of the doped region, to form an ultra shallow junction with a depth below 450 angstroms and a resistance 値 within 400 (ohm / square inch) (Ultra shallow junction; USJ). In this way, in order to meet the design requirements of increasingly dense semiconductor components "(Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) .A4 specifications (210X297 mm) Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee consumer cooperative 461024 A7 _________ B7 V. Description of the invention ()-In general, 'compared to the ion diffusion method which is not easy to control accurately' The ion implantation method can control the amount of ion beam current and The applied voltage effectively determines the doping concentration and depth, and accurately grasps the dopant distribution in the semiconductor wafer. Therefore, it is widely used in the related process of ultra shallow junction (USj). In addition, by determining the type, concentration, and depth of dopants, various types of components can be effectively formed in a semiconductor wafer. In the current ULSI related processes, commonly used dopant sources include solid phosphorus and arsenic, in addition to gaseous arsenic hydride (AsH3, Arsi.ne), phosphorus hydride (PH3_, Phosphine), and boron trioxide (BF3 , Boron Trifluori.de), etc., have also been used as a source of dopants required to make η-type silicon materials and p-type silicon materials. Please refer to the first figure, which shows one of the intentions of applying ion implantation to the metal-oxygen half field effect transistor process. Among them, on the semiconductor substrate 2 provided, a gate structure 4 composed of a conductive material is first formed, and a gate oxide layer 6 is formed between the gate structure 4 and the semiconductor substrate 2 so as to generate an insulation effect. . In addition, sidewall spacers 8 may be formed on the sidewalls of the gate structure 4, respectively. Subsequently, the above-mentioned ion implantation procedure can be used to form the required doped regions 10 in the semiconductor substrate 2 adjacent to both sides of the gate structure 4 as the source and drain of the entire transistor structure. use. It should be noted that after performing the ion implantation procedure, it is often necessary to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) to the paper size of the semiconductor. --------- ^ Pack- --- 丨 —Order -------- C / ____- · / I (Please read the notes on the back before filling this page) 461024 A7 B7 V. Description of the invention () The temperature of the body substrate 2 is about A thermal annealing process at 800 to 1 000 ° C to effectively activate the implanted dopants and make them conductive. In addition, the thermal tempering procedure performed can also be used to repair the damage to the silicon structure of the semiconductor substrate 2 during the ion implantation procedure, so that the crystalline silicon that is sequentially disordered and restored to its original crystalline state. However, it should be particularly noted that, during the thermal tempering process, dopants located in the doped region often have a diffusion effect, which affects the profile of the doped region. However, as mentioned above, due to the shrinking of the size of semiconductor devices, doping the dopants in the doped region will often cause the dopants to diffuse into other devices, which will affect the properties of the integrated circuit. In order to overcome this problem, and to optimize the formation of the super shallow junction to have a lower sheet resistance, in the traditional process, an oxide layer with a thickness of about several tens of angstroms is often used as A cap layer is used to prevent the dopant from generating an external diffusion effect and infiltrating other components during the thermal tempering process. ϋ-—i In ———— — — I m ϋ nm 1— T ...,-* (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs In the traditional process, a rapid thermal procedure (RTP) or furnace. Tube (furnace) is used to manufacture the oxide layer as the cover layer, and its temperature is often as high as 800 to 900 ° C. Therefore, it is easy to cause the dopant 'diffusion effect' located in the doped region to change the profile of the doped region and cause the ultra-shallow junction to have extremely uncertain resistance and depth. Even the other paper sizes that cause adjacent doped areas are subject to the Chinese National Standard (CNS) A4 (210X297 mm) line β 4 102 4 A7 ___ B7 V. Description of the invention () Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs For parts, the conductive properties are changed. Development date and time: The purpose of the present invention is to prevent the dopants in the semiconductor substrate and generate diffusion during the part manufacturing process, so as to avoid the influence of the dopant diffusion on the properties of the semiconductor device. A further object of the present invention is a method for manufacturing an ultra shallow junction which can effectively prevent the diffusion effect of the dopant in the ultra shallow junction (USJ). Another object of the present invention is a method for forming a nitrided material layer on an ultra-shallow junction using a remote plasma source (RPS) to avoid external diffusion of dopants in the ultra-shallow junction. The invention provides a method for forming an ultra shallow junction (USJ) on a semiconductor substrate. First, a wet etching process is performed on the semiconductor substrate to remove the natural oxide layer on the surface of the semiconductor substrate. Next, an ion implantation process is performed on the semiconductor substrate to form a doped region as an ultra shallow junction in the semiconductor substrate. Then, a gas is introduced into the first reaction chamber, and a plasma process is performed to generate a highly activated atomic group or atom. The generated radicals are then introduced into a second reaction chamber. At the same time, the semiconductor substrate is placed in a second reaction chamber and heated to a temperature of about 350 to 500 ° C. In this way, it will be tangible (please read the precautions on the back before filling out this page) • Binding, ordering, .w This paper wave scale applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 6 4 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the consumer cooperatives __________ 5. Description of the invention () A layer of nitride material is formed on the semiconductor substrate, and it is covered on the super shallow junction surface as a cap layer. Next, a rapid thermal tempering process (RTP) is performed on the semiconductor substrate to activate the dopants located in the super shallow junction. The nitrided material layer can be used to prevent the dopants located in the super shallow junction from generating external materials. Diffusion effect. It should be noted that by controlling the gas that is passed into the first reaction chamber, the nitrided material layer formed can be controlled. Among them, oxygen may be firstly passed in to form an oxide (RPO) on the semiconductor substrate, then the supply of oxygen is stopped, and nitrogen is passed in to form a nitride (RPN) on the RPO layer; or, In the case of continuously supplying oxygen, nitrogen is provided to the first reaction chamber to generate a nitride oxide (RPNO) on the RPO layer. In addition, the RPNO layer can also be formed directly on the semiconductor substrate; or just by passing in nitrogen to form the RPN layer on the semiconductor substrate. Brief description of the drawings: The above content and the many advantages of this invention can be easily understood through the following detailed description combined with the attached drawings, of which: The first figure is a cross-sectional view of a semiconductor wafer, showing the formation according to traditional technology The step of a metal oxide half field effect transistor on a semiconductor substrate; the second figure is a cross-sectional view of a semiconductor wafer, showing the step of forming a doped region with a capping layer on the semiconductor substrate according to the present invention; the third figure is a long-distance electricity A cross-sectional view of a pulp source device, according to the present invention (please read the precautions on the back before filling this page), --- • I—Order.ILV / .W— This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm) 6 4 102 4 ΑΊ Β7 V. Description of the invention () The steps of printing and using a remote plasma source device by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to form a nitride material layer on a semiconductor substrate; and The fourth figure is a cross-sectional view of a semiconductor wafer, showing the steps in the process of the metal-oxygen half field effect transistor using the method provided by the present invention. Detailed description of the invention: The present invention discloses a method for forming an ultra shallow junction (usj) in a semiconductor substrate. Among them, by using the remote plasma source method, a cap layer is formed on the semiconductor substrate and covered on the super shallow junction, which can effectively avoid the thermal tempering process of doping in the activated ultra shallow junction. Dopants produce external diffusion that affects the properties of other surrounding components. A detailed description of the present invention is as follows. Referring to the second figure, according to the embodiment provided by the present invention, a single crystal silicon with < 100 > crystal orientation is first provided as the semiconductor substrate 12. Generally speaking, other types of semiconductor materials, such as gallium arsenide, germanium, or a suicon on insulator (SOI) on an insulating layer, can be used as the semiconductor substrate. In addition, since the characteristics of the surface of the semiconductor substrate do not cause special effects to the present invention, the crystal orientation can also be selected as < 110 > or < 111 >. Then, an ion implantation procedure can be performed on the semiconductor substrate 12 to form an ultra shallow junction (USJ) 14 on the semiconductor (please read the precautions on the back before filling this page). ^ Clothing. This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297). _____ B7___ 5. Description of the invention () (Please read the precautions on the back before filling this page) in the body substrate 12. In a preferred embodiment, this step can be performed by using low-energy and high-dose ion implantation. In this way, the doped region formed will have a shallow junction structure. In this step, the dose and ion implantation energy used are 5E15 to 1E12 atoms / cm2, 200eV to 5 KeV, and the optimal energy is about 2 KeV. It should be noted that, since the semiconductor substrate 12 is at room temperature, it is very easy to form a native silicon oxide layer on its surface. Therefore, before performing the above-mentioned ion implantation process, a wet etching process is often performed on the semiconductor substrate 12 in order to remove the native, ox id e layer on the surface of the semiconductor substrate 12. ). In a preferred embodiment, the semiconductor substrate 12 may be placed in an aqueous HF solution to perform a wet etching process. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, after the ion implantation process, a nitride material layer 16 is formed on the semiconductor substrate 12 and covered on the super shallow junction 14 as the super shallow junction 14 Cap layer (〇3? 1 ^^). It should be noted that the nitrided material layer 14 is formed using a remote plasma source (remote plasma so.urce; RPS) program in an environment with a temperature of S 500 ° C. In a preferred embodiment, the nitride material layer 16 can be selected from nitride, oxynitride, or any combination thereof. That is, the formed nitrided material layer 16 can be selected from remote plasma nitride (RPN) or remote plasma nitrided oxide (RPNO). This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 6 4 1 0 24 A7. ______ B7 V. Description of Invention () Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economics Please refer to the third figure, The figure shows the device used to form the nitride material layer 16 in the present invention. The first reaction chamber 20 for manufacturing the plasma is connected to the second reaction chamber 24 for depositing the nitrided material layer 16 through a connecting pipe 22. The first reaction chamber 20 'also has an inlet 26 for inputting a reaction gas. In the present invention, the gases input into the first reaction chamber 20 are mainly N2 and O2. In addition, in the first reaction chamber 20, a microwave 28 of about 1,500 to 3000 Watt is provided to excite and dissociate the introduced gas to form a plasma including an atomic group (radical) or an atom, and then through the above connection The tube 22 opens into the second reaction chamber 24. The semiconductor substrate 12 is placed on the heating plate 30 in the second reaction chamber 24, and the temperature of the semiconductor substrate 12 is maintained at a temperature of about 350 to 500 ° C by controlling the heating plate 30. under. In this way, the plasma material such as the atomic radicals passed in will form the required nitrided material layer 16 on the semiconductor substrate 12. In a preferred embodiment, the pressure in the second reaction chamber 24 is maintained between 0.1 and 10 Torr. Generally, when the gas that is passed into the first reaction chamber 20 is nitrogen, a remote plasma nitride (RPN) can be formed on the semiconductor substrate 12 as the required nitride material layer. 1 6. Alternatively, nitrogen and oxygen may be introduced at the same time, so as to generate the required remote plasma nitrided ox.ide (RPNO) on the semiconductor substrate 12 to form the nitride material layer 16 . Among them, in a preferred embodiment, (please read the notes on the back before filling this page) This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 461024 A7 B7 Intellectual Property Bureau of the Ministry of Economic Affairs employee consumption Printed by the cooperative V. Description of the invention () The flow rate of nitrogen and oxygen flowing into the first reaction chamber 20 is 0.5 to 5 slm (standard liter per minute). The thickness of the nitrided material layer 16 is about 40 to 90 angstroms. In addition, it is also possible to first introduce oxygen into the first reaction chamber 20 so as to form a remote plasma oxide (RP0) on the semiconductor substrate 12; then, stop inputting oxygen and change to Nitrogen gas is introduced into the first reaction chamber 20 to form a remote plasma nitride (RPN) on the formed RPO film. In this way, a composite film layer composed of RP0 and RPN can be formed on the semiconductor substrate 12 as the above-mentioned nitride material layer 16. Similarly, the RPO layer may be formed on the semiconductor substrate 12 by supplying oxygen first, and then the NPO layer may be formed on the RP0 layer by introducing nitrogen. In this way, a composite film layer composed of RP0 and RPN0 is formed as the nitride material layer 16. Next, a thermal annealing process may be performed on the semiconductor substrate 12 to activate the dopants located in the super shallow junction 14, wherein the nitride material layer 16 may be used to prevent the dopants located in the super shallow junction 14. Quality, producing an out diffusion effect. In a preferred embodiment, the thermal tempering process takes about 5 to 20 seconds and the temperature is about 950 to 1100 ° C. Among them, the heating rate is about 50 ° C / sec to 25 ° C / seC. In this way, in addition to effectively activating the dopants in the ultra-shallow junction 14 to make it conductive, it can also be repaired in progress. Damage caused to the semiconductor substrate 12 during ion implantation procedure. — Binding f. / L, (Please read the precautions on the back before filling this page) This paper size applies Chinese National Standard (CNS) A4 specification (210X297 (Mm) 46 102 4 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Please refer to the fourth figure, which shows the method of forming an ultra shallow junction (USJ) provided by the present invention. An embodiment applied to a metal half field effect transistor manufacturing process. As described above, a semiconductor substrate 42 is first provided. Then, a semiconductor oxide layer 46 and a gate structure can be sequentially formed on the semiconductor substrate 42. 44. In a preferred embodiment, an oxide layer and a conductive layer can be sequentially formed on the semiconductor substrate 42, and then the relevant lithography process technology is used to define the gate oxide layer 46 and the gate structure 44. Generally In terms of this oxide layer is The temperature is about 800 to 1100 ° C. It is formed in an oxygen-filled environment, and the thickness of the oxide layer is about 1 to 250 Angstroms. In addition, the oxide layer can also be formed by other suitable oxide chemical combinations and procedures, such as chemical vapor phase. Deposition method. As for the conductive layer used to define the gate structure 44, it can be deposited on the oxide layer by well-known techniques, such as physical vapor deposition (PVD), sputtering, and the like. The material of the layer may be aluminum, titanium, tungsten, copper, gold, uranium 'alloy, polycrystalline silicon, etc. Next, a sidewall spacer 48 may be formed on the sidewall of the gate structure 44. Generally, a first A dielectric layer is on the semiconductor substrate 42 and covers the electrode structure 44. Then, the formed dielectric layer is anisotropically etched to form a sidewall spacer 48 on the sidewall of the gate structure 44. In the embodiment, the nitride layer may be used as the material of the above-mentioned dielectric layer. The silicon nitride layer may be deposited using any suitable process, as is well known to those skilled in the art, 'low pressure chemical vapor deposition may be used ( (LPCVD) Plasma-enhanced (Please read the Notes on the back to fill out this page) I ------------ {: loading ----
、1T 本紙張尺度適用中國國家標準（.CNS ) A4規格（210X297公釐） 461024 A7 B7 五、發明説明() 化學氣相沈積法（PECVD)等製程進行沈積而得。更者，形成 氮化矽層之溫度大約在400-8 00°C。並且，用來製造氮化矽 層所用的反應氣體爲SiH4，NH3，N2，N20或是SiH2Cl2, NH3，N2，N20。至於用來蝕刻氮化矽層之蝕刻劑可選擇 cf4/h2，chf3或ch3chf2。此外，其它介電材料，如氧化 较亦可作爲上述側壁間隙壁4 8之材料使用。 在形成側壁間隙壁48後，接著可利用閘極結構44作 爲罩冪，對半導體底材42進行離子植入程序，以形成作爲 源極、汲極結構之超淺接面（USJ)50於半導體底材42中。 然後，可使用遠距電漿源（RPS)方法，形成所需之蓋層52 於半導體底材42上，且覆蓋於閘極結構44、側壁間隙壁48 與超淺接面50上。其中如同上述，可使用遠距電漿氧化物 (RPO)、遠距電漿氮化物（RPN)與遠距電漿氮化氧化物 (RPNO)所組成之氮化材料層，來作爲所需之蓋層52。一般 而言，由於硼（boron)摻質較砷（arsenic)摻質爲輕，在進行熱 回火程序中，極易受到活化而向外擴散。是以僅使用遠距電 漿氧化物（RPO)來作爲蓋層52，往往無法有效的防止硼摻質 產生擴散效應。因此可使用遠距電漿源（RPS)之方法，形成 氮化材料來作爲蓋層’以便能更有效的提高蓋層52之阻障 能力。並且，由於使用遠距電漿源（RPS)來形成氮化材料蓋 層’所需之溫度僅約400至500 °C左右，是以不致於在形成 蓋層的同時，便活化位於超淺接面（USJ)中之摻質。 本紙張尺度適用中國國家標準（CNS ) Α4规格（210 X 297公釐） (請先閱讀背面之注意事項#填寫本頁) ,ιτ 經濟部智慧財產局員工消費合作社印製 4 6 1 0 2 4 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 接著’可對半導體底材42進行快速熱回火程序（rapid thermal procedure; RTP) ’以活化位於超淺接面（USJ)50中 之摻質，使其產生導電作用。同時，所進行之快速熱回火程 序，亦可修復在進行上述離子植入程序時，對半導體底材 42所造成之傷害。如此，可有效的控制所形成超淺接面中 摻質的擴散情形，且維持超淺接面之輪廓（pro file)。一般而 言，在進行快速熱回火程序之前，可根據後續相關製程的需 要，在半導體底材上先形成所需之各式元件（圖中並未顯 示）。是以，在進行快速熱回火程序畤，上述所形成之蓋層 52，將可有效的防止位於超淺接面中摻質向外擴散，而滲入 位於超淺接面週圍之其它元件。 本發明具有極多的優點。其中，藉著使用氮化材料來 作爲蓋層，可有效防止諸如硼原子等較輕的摻質，產生擴散 效應。此外，由於氮化材料蓋層是使用遠距電漿源（RPS)所 形成，是以其形成之溫度較低，如此可避免在製造蓋層時， 便激發且活化位於超淺接面中之摻質，而導致發生擴散效 應。 本發明雖以一較佳實例闡明如上，然其並非用以限定 本發明精神與發明實體，僅止於此一實施例爾。是以，在不 脫離本發明之精神與範圍內所作之修改，均應包含在下述之 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） 461024 A7 B7 五、發明説明（ 內圍 範 利 專 請申 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）、 1T This paper size applies the Chinese National Standard (.CNS) A4 specification (210X297 mm) 461024 A7 B7 V. Description of the invention () Chemical vapor deposition (PECVD) and other processes for deposition. Furthermore, the temperature at which the silicon nitride layer is formed is about 400-8 00 ° C. In addition, the reaction gas used to make the silicon nitride layer is SiH4, NH3, N2, N20 or SiH2Cl2, NH3, N2, N20. As for the etchant used to etch the silicon nitride layer, cf4 / h2, chf3 or ch3chf2 can be selected. In addition, other dielectric materials, such as oxidation, can also be used as the material of the above-mentioned sidewall spacers 48. After the sidewall spacer 48 is formed, the gate structure 44 can be used as a mask to perform an ion implantation process on the semiconductor substrate 42 to form a super shallow junction (USJ) 50 as a source and drain structure on the semiconductor. Substrate 42. Then, a remote plasma source (RPS) method can be used to form a desired capping layer 52 on the semiconductor substrate 42 and cover the gate structure 44, the sidewall spacer 48, and the super shallow junction 50. As mentioned above, a nitrided material layer composed of remote plasma oxide (RPO), remote plasma nitride (RPN), and remote plasma nitride oxide (RPNO) can be used as the required盖层 52。 Cover layer 52. In general, because boron dopants are lighter than arsenic dopants, they are highly susceptible to activation and diffuse outward during thermal tempering procedures. The use of only remote plasma oxide (RPO) as the capping layer 52 often fails to effectively prevent the diffusion effect of the boron dopant. Therefore, a remote plasma source (RPS) method can be used to form a nitride material as the capping layer 'in order to more effectively improve the barrier capability of the capping layer 52. In addition, because the remote plasma source (RPS) is used to form the capping layer of the nitride material, the temperature is only about 400 to 500 ° C, so that the super shallow contact is not activated while the capping layer is formed. Noodles (USJ). This paper size applies Chinese National Standard (CNS) Α4 specification (210 X 297 mm) (Please read the note on the back #Fill this page), printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives 4 6 1 0 2 4 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Then 'rapid thermal procedure (RTP) of the semiconductor substrate 42 can be performed' to activate the super shallow junction (USJ) Dopant in 50 makes it conductive. At the same time, the rapid thermal tempering process performed can also repair the damage to the semiconductor substrate 42 during the above-mentioned ion implantation process. In this way, it is possible to effectively control the diffusion of dopants in the formed super shallow junction and maintain the profile of the super shallow junction. Generally speaking, before the rapid thermal tempering process is performed, various required components can be formed on the semiconductor substrate according to the requirements of subsequent related processes (not shown in the figure). Therefore, during the rapid thermal tempering process, the capping layer 52 formed above can effectively prevent the dopants from diffusing out of the super shallow junction to penetrate into other components around the super shallow junction. The invention has many advantages. Among them, by using a nitride material as a capping layer, lighter dopants such as boron atoms can be effectively prevented from generating a diffusion effect. In addition, because the capping layer of nitride material is formed by using a remote plasma source (RPS), its formation temperature is lower, so that it can avoid the excitation and activation of the super shallow junction when the capping layer is manufactured. Dopant, which leads to diffusion effect. Although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the inventive substance of the present invention, but only to this embodiment. Therefore, the modifications made without departing from the spirit and scope of the present invention should be included in the following (please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (21 〇X297mm) 461024 A7 B7 V. Description of the invention (Inner Fan Li special application (please read the precautions on the back before filling this page) Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economics 4 This paper size applies to China Standard (CNS) A4 specification (210X297 mm)