TW440929B - Method for forming dielectric layer with a low dielectric constant - Google Patents
Method for forming dielectric layer with a low dielectric constant Download PDFInfo
- Publication number
- TW440929B TW440929B TW89105734A TW89105734A TW440929B TW 440929 B TW440929 B TW 440929B TW 89105734 A TW89105734 A TW 89105734A TW 89105734 A TW89105734 A TW 89105734A TW 440929 B TW440929 B TW 440929B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor substrate
- forming
- dielectric layer
- minutes
- patent application
- Prior art date
Links
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
440929 五、發明說明(i) 詳細說明: 技術領域: 本發明係關於一種在積體電路中形成低介電常數之介 電層的方法’特別是關於一種形成黑鑽石薄膜以做為低介 電常數介電層的方法β 發明背景: 為了追求更快的運作速率以及更大的集積密度,積體 電路之研究單位及製造業者無不竭盡心力地設計及製造關 鍵尺寸(Critical Dimension; CD)更小的元件。根據實驗 顯示,當積體電路的製程進入0.1 8微米甚至0.1 3微米的技 術領域之後,影響元件運作速秦的關鍵因素已從閘極的寬 度轉換至金屬内連線(metal interconnection)的電阻-電 容遲滯(RC delay)效應。 因導線的阻值與其截面積成反比,隨著積鳢電路之集 積密度的提高,金屬内連線的線寬和厚度都隨之縮小,因 此其阻值便隨之提高;尤有甚者,隨著積體電路之集積密 度的提高,亦使金屬内連線的線距隨之縮小,因而造成導 線之間的耦合電容升高。因此當積體電路的製程進入深次 微米領域之後’金屬内連線的電阻-電容遲滞大幅提高, 也因此影響積體電路的運算速率和存}速率。為了提高積 趙電路的集積密度,在線寬和線距都不宜提高的條件之 下,更換金屬内連線和層間介電層的材質是最佳的選擇^ 在金屬内連線方面’金屬材質由原先的鋁矽銅合金或銘鋼 合金換成銅金屬,除了具有低電阻的特性外,更具有良好440929 V. Description of the invention (i) Detailed description: Technical field: The present invention relates to a method for forming a dielectric layer with a low dielectric constant in an integrated circuit, and particularly to a method for forming a black diamond film as a low dielectric material. Method of constant dielectric layer β Background of the Invention: In order to pursue faster operating speed and greater integration density, research units and manufacturers of integrated circuits have endlessly devoted themselves to designing and manufacturing critical dimensions (CDs). Small components. According to experiments, when the integrated circuit manufacturing process enters the technical field of 0.1 8 microns or even 0.1 3 microns, the key factors affecting the speed of component operation have shifted from the width of the gate to the resistance of the metal interconnection- Capacitive hysteresis (RC delay) effect. Because the resistance value of a wire is inversely proportional to its cross-sectional area, as the accumulation density of the integrated circuit increases, the line width and thickness of the metal interconnects decrease, so the resistance value increases. In particular, With the increase of the integrated density of the integrated circuit, the line spacing of the metal interconnects is also reduced, thereby causing the coupling capacitance between the wires to increase. Therefore, when the manufacturing process of the integrated circuit enters the deep sub-micron field, the resistance-capacitance hysteresis of the metal interconnects is greatly improved, which also affects the operation rate and storage rate of the integrated circuit. In order to increase the accumulation density of the product circuit, under the condition that the line width and line spacing should not be increased, it is the best choice to replace the material of the metal interconnect and the interlayer dielectric layer. The original aluminum-silicon-copper alloy or Ming-steel alloy was replaced with copper metal.
第4頁 440929Page 4 440929
五、發明說明(2) 的抗電子遷移性和良好的抗應力性,除了可以提高 操作速率外,同時可以提升元件的可靠度;在另—方、 層間介電層則必須選擇低介電常數(Dielectric ’V. Description of the invention (2) The resistance to electron migration and good stress resistance, in addition to increasing the operation rate, can also improve the reliability of the component; in the other side, the interlayer dielectric layer must choose a low dielectric constant (Dielectric '
Constant)的材質以取代原有的二氧化矽,以降低金 連線之間的耦合電容。二氧化矽的介電常數約為3 9,因 此必須選取介電常數小於3. 9的介電質做為層間介電層, 方可達到降低電阻-電容遲滯的功效’例如:氟摻雜之二 氧化矽(Si 0F)、有機旋塗玻璃(HSQ)等等。另外—種有效 之低介電常數的材質為黑鎮石(black diamond),其係由 甲基矽烷(11^1;11715113116)所形成,其成分為矽2〇%、氧 30%、碳9%、氫36%、及其他元素。因黑鑽石約有36%的體 積為孔洞,因此其介電常數僅約為2. 9,是一種很具潛力 的低介電常數材質。 在銅製程的技術中,因銅金屬無法如同鋁合金一般用 氣氣進行钱刻,因此業界發展出一種鑲嵌(damascene)的 製程方法。鑲嵌的製程技術可參考Mo tor 〇 la公司Boeck;Constant) material to replace the original silicon dioxide to reduce the coupling capacitance between the gold connections. The dielectric constant of silicon dioxide is about 39, so a dielectric with a dielectric constant less than 3.9 must be selected as the interlayer dielectric layer to achieve the effect of reducing the resistance-capacitance hysteresis. For example: fluorine-doped Silicon dioxide (Si 0F), organic spin-on glass (HSQ), etc. In addition, an effective low-dielectric constant material is black diamond, which is formed by methyl silane (11 ^ 1; 11715113116). Its composition is 20% silicon, 30% oxygen, and carbon 9 %, Hydrogen 36%, and other elements. Because about 36% of the volume of black diamonds is pores, its dielectric constant is only about 2.9, which is a very low-dielectric constant material with great potential. In copper process technology, because copper metal cannot be engraved with gas like aluminum alloy, the industry has developed a damascene process method. For inlaying process technology, please refer to Motorola Corporation's Boeck;
Bruce Allen等人在美國專利第588001 8號所揭露之 "Method for manufacturing a low dielectric constant inter-level integrated circuit structure"。請參考圖一,在一已完成前段製程的半導體 基板10上連續形成第一氮化矽層11、第一低介電常數介電 層12、第二氮化矽層13、和第二低介電常數介電層14,再 以連續兩道微影與蝕刻技術形成如圖一 A之開口 1 5。接下 來請參考圖一 B,以PVD、CVD、或電鍍方法形成一層銅薄"Method for manufacturing a low dielectric constant inter-level integrated circuit structure" disclosed by Bruce Allen et al. In U.S. Patent No. 588001 8. Please refer to FIG. 1, a first silicon nitride layer 11, a first low-k dielectric layer 12, a second silicon nitride layer 13, and a second low-dielectric layer are continuously formed on a semiconductor substrate 10 that has completed a previous process. The dielectric constant dielectric layer 14 is formed by two successive lithography and etching techniques, as shown in FIG. 1A. Next, please refer to Figure 1B. A layer of copper is formed by PVD, CVD, or electroplating.
第5頁 4 4092 9 五、發明說明(3) 膜16。最後如圖一 C所示,利周化學機械研磨法(Chemical Mechanical Pol i shi ng; CMP)對所述銅薄膜1 6進行研磨, 以形成銅導線1 7。 在傳統的技術上,當選用黑鑽石做為低介電常數介電 層時,黑鑽石薄膜的沉積必須分為三個步驟。如圖二所示 之製程流程圖’首先利用化學汽相沉積法(CVD)形成黑 鑽石薄膜21;接著將半導體基板送入爐管令’在攝氏200 度的溫度下通入氧氣以進行穩定化製程 (stabilizati〇n)22;最後將半導體基板送入爐管中,在 攝氏40 0度的溫度下通入氮氣以進行固化製程(cure)23e 其中步驟2 2所述的穩定化製程必須在爐管中進行4 0分鐘, 若再加上升溫和降溫的過程,所耗的時間超過2小時,不 僅降低產量,也使製造的成本提高(因爐管在1C廢中屬昂 貴的機台再者’因為穩定化製程必須在攝氏20 0度的 溫度下進行,也將提高製程的熱預算(thermal budget)。 因此’發展出一種用以取代穩定化製程22的製程,以提高 產量、降低製造成本、並且降低熱預算,便成為半導體業 界亟待解決的問題。 發明概述: 本發明的主要目的為提供一種形成低介電常數之介電 層的方法。 本發明的次要目的為提供一種形成黑鑽石薄膜以做為 低介電常數介電層的方法βPage 5 4 4092 9 V. Description of the invention (3) Membrane 16. Finally, as shown in FIG. 1C, the copper thin film 16 is polished by a chemical mechanical polishing method (CMP) to form a copper wire 17. Traditionally, when black diamond is selected as the low-k dielectric layer, the black diamond film deposition must be divided into three steps. The process flow chart shown in Figure 2 'Firstly, the black diamond film 21 is formed by chemical vapor deposition (CVD); then the semiconductor substrate is sent to the furnace tube' and oxygen is introduced at 200 ° C for stabilization. Process (stabilizati〇n) 22; Finally, the semiconductor substrate is sent into the furnace tube, and nitrogen is introduced at a temperature of 40 degrees Celsius to perform a curing process (cure) 23e. For 40 minutes in the tube, if the process of heating and cooling is added, it takes more than 2 hours, which not only reduces the output, but also increases the manufacturing cost (because the furnace tube is an expensive machine in the 1C waste) Because the stabilization process must be performed at a temperature of 200 degrees Celsius, the thermal budget of the process will also be increased. Therefore, a process to replace the stabilization process 22 has been developed to increase production, reduce manufacturing costs, And reducing the thermal budget has become an urgent problem to be solved in the semiconductor industry. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a method for forming a dielectric layer with a low dielectric constant. The present invention The method of β secondary objective is to provide a thin film formed as Black Diamond low-k dielectric layer
440929 五、發明說明(4) 本發明係揭露一種形成低介電常數之介電層的方法, 在一半導體基板上形成黑鑽石薄膜,其步驟包括有:首先 利用化學汽相沉積法在所述半導體基板上沉積一層黑鑽石 薄膜。接下來進行穩定化製程’將所述半導體基板放入攝 氏7 0度至1 0 0度的去離子水中浸泡1 5至3 0分鐘;或者將所 述半導體基板放入室溫的5-20%雙氧水中浸泡1〇至6〇分 鐘。最後將所述半導體基板放入爐管中,在攝氏4〇〇度的 溫度下通入氮氣進行20至40分鐘,以形成黑鑽石薄膜。 本發明以清洗槽的浸泡製程來取代習知技藝之高溫穩 定化製程。比起習知技藝需在攝氏2〇〇度的爐管中行^". 定化製程,本發明製程所需的時間較短,以較便宜 二 槽製程取代爐管’同時本發明浸泡製程所需的溫低' 可以降低產品的熱預算,提高產品的良率和可 $权似 本發明所形成之黑鑽石薄膜的介電啻 和習知技藝所得結果相ϋ,顯示在穩定化都 揭露的浸泡製程確實可以取代習知技藝的:J::所 此外,本發明各實施例所得之平坦能帶電壓 $管製程。 voltage)的絕對值遠較習知技藝為低, at~band 電流(leakage current),大幅提高元件的^于^較低的漏 藉由調整本發明之浸泡製程的參數,例如浸泡& °/外’ 溫度、以及浸泡時間,可以調整所形成之爱脖^, 電常數’對元件的設計和應用有極大的助益。薄膜的介 圖式的簡要說明:440929 V. Description of the invention (4) The present invention discloses a method for forming a dielectric layer with a low dielectric constant. A black diamond film is formed on a semiconductor substrate. The steps include: firstly, using a chemical vapor deposition method in the A black diamond film is deposited on the semiconductor substrate. Next, the stabilization process is performed. The semiconductor substrate is immersed in deionized water at 70 to 100 degrees Celsius for 15 to 30 minutes; or the semiconductor substrate is placed at 5-20% of room temperature. Soak in hydrogen peroxide for 10 to 60 minutes. Finally, the semiconductor substrate is put into a furnace tube, and nitrogen gas is introduced at a temperature of 400 degrees Celsius for 20 to 40 minutes to form a black diamond film. In the present invention, the soaking process of the cleaning tank is used instead of the high-temperature stabilization process of the conventional technique. Compared with the conventional technique, which needs to be performed in a furnace tube at 200 degrees Celsius, the process of the present invention requires less time, and the furnace tube is replaced by a cheaper two-tank process. The required low temperature can reduce the thermal budget of the product, increase the yield of the product, and compare the results of the dielectric properties of the black diamond film formed by the present invention and the results obtained from conventional techniques, which are revealed in the stabilization. The immersion process can indeed replace the conventional technique: J :: In addition, the flat energy band voltage control process obtained by the embodiments of the present invention. The absolute value of voltage) is much lower than that of conventional techniques. The at ~ band current (leakage current) greatly improves the low leakage of the component by adjusting the parameters of the immersion process of the present invention, such as immersion & ° / The external temperature and immersion time can be adjusted to form the love neck ^, the electrical constant 'is of great help to the design and application of components. Brief description of the film's media:
第7頁 t:::' - Ο 9 P α 五、發明說明(5) 圖一 A是習知雙鑲嵌製程中在一已完成前段製程的半導體 基板上連績形成第一氮化矽層、第一低介電常數介電層、 第二氮化矽層、和第二低介電常數介電層,再以連續兩道 微影與蝕刻技術形成開口之製程的剖面示意圖。 圖一 B是習知雙鑲嵌製程中形成一層銅薄膜之製程的剖面 示意圖。 圖一 C是是習知雙鑲嵌製程中利用化學機械研磨法對所述 銅薄膜進行研磨,以形成銅導線之製程的剖面示意圖。 圖二是習知技術中形成黑鑽石薄膜之製程流程圖。 圖三是本發明第一實施例中形成黑鑽石薄膜之製程流程 圖。 圖四是本發明第二實施例中形成黑鑽石薄膜之製程流程 圖。 圖號說明 1 0 -半導體基板 1卜第一氮化矽層 12- 第一低介電常數介電層 13- 第二氮化矽層 14- 第二低介電常數介電層 1 5 -開口 1 6 -銅薄膜 1 7 -銅導線Page 7 t ::: '-Ο 9 P α V. Description of the invention (5) Figure 1A is a conventional double damascene process in which a first silicon nitride layer is successively formed on a semiconductor substrate that has completed the previous process. A schematic cross-sectional view of a process of forming a first low-k dielectric layer, a second silicon nitride layer, and a second low-k dielectric layer, and then using two successive lithography and etching techniques to form an opening. FIG. 1B is a schematic cross-sectional view of a process for forming a copper film in a conventional dual damascene process. FIG. 1C is a schematic cross-sectional view of a process for forming a copper wire by grinding the copper film by a chemical mechanical polishing method in a conventional dual damascene process. FIG. 2 is a flow chart of a process for forming a black diamond film in the conventional technology. Fig. 3 is a flow chart of a process for forming a black diamond film in the first embodiment of the present invention. Fig. 4 is a flow chart of a process for forming a black diamond film in the second embodiment of the present invention. Description of Drawing Numbers 10-Semiconductor substrate 1 First silicon nitride layer 12-First low dielectric constant dielectric layer 13-Second silicon nitride layer 14-Second low dielectric constant dielectric layer 1 5-Opening 1 6-copper film 1 7-copper wire
第8頁 44〇92 9 五、發明說明(6) - 本發明係揭露一種形成低介電常數之介電層的方法, 特別是關於一種形成黑鑽石薄膜以做為低介電常數介電層 的方法。本發明可適用於各種型態之邏輯元件及記憶體元 件的銅製程。 本發明第一實施例的製程流程圈請參閱圖三,首先利 用化學汽相沉積法形成黑鑽石薄臈31;接著將半導體基板 在攝氏7 0度至1 〇 〇度的去離子水中浸泡丨5至3 〇分鐘3 2 ;最 後將半導體基板送入爐管中,在攝氏4〇〇度的溫度下通入 氣氣以進行固化製程(cure)33。Page 8 44〇92 9 V. Description of the invention (6)-The present invention discloses a method for forming a dielectric layer with a low dielectric constant, in particular, a method for forming a black diamond film as a low dielectric constant dielectric layer Methods. The invention can be applied to copper processes of logic elements and memory elements of various types. Please refer to FIG. 3 for the manufacturing process circle of the first embodiment of the present invention. First, a black diamond thin cymbal 31 is formed by a chemical vapor deposition method; then, a semiconductor substrate is immersed in deionized water at 70 to 100 ° C. To 30 minutes 3 2; finally, the semiconductor substrate is sent into a furnace tube, and a gas is passed at a temperature of 400 degrees Celsius to perform a cure process 33.
其中步驟3 1係以電漿增強式化學汽相沉積法(pECVD )在攝氏1 5度至攝氏2 0度的低溫下進行。在步驟3 2的浸泡 製程中’最佳的製程參數是將半導體基板在攝氏9〇度的去 離子水中浸泡2 0分鐘。在步驟3 3的固化製程中,較佳的製 程時間為2 0至4 0分鐘’最佳的製程時間約為3 〇分鐘。 此外’本實施例之步驟3 2的浸泡製程,亦可改為將半導體 基板在室溫的去離子水中浸泡2 4小時,可以達到相同的功 效。 本發明第二實施例的製程流程圖請參閱圖四,首先利 用化學汽相沉積法形成黑鑽石薄膜41;接著將半導體基板 在室溫下的雙氧水中浸泡丨〇至6〇分鐘42 ;最後將半導體基 板送入爐管中,在攝氏4 00度的溫度下通入氮氣以進行固 化製程4 3。 其中步驟41係以電漿增強式化學汽相沉積法(pECVD )在攝氏15度至攝氏2 0度的低溫下進行。在步驟4 2的浸泡Step 31 is performed by a plasma enhanced chemical vapor deposition method (pECVD) at a low temperature of 15 ° C to 20 ° C. In the soaking process of step 32, the best process parameter is to soak the semiconductor substrate in deionized water at 90 degrees Celsius for 20 minutes. In the curing process of step 33, the preferred process time is 20 to 40 minutes', and the optimal process time is about 30 minutes. In addition, the soaking process of step 32 in this embodiment may be changed to immersing the semiconductor substrate in deionized water at room temperature for 24 hours, which can achieve the same effect. Please refer to FIG. 4 for a process flow chart of the second embodiment of the present invention. First, a black diamond thin film 41 is formed by a chemical vapor deposition method; then the semiconductor substrate is immersed in hydrogen peroxide at room temperature for 0 to 60 minutes 42; finally, The semiconductor substrate is sent into a furnace tube, and nitrogen gas is passed at a temperature of 400 degrees Celsius to perform a curing process 43. Step 41 is performed by a plasma enhanced chemical vapor deposition method (pECVD) at a low temperature of 15 ° C to 20 ° C. Soak in step 4 2
第9頁 .440929 五 '發明說明(7) 製程中,最佳的製程參數是將半導體基板在5~20%的雙氧 水中在室溫下浸泡15分鐘。在步帮4 3的固化製程中,較佳 的製程時間為2 0至4 0分鐘’最佳的製程時間约為3 0分鐘》 由上述說明及圖三和圖四之流程圊可以得知,本發明以清 洗槽的浸泡製程來取代習知技藝之高溫穩定化製程,比起 習知技藝需在攝氏20 0度的爐管中進行穩定化製程,前後 費時2小時,本發明製程所需的時間較短,並且可以同時 浸泡數批晶片’大幅提升低介電常數薄膜製程的產量;同 時因爐管在1C座中屬於較昂貴的機台,高溫爐管製程所需 的成本甚高,本發明以較便宜的清洗槽製程取代壚管,可 ί大幅降低製程的成本;同時本發明浸泡製程所需的溫度較 低’可以降低產品的熱預算’提高產品的良率和可靠度。 本發明之製程結果和習知技藝之製程結果的比較請參閱表 穩定化製程 介電常數 平坦能帶電壓 折射係數 習知技藝 3.10 -41.0 V 1.421 (爐管通氧氣200°C) 本發明第一實施例 2.99 -11.0 V 1.440 (90°CDI水浸泡20分鐘) 本發明第二實施例 3.08 -1.9 V 1.429 (室溫雙氧水浸泡15分鐘) 本發明第二實施例 3.46 -0.5V 1.447 (室溫雙氧水浸泡60分鐘) 表一Page 9 .440929 Five 'Invention description (7) In the process, the best process parameter is to soak the semiconductor substrate in 5 ~ 20% hydrogen peroxide at room temperature for 15 minutes. In the curing process of Step 4 3, the preferred process time is 20 to 40 minutes. The optimal process time is about 30 minutes. "From the above description and the processes in Figures 3 and 4, we can know that The invention replaces the high-temperature stabilization process of the conventional technique with the immersion process of the cleaning tank. Compared with the conventional technique, the stabilization process needs to be performed in a furnace tube at 200 degrees Celsius, which takes 2 hours before and after. The time is short, and several batches of wafers can be immersed at the same time, which greatly increases the output of the low dielectric constant thin film process; at the same time, because the furnace tube is a more expensive machine in the 1C block, the cost of the high-temperature furnace control process is very high. The invention replaces the stern tube with a cheaper cleaning tank process, which can greatly reduce the cost of the process; at the same time, the temperature required for the immersion process of the present invention is lower, which can reduce the thermal budget of the product, and improve the yield and reliability of the product. For comparison between the process results of the present invention and the process results of the conventional technique, please refer to the table for stabilizing the process, the dielectric constant, the flat band voltage, and the refractive index of the conventional technique. Example 2.99 -11.0 V 1.440 (90 ° C DI water immersion for 20 minutes) The second embodiment of the present invention 3.08 -1.9 V 1.429 (room temperature hydrogen peroxide soaked for 15 minutes) The second embodiment of the present invention 3.46 -0.5V 1.447 (room temperature hydrogen peroxide Soak for 60 minutes) Table 1
ΗΒΗ HI 第ίο頁 ο 9 2 9 五、發明說明(8) 如表一所示,本發明之第一實施例和第二實施例所得 到的介電常數和折射係數都和習知技藝所得結果相近,顯 示在穩定化製程中本發明所揭露的浸泡製程確實可以取代 習知技藝的高溫爐管製程。此外,本發明各實施例所得之 平坦能帶電壓(flat-band voltage)的絕對值遠較習知技 藝為低,可以得到較低的漏電流,大幅提高元件的性能。 另外,本發明有一項相當重要的優點,由表一之實驗以及 其他的實驗可知,藉由調整本發明之浸泡製程的參數,例 如浸泡液體、浸泡溫度、以及浸泡時間,便可以調整所形 成之黑鑽石薄膜的介電常數,對元件的設計和應用有極大 的助益。 以上所述係利用較佳實施例詳細說明本發明,而非限 制本發明的範圍,而且熟知此技藝的人士亦能明瞭,適當 而作些微的改變與調整,仍將不失本發明之要義所在,亦 不脫離本發明之精神和範圍。ΗΒΗ HI Page ίοο 9 2 9 V. Description of the invention (8) As shown in Table 1, the dielectric constant and refractive index obtained by the first and second embodiments of the present invention are both the results obtained by the conventional techniques Similarly, it is shown that the immersion process disclosed in the present invention can indeed replace the conventional high-temperature furnace control process in the stabilization process. In addition, the absolute value of the flat-band voltage obtained by the embodiments of the present invention is much lower than that of the conventional technology, a lower leakage current can be obtained, and the performance of the device is greatly improved. In addition, the present invention has a very important advantage. From the experiments in Table 1 and other experiments, it can be known that by adjusting the parameters of the immersion process of the present invention, such as immersion liquid, immersion temperature, and immersion time, the formed The dielectric constant of the black diamond film is of great help to the design and application of components. The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention, and those skilled in the art will also understand that making small changes and adjustments appropriately will still lose the essence of the present invention. Without departing from the spirit and scope of the invention.
第11頁 t'" 4 4 0 9 2 9 圖式簡單說明 圖式的簡要說明: 圖一 A是習知雙鑲嵌製程中在一已完成前段製程的半導體 基板上連續形成第一氮化矽層、第一低介電常數介電層、 第二氮化矽層、和第二低介電常數介電層,再以連續兩道 微影與蝕刻技術形成開口之製程的剖面示意圖。 圖一 B是習知雙鑲嵌製程中形成一層銅薄膜之製程的剖面 示意圖。 圖一 C是是習知雙鑲嵌製程中利用化學機械研磨法對所述 銅薄膜進行研磨,以形成銅導線之製程的剖面示意圖。 圖二是習知技術中形成黑鑽石薄膜之製程流程圖。 圖三是本發明第一實施例中形成黑鑽石薄臈之製程流程 圖。 圖四是本發明第二實施例中形成黑鑽石薄膜之製程流程 圖。Page 11 t '" 4 4 0 9 2 9 Brief description of the diagram Brief description of the diagram: Figure 1A is a conventional dual damascene process in which a first silicon nitride is continuously formed on a semiconductor substrate that has completed the previous process Layer, the first low-k dielectric layer, the second silicon nitride layer, and the second low-k dielectric layer, and then the process of forming an opening by two successive lithography and etching techniques is shown. FIG. 1B is a schematic cross-sectional view of a process for forming a copper film in a conventional dual damascene process. FIG. 1C is a schematic cross-sectional view of a process for forming a copper wire by grinding the copper film by a chemical mechanical polishing method in a conventional dual damascene process. FIG. 2 is a flow chart of a process for forming a black diamond film in the conventional technology. FIG. 3 is a flow chart of a process for forming a black diamond thin bead in the first embodiment of the present invention. Fig. 4 is a flow chart of a process for forming a black diamond film in the second embodiment of the present invention.
第12頁Page 12
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW89105734A TW440929B (en) | 2000-03-29 | 2000-03-29 | Method for forming dielectric layer with a low dielectric constant |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW89105734A TW440929B (en) | 2000-03-29 | 2000-03-29 | Method for forming dielectric layer with a low dielectric constant |
Publications (1)
Publication Number | Publication Date |
---|---|
TW440929B true TW440929B (en) | 2001-06-16 |
Family
ID=21659235
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW89105734A TW440929B (en) | 2000-03-29 | 2000-03-29 | Method for forming dielectric layer with a low dielectric constant |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW440929B (en) |
-
2000
- 2000-03-29 TW TW89105734A patent/TW440929B/en not_active IP Right Cessation
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4090740B2 (en) | Integrated circuit manufacturing method and integrated circuit | |
US5900290A (en) | Method of making low-k fluorinated amorphous carbon dielectric | |
US6919270B2 (en) | Method of manufacturing silicon carbide film | |
US7314838B2 (en) | Method for forming a high density dielectric film by chemical vapor deposition | |
KR100887225B1 (en) | Semiconductor device manufacturing method | |
TW200524042A (en) | Structures with improved interfacial strength of sicoh dielectrics and method for preparing the same | |
JP4548280B2 (en) | Manufacturing method of semiconductor device | |
JP2005033203A (en) | Method for forming silicon carbide film | |
JP3698885B2 (en) | Method for manufacturing device using ferroelectric film | |
TWI295485B (en) | Method of improving low-k film property and damascene process using the same | |
JP4034227B2 (en) | Manufacturing method of semiconductor device | |
JPH10340899A (en) | Silica insulation film and semiconductor device, and manufacturing method thereof | |
TW200407979A (en) | Method of manufacturing low K layer | |
US20050153533A1 (en) | Semiconductor manufacturing method and semiconductor manufacturing apparatus | |
JP2007227958A (en) | Semiconductor device | |
TW440929B (en) | Method for forming dielectric layer with a low dielectric constant | |
JP4223012B2 (en) | Insulating film forming method, multilayer structure forming method, and semiconductor device manufacturing method | |
US7253121B2 (en) | Method for forming IMD films | |
TW588432B (en) | Manufacturing process for surface modification of dielectric layer | |
TW465031B (en) | Copper manufacture process for semiconductor | |
JP3843275B2 (en) | Manufacturing method of semiconductor device | |
TW447075B (en) | Method for forming dielectric layer with low dielectric constant | |
Jiang et al. | Recent patents on Cu/low-k dielectrics interconnects in integrated circuits | |
Yin et al. | Structure characterization of HSQ films for low dielectrics uses D4 as sacrificial porous materials | |
TW563186B (en) | Surface treatment method of low dielectric constant material |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MK4A | Expiration of patent term of an invention patent |